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1; RUN: llc -mtriple=riscv32 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \2; RUN: grep -v "Verify generated machine code" | \3; RUN: FileCheck %s --check-prefixes=CHECK4; RUN: llc -mtriple=riscv64 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \5; RUN: grep -v "Verify generated machine code" | \6; RUN: FileCheck %s --check-prefixes=CHECK,RV647 8; REQUIRES: asserts9 10; CHECK-LABEL: Pass Arguments:11; CHECK-NEXT: Target Library Information12; CHECK-NEXT: Target Pass Configuration13; CHECK-NEXT: Machine Module Information14; CHECK-NEXT: Target Transform Information15; CHECK-NEXT: Assumption Cache Tracker16; CHECK-NEXT: Profile summary info17; CHECK-NEXT: Type-Based Alias Analysis18; CHECK-NEXT: Scoped NoAlias Alias Analysis19; CHECK-NEXT: Create Garbage Collector Module Metadata20; CHECK-NEXT: Machine Branch Probability Analysis21; CHECK-NEXT: Default Regalloc Eviction Advisor22; CHECK-NEXT: Default Regalloc Priority Advisor23; CHECK-NEXT: ModulePass Manager24; CHECK-NEXT: Pre-ISel Intrinsic Lowering25; CHECK-NEXT: FunctionPass Manager26; CHECK-NEXT: Expand large div/rem27; CHECK-NEXT: Expand fp28; CHECK-NEXT: Expand Atomic instructions29; CHECK-NEXT: RISC-V Zacas ABI fix 30; CHECK-NEXT: Dominator Tree Construction31; CHECK-NEXT: Natural Loop Information32; CHECK-NEXT: Canonicalize natural loops33; CHECK-NEXT: Lazy Branch Probability Analysis34; CHECK-NEXT: Lazy Block Frequency Analysis35; CHECK-NEXT: Optimization Remark Emitter36; CHECK-NEXT: Scalar Evolution Analysis37; CHECK-NEXT: Loop Data Prefetch38; CHECK-NEXT: RISC-V gather/scatter lowering39; CHECK-NEXT: Interleaved Access Pass40; CHECK-NEXT: RISC-V CodeGenPrepare41; CHECK-NEXT: Module Verifier42; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)43; CHECK-NEXT: Canonicalize natural loops44; CHECK-NEXT: Scalar Evolution Analysis45; CHECK-NEXT: Loop Pass Manager46; CHECK-NEXT: Canonicalize Freeze Instructions in Loops47; CHECK-NEXT: Induction Variable Users48; CHECK-NEXT: Loop Strength Reduction49; CHECK-NEXT: Loop Terminator Folding50; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)51; CHECK-NEXT: Function Alias Analysis Results52; CHECK-NEXT: Merge contiguous icmps into a memcmp53; CHECK-NEXT: Natural Loop Information54; CHECK-NEXT: Lazy Branch Probability Analysis55; CHECK-NEXT: Lazy Block Frequency Analysis56; CHECK-NEXT: Expand memcmp() to load/stores57; CHECK-NEXT: Lower Garbage Collection Instructions58; CHECK-NEXT: Shadow Stack GC Lowering59; CHECK-NEXT: Remove unreachable blocks from the CFG60; CHECK-NEXT: Natural Loop Information61; CHECK-NEXT: Post-Dominator Tree Construction62; CHECK-NEXT: Branch Probability Analysis63; CHECK-NEXT: Block Frequency Analysis64; CHECK-NEXT: Constant Hoisting65; CHECK-NEXT: Replace intrinsics with calls to vector library66; CHECK-NEXT: Lazy Branch Probability Analysis67; CHECK-NEXT: Lazy Block Frequency Analysis68; CHECK-NEXT: Optimization Remark Emitter69; CHECK-NEXT: Partially inline calls to library functions70; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)71; CHECK-NEXT: Scalarize Masked Memory Intrinsics72; CHECK-NEXT: Expand reduction intrinsics73; CHECK-NEXT: Natural Loop Information74; CHECK-NEXT: Type Promotion75; CHECK-NEXT: CodeGen Prepare76; CHECK-NEXT: Dominator Tree Construction77; CHECK-NEXT: Exception handling preparation78; CHECK-NEXT: RISC-V Promote Constants79; CHECK-NEXT: A No-Op Barrier Pass80; CHECK-NEXT: FunctionPass Manager81; CHECK-NEXT: Merge internal globals82; CHECK-NEXT: Dominator Tree Construction83; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)84; CHECK-NEXT: Function Alias Analysis Results85; CHECK-NEXT: ObjC ARC contraction86; CHECK-NEXT: Prepare callbr87; CHECK-NEXT: Safe Stack instrumentation pass88; CHECK-NEXT: Insert stack protectors89; CHECK-NEXT: Module Verifier90; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)91; CHECK-NEXT: Function Alias Analysis Results92; CHECK-NEXT: Natural Loop Information93; CHECK-NEXT: Post-Dominator Tree Construction94; CHECK-NEXT: Branch Probability Analysis95; CHECK-NEXT: Assignment Tracking Analysis96; CHECK-NEXT: Lazy Branch Probability Analysis97; CHECK-NEXT: Lazy Block Frequency Analysis98; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection99; CHECK-NEXT: Finalize ISel and expand pseudo-instructions100; CHECK-NEXT: RISC-V Vector Peephole Optimization101; CHECK-NEXT: RISC-V Fold Memory Offset102; CHECK-NEXT: Lazy Machine Block Frequency Analysis103; CHECK-NEXT: Early Tail Duplication104; CHECK-NEXT: Optimize machine instruction PHIs105; CHECK-NEXT: Slot index numbering106; CHECK-NEXT: Merge disjoint stack slots107; CHECK-NEXT: Local Stack Slot Allocation108; CHECK-NEXT: Remove dead machine instructions109; CHECK-NEXT: MachineDominator Tree Construction110; CHECK-NEXT: Machine Natural Loop Construction111; CHECK-NEXT: Machine Trace Metrics 112; CHECK-NEXT: Lazy Machine Block Frequency Analysis 113; CHECK-NEXT: Machine InstCombiner 114; CHECK-NEXT: Machine Block Frequency Analysis115; CHECK-NEXT: Early Machine Loop Invariant Code Motion116; CHECK-NEXT: MachineDominator Tree Construction117; CHECK-NEXT: Machine Block Frequency Analysis118; CHECK-NEXT: Machine Common Subexpression Elimination119; CHECK-NEXT: MachinePostDominator Tree Construction120; CHECK-NEXT: Machine Cycle Info Analysis121; CHECK-NEXT: Machine code sinking122; CHECK-NEXT: Peephole Optimizations123; CHECK-NEXT: Remove dead machine instructions124; RV64-NEXT: RISC-V Optimize W Instructions125; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass126; CHECK-NEXT: RISC-V Merge Base Offset127; CHECK-NEXT: MachineDominator Tree Construction128; CHECK-NEXT: RISC-V VL Optimizer129; CHECK-NEXT: RISC-V pre-allocation Zilsd load/store optimization130; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass131; CHECK-NEXT: RISC-V Insert Write VXRM Pass132; CHECK-NEXT: RISC-V Landing Pad Setup133; CHECK-NEXT: RISC-V VMV0 Elimination134; CHECK-NEXT: Detect Dead Lanes135; CHECK-NEXT: Init Undef Pass136; CHECK-NEXT: Process Implicit Definitions137; CHECK-NEXT: Remove unreachable machine basic blocks138; CHECK-NEXT: Live Variable Analysis139; CHECK-NEXT: Eliminate PHI nodes for register allocation140; CHECK-NEXT: Two-Address instruction pass141; CHECK-NEXT: Slot index numbering142; CHECK-NEXT: Live Interval Analysis143; CHECK-NEXT: Register Coalescer144; CHECK-NEXT: Rename Disconnected Subregister Components145; CHECK-NEXT: Machine Instruction Scheduler146; CHECK-NEXT: Machine Block Frequency Analysis147; CHECK-NEXT: Debug Variable Analysis148; CHECK-NEXT: Live Stack Slot Analysis149; CHECK-NEXT: Virtual Register Map150; CHECK-NEXT: Live Register Matrix151; CHECK-NEXT: Bundle Machine CFG Edges152; CHECK-NEXT: Spill Code Placement Analysis153; CHECK-NEXT: Lazy Machine Block Frequency Analysis154; CHECK-NEXT: Machine Optimization Remark Emitter155; CHECK-NEXT: Greedy Register Allocator156; CHECK-NEXT: Virtual Register Rewriter157; CHECK-NEXT: RISC-V Insert VSETVLI pass158; CHECK-NEXT: RISC-V Dead register definitions159; CHECK-NEXT: Virtual Register Map160; CHECK-NEXT: Live Register Matrix161; CHECK-NEXT: Greedy Register Allocator162; CHECK-NEXT: Virtual Register Rewriter163; CHECK-NEXT: Register Allocation Pass Scoring164; CHECK-NEXT: Stack Slot Coloring165; CHECK-NEXT: Machine Copy Propagation Pass166; CHECK-NEXT: Machine Loop Invariant Code Motion167; CHECK-NEXT: RISC-V Redundant Copy Elimination168; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis169; CHECK-NEXT: Fixup Statepoint Caller Saved170; CHECK-NEXT: PostRA Machine Sink171; CHECK-NEXT: MachineDominator Tree Construction172; CHECK-NEXT: Machine Natural Loop Construction173; CHECK-NEXT: Machine Block Frequency Analysis174; CHECK-NEXT: MachinePostDominator Tree Construction175; CHECK-NEXT: Lazy Machine Block Frequency Analysis176; CHECK-NEXT: Machine Optimization Remark Emitter177; CHECK-NEXT: Shrink Wrapping analysis178; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization179; CHECK-NEXT: Machine Late Instructions Cleanup Pass180; CHECK-NEXT: Control Flow Optimizer181; CHECK-NEXT: Lazy Machine Block Frequency Analysis182; CHECK-NEXT: Tail Duplication183; CHECK-NEXT: Machine Copy Propagation Pass184; CHECK-NEXT: Post-RA pseudo instruction expansion pass185; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass186; CHECK-NEXT: Insert KCFI indirect call checks187; CHECK-NEXT: RISC-V Load / Store Optimizer188; CHECK-NEXT: MachineDominator Tree Construction189; CHECK-NEXT: Machine Natural Loop Construction190; CHECK-NEXT: PostRA Machine Instruction Scheduler191; CHECK-NEXT: Analyze Machine Code For Garbage Collection192; CHECK-NEXT: Machine Block Frequency Analysis193; CHECK-NEXT: MachinePostDominator Tree Construction194; CHECK-NEXT: Branch Probability Basic Block Placement195; CHECK-NEXT: Insert fentry calls196; CHECK-NEXT: Insert XRay ops197; CHECK-NEXT: Implement the 'patchable-function' attribute198; CHECK-NEXT: Machine Copy Propagation Pass199; CHECK-NEXT: RISC-V Late Branch Optimisation Pass200; CHECK-NEXT: RISC-V Indirect Branch Tracking201; CHECK-NEXT: Branch relaxation pass202; CHECK-NEXT: RISC-V Make Compressible203; CHECK-NEXT: Contiguously Lay Out Funclets204; CHECK-NEXT: Remove Loads Into Fake Uses205; CHECK-NEXT: StackMap Liveness Analysis206; CHECK-NEXT: Live DEBUG_VALUE analysis207; CHECK-NEXT: Machine Sanitizer Binary Metadata208; CHECK-NEXT: Machine Outliner209; CHECK-NEXT: FunctionPass Manager210; CHECK-NEXT: Insert CFI remember/restore state instructions211; CHECK-NEXT: Lazy Machine Block Frequency Analysis212; CHECK-NEXT: Machine Optimization Remark Emitter213; CHECK-NEXT: Stack Frame Layout Analysis214; CHECK-NEXT: RISC-V Zcmp move merging pass215; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass216; CHECK-NEXT: RISC-V pseudo instruction expansion pass217; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass218; CHECK-NEXT: Unpack machine instruction bundles219; CHECK-NEXT: Lazy Machine Block Frequency Analysis220; CHECK-NEXT: Machine Optimization Remark Emitter221; CHECK-NEXT: RISC-V Assembly Printer222; CHECK-NEXT: Free MachineFunction223