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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=ZBB,RV32ZBB5; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=ZBB,RV64ZBB6;7; trunc(nabs(sub(sext(a),sext(b)))) -> nabds(a,b)8;9 10define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {11; RV32I-LABEL: abd_ext_i8:12; RV32I: # %bb.0:13; RV32I-NEXT: slli a1, a1, 2414; RV32I-NEXT: slli a0, a0, 2415; RV32I-NEXT: srai a1, a1, 2416; RV32I-NEXT: srai a0, a0, 2417; RV32I-NEXT: sub a0, a0, a118; RV32I-NEXT: srai a1, a0, 3119; RV32I-NEXT: xor a0, a0, a120; RV32I-NEXT: sub a0, a1, a021; RV32I-NEXT: ret22;23; RV64I-LABEL: abd_ext_i8:24; RV64I: # %bb.0:25; RV64I-NEXT: slli a0, a0, 5626; RV64I-NEXT: slli a1, a1, 5627; RV64I-NEXT: srai a0, a0, 5628; RV64I-NEXT: srai a1, a1, 5629; RV64I-NEXT: sub a0, a0, a130; RV64I-NEXT: srai a1, a0, 6331; RV64I-NEXT: xor a0, a0, a132; RV64I-NEXT: sub a0, a1, a033; RV64I-NEXT: ret34;35; RV32ZBB-LABEL: abd_ext_i8:36; RV32ZBB: # %bb.0:37; RV32ZBB-NEXT: sext.b a1, a138; RV32ZBB-NEXT: sext.b a0, a039; RV32ZBB-NEXT: max a2, a0, a140; RV32ZBB-NEXT: min a0, a0, a141; RV32ZBB-NEXT: sub a0, a0, a242; RV32ZBB-NEXT: ret43;44; RV64ZBB-LABEL: abd_ext_i8:45; RV64ZBB: # %bb.0:46; RV64ZBB-NEXT: sext.b a0, a047; RV64ZBB-NEXT: sext.b a1, a148; RV64ZBB-NEXT: sub a0, a0, a149; RV64ZBB-NEXT: neg a1, a050; RV64ZBB-NEXT: min a0, a0, a151; RV64ZBB-NEXT: ret52 %aext = sext i8 %a to i6453 %bext = sext i8 %b to i6454 %sub = sub i64 %aext, %bext55 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)56 %nabs = sub i64 0, %abs57 %trunc = trunc i64 %nabs to i858 ret i8 %trunc59}60 61define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {62; RV32I-LABEL: abd_ext_i8_i16:63; RV32I: # %bb.0:64; RV32I-NEXT: slli a1, a1, 1665; RV32I-NEXT: slli a0, a0, 2466; RV32I-NEXT: srai a1, a1, 1667; RV32I-NEXT: srai a0, a0, 2468; RV32I-NEXT: sub a0, a0, a169; RV32I-NEXT: srai a1, a0, 3170; RV32I-NEXT: xor a0, a0, a171; RV32I-NEXT: sub a0, a1, a072; RV32I-NEXT: ret73;74; RV64I-LABEL: abd_ext_i8_i16:75; RV64I: # %bb.0:76; RV64I-NEXT: slli a0, a0, 5677; RV64I-NEXT: slli a1, a1, 4878; RV64I-NEXT: srai a0, a0, 5679; RV64I-NEXT: srai a1, a1, 4880; RV64I-NEXT: sub a0, a0, a181; RV64I-NEXT: srai a1, a0, 6382; RV64I-NEXT: xor a0, a0, a183; RV64I-NEXT: sub a0, a1, a084; RV64I-NEXT: ret85;86; RV32ZBB-LABEL: abd_ext_i8_i16:87; RV32ZBB: # %bb.0:88; RV32ZBB-NEXT: sext.h a1, a189; RV32ZBB-NEXT: sext.b a0, a090; RV32ZBB-NEXT: max a2, a0, a191; RV32ZBB-NEXT: min a0, a0, a192; RV32ZBB-NEXT: sub a0, a0, a293; RV32ZBB-NEXT: ret94;95; RV64ZBB-LABEL: abd_ext_i8_i16:96; RV64ZBB: # %bb.0:97; RV64ZBB-NEXT: sext.b a0, a098; RV64ZBB-NEXT: sext.h a1, a199; RV64ZBB-NEXT: sub a0, a0, a1100; RV64ZBB-NEXT: neg a1, a0101; RV64ZBB-NEXT: min a0, a0, a1102; RV64ZBB-NEXT: ret103 %aext = sext i8 %a to i64104 %bext = sext i16 %b to i64105 %sub = sub i64 %aext, %bext106 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)107 %nabs = sub i64 0, %abs108 %trunc = trunc i64 %nabs to i8109 ret i8 %trunc110}111 112define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {113; RV32I-LABEL: abd_ext_i8_undef:114; RV32I: # %bb.0:115; RV32I-NEXT: slli a1, a1, 24116; RV32I-NEXT: slli a0, a0, 24117; RV32I-NEXT: srai a1, a1, 24118; RV32I-NEXT: srai a0, a0, 24119; RV32I-NEXT: sub a0, a0, a1120; RV32I-NEXT: srai a1, a0, 31121; RV32I-NEXT: xor a0, a0, a1122; RV32I-NEXT: sub a0, a1, a0123; RV32I-NEXT: ret124;125; RV64I-LABEL: abd_ext_i8_undef:126; RV64I: # %bb.0:127; RV64I-NEXT: slli a0, a0, 56128; RV64I-NEXT: slli a1, a1, 56129; RV64I-NEXT: srai a0, a0, 56130; RV64I-NEXT: srai a1, a1, 56131; RV64I-NEXT: sub a0, a0, a1132; RV64I-NEXT: srai a1, a0, 63133; RV64I-NEXT: xor a0, a0, a1134; RV64I-NEXT: sub a0, a1, a0135; RV64I-NEXT: ret136;137; RV32ZBB-LABEL: abd_ext_i8_undef:138; RV32ZBB: # %bb.0:139; RV32ZBB-NEXT: sext.b a1, a1140; RV32ZBB-NEXT: sext.b a0, a0141; RV32ZBB-NEXT: max a2, a0, a1142; RV32ZBB-NEXT: min a0, a0, a1143; RV32ZBB-NEXT: sub a0, a0, a2144; RV32ZBB-NEXT: ret145;146; RV64ZBB-LABEL: abd_ext_i8_undef:147; RV64ZBB: # %bb.0:148; RV64ZBB-NEXT: sext.b a0, a0149; RV64ZBB-NEXT: sext.b a1, a1150; RV64ZBB-NEXT: sub a0, a0, a1151; RV64ZBB-NEXT: neg a1, a0152; RV64ZBB-NEXT: min a0, a0, a1153; RV64ZBB-NEXT: ret154 %aext = sext i8 %a to i64155 %bext = sext i8 %b to i64156 %sub = sub i64 %aext, %bext157 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)158 %nabs = sub i64 0, %abs159 %trunc = trunc i64 %nabs to i8160 ret i8 %trunc161}162 163define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {164; RV32I-LABEL: abd_ext_i16:165; RV32I: # %bb.0:166; RV32I-NEXT: slli a1, a1, 16167; RV32I-NEXT: slli a0, a0, 16168; RV32I-NEXT: srai a1, a1, 16169; RV32I-NEXT: srai a0, a0, 16170; RV32I-NEXT: sub a0, a0, a1171; RV32I-NEXT: srai a1, a0, 31172; RV32I-NEXT: xor a0, a0, a1173; RV32I-NEXT: sub a0, a1, a0174; RV32I-NEXT: ret175;176; RV64I-LABEL: abd_ext_i16:177; RV64I: # %bb.0:178; RV64I-NEXT: slli a0, a0, 48179; RV64I-NEXT: slli a1, a1, 48180; RV64I-NEXT: srai a0, a0, 48181; RV64I-NEXT: srai a1, a1, 48182; RV64I-NEXT: sub a0, a0, a1183; RV64I-NEXT: srai a1, a0, 63184; RV64I-NEXT: xor a0, a0, a1185; RV64I-NEXT: sub a0, a1, a0186; RV64I-NEXT: ret187;188; RV32ZBB-LABEL: abd_ext_i16:189; RV32ZBB: # %bb.0:190; RV32ZBB-NEXT: sext.h a1, a1191; RV32ZBB-NEXT: sext.h a0, a0192; RV32ZBB-NEXT: max a2, a0, a1193; RV32ZBB-NEXT: min a0, a0, a1194; RV32ZBB-NEXT: sub a0, a0, a2195; RV32ZBB-NEXT: ret196;197; RV64ZBB-LABEL: abd_ext_i16:198; RV64ZBB: # %bb.0:199; RV64ZBB-NEXT: sext.h a0, a0200; RV64ZBB-NEXT: sext.h a1, a1201; RV64ZBB-NEXT: sub a0, a0, a1202; RV64ZBB-NEXT: neg a1, a0203; RV64ZBB-NEXT: min a0, a0, a1204; RV64ZBB-NEXT: ret205 %aext = sext i16 %a to i64206 %bext = sext i16 %b to i64207 %sub = sub i64 %aext, %bext208 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)209 %nabs = sub i64 0, %abs210 %trunc = trunc i64 %nabs to i16211 ret i16 %trunc212}213 214define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {215; RV32I-LABEL: abd_ext_i16_i32:216; RV32I: # %bb.0:217; RV32I-NEXT: slli a0, a0, 16218; RV32I-NEXT: srai a0, a0, 16219; RV32I-NEXT: blt a1, a0, .LBB4_2220; RV32I-NEXT: # %bb.1:221; RV32I-NEXT: sub a0, a1, a0222; RV32I-NEXT: neg a0, a0223; RV32I-NEXT: ret224; RV32I-NEXT: .LBB4_2:225; RV32I-NEXT: sub a0, a0, a1226; RV32I-NEXT: neg a0, a0227; RV32I-NEXT: ret228;229; RV64I-LABEL: abd_ext_i16_i32:230; RV64I: # %bb.0:231; RV64I-NEXT: slli a0, a0, 48232; RV64I-NEXT: srai a0, a0, 48233; RV64I-NEXT: sext.w a1, a1234; RV64I-NEXT: sub a0, a0, a1235; RV64I-NEXT: srai a1, a0, 63236; RV64I-NEXT: xor a0, a0, a1237; RV64I-NEXT: sub a0, a1, a0238; RV64I-NEXT: ret239;240; RV32ZBB-LABEL: abd_ext_i16_i32:241; RV32ZBB: # %bb.0:242; RV32ZBB-NEXT: sext.h a0, a0243; RV32ZBB-NEXT: max a2, a0, a1244; RV32ZBB-NEXT: min a0, a0, a1245; RV32ZBB-NEXT: sub a0, a0, a2246; RV32ZBB-NEXT: ret247;248; RV64ZBB-LABEL: abd_ext_i16_i32:249; RV64ZBB: # %bb.0:250; RV64ZBB-NEXT: sext.h a0, a0251; RV64ZBB-NEXT: sext.w a1, a1252; RV64ZBB-NEXT: sub a0, a0, a1253; RV64ZBB-NEXT: neg a1, a0254; RV64ZBB-NEXT: min a0, a0, a1255; RV64ZBB-NEXT: ret256 %aext = sext i16 %a to i64257 %bext = sext i32 %b to i64258 %sub = sub i64 %aext, %bext259 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)260 %nabs = sub i64 0, %abs261 %trunc = trunc i64 %nabs to i16262 ret i16 %trunc263}264 265define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {266; RV32I-LABEL: abd_ext_i16_undef:267; RV32I: # %bb.0:268; RV32I-NEXT: slli a1, a1, 16269; RV32I-NEXT: slli a0, a0, 16270; RV32I-NEXT: srai a1, a1, 16271; RV32I-NEXT: srai a0, a0, 16272; RV32I-NEXT: sub a0, a0, a1273; RV32I-NEXT: srai a1, a0, 31274; RV32I-NEXT: xor a0, a0, a1275; RV32I-NEXT: sub a0, a1, a0276; RV32I-NEXT: ret277;278; RV64I-LABEL: abd_ext_i16_undef:279; RV64I: # %bb.0:280; RV64I-NEXT: slli a0, a0, 48281; RV64I-NEXT: slli a1, a1, 48282; RV64I-NEXT: srai a0, a0, 48283; RV64I-NEXT: srai a1, a1, 48284; RV64I-NEXT: sub a0, a0, a1285; RV64I-NEXT: srai a1, a0, 63286; RV64I-NEXT: xor a0, a0, a1287; RV64I-NEXT: sub a0, a1, a0288; RV64I-NEXT: ret289;290; RV32ZBB-LABEL: abd_ext_i16_undef:291; RV32ZBB: # %bb.0:292; RV32ZBB-NEXT: sext.h a1, a1293; RV32ZBB-NEXT: sext.h a0, a0294; RV32ZBB-NEXT: max a2, a0, a1295; RV32ZBB-NEXT: min a0, a0, a1296; RV32ZBB-NEXT: sub a0, a0, a2297; RV32ZBB-NEXT: ret298;299; RV64ZBB-LABEL: abd_ext_i16_undef:300; RV64ZBB: # %bb.0:301; RV64ZBB-NEXT: sext.h a0, a0302; RV64ZBB-NEXT: sext.h a1, a1303; RV64ZBB-NEXT: sub a0, a0, a1304; RV64ZBB-NEXT: neg a1, a0305; RV64ZBB-NEXT: min a0, a0, a1306; RV64ZBB-NEXT: ret307 %aext = sext i16 %a to i64308 %bext = sext i16 %b to i64309 %sub = sub i64 %aext, %bext310 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)311 %nabs = sub i64 0, %abs312 %trunc = trunc i64 %nabs to i16313 ret i16 %trunc314}315 316define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {317; RV32I-LABEL: abd_ext_i32:318; RV32I: # %bb.0:319; RV32I-NEXT: blt a1, a0, .LBB6_2320; RV32I-NEXT: # %bb.1:321; RV32I-NEXT: sub a0, a1, a0322; RV32I-NEXT: neg a0, a0323; RV32I-NEXT: ret324; RV32I-NEXT: .LBB6_2:325; RV32I-NEXT: sub a0, a0, a1326; RV32I-NEXT: neg a0, a0327; RV32I-NEXT: ret328;329; RV64I-LABEL: abd_ext_i32:330; RV64I: # %bb.0:331; RV64I-NEXT: sext.w a0, a0332; RV64I-NEXT: sext.w a1, a1333; RV64I-NEXT: sub a0, a0, a1334; RV64I-NEXT: srai a1, a0, 63335; RV64I-NEXT: xor a0, a0, a1336; RV64I-NEXT: sub a0, a1, a0337; RV64I-NEXT: ret338;339; RV32ZBB-LABEL: abd_ext_i32:340; RV32ZBB: # %bb.0:341; RV32ZBB-NEXT: max a2, a0, a1342; RV32ZBB-NEXT: min a0, a0, a1343; RV32ZBB-NEXT: sub a0, a0, a2344; RV32ZBB-NEXT: ret345;346; RV64ZBB-LABEL: abd_ext_i32:347; RV64ZBB: # %bb.0:348; RV64ZBB-NEXT: sext.w a0, a0349; RV64ZBB-NEXT: sext.w a1, a1350; RV64ZBB-NEXT: sub a0, a0, a1351; RV64ZBB-NEXT: neg a1, a0352; RV64ZBB-NEXT: min a0, a0, a1353; RV64ZBB-NEXT: ret354 %aext = sext i32 %a to i64355 %bext = sext i32 %b to i64356 %sub = sub i64 %aext, %bext357 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)358 %nabs = sub i64 0, %abs359 %trunc = trunc i64 %nabs to i32360 ret i32 %trunc361}362 363define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {364; RV32I-LABEL: abd_ext_i32_i16:365; RV32I: # %bb.0:366; RV32I-NEXT: slli a1, a1, 16367; RV32I-NEXT: srai a1, a1, 16368; RV32I-NEXT: blt a1, a0, .LBB7_2369; RV32I-NEXT: # %bb.1:370; RV32I-NEXT: sub a0, a1, a0371; RV32I-NEXT: neg a0, a0372; RV32I-NEXT: ret373; RV32I-NEXT: .LBB7_2:374; RV32I-NEXT: sub a0, a0, a1375; RV32I-NEXT: neg a0, a0376; RV32I-NEXT: ret377;378; RV64I-LABEL: abd_ext_i32_i16:379; RV64I: # %bb.0:380; RV64I-NEXT: sext.w a0, a0381; RV64I-NEXT: slli a1, a1, 48382; RV64I-NEXT: srai a1, a1, 48383; RV64I-NEXT: sub a0, a0, a1384; RV64I-NEXT: srai a1, a0, 63385; RV64I-NEXT: xor a0, a0, a1386; RV64I-NEXT: sub a0, a1, a0387; RV64I-NEXT: ret388;389; RV32ZBB-LABEL: abd_ext_i32_i16:390; RV32ZBB: # %bb.0:391; RV32ZBB-NEXT: sext.h a1, a1392; RV32ZBB-NEXT: max a2, a0, a1393; RV32ZBB-NEXT: min a0, a0, a1394; RV32ZBB-NEXT: sub a0, a0, a2395; RV32ZBB-NEXT: ret396;397; RV64ZBB-LABEL: abd_ext_i32_i16:398; RV64ZBB: # %bb.0:399; RV64ZBB-NEXT: sext.w a0, a0400; RV64ZBB-NEXT: sext.h a1, a1401; RV64ZBB-NEXT: sub a0, a0, a1402; RV64ZBB-NEXT: neg a1, a0403; RV64ZBB-NEXT: min a0, a0, a1404; RV64ZBB-NEXT: ret405 %aext = sext i32 %a to i64406 %bext = sext i16 %b to i64407 %sub = sub i64 %aext, %bext408 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)409 %nabs = sub i64 0, %abs410 %trunc = trunc i64 %nabs to i32411 ret i32 %trunc412}413 414define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {415; RV32I-LABEL: abd_ext_i32_undef:416; RV32I: # %bb.0:417; RV32I-NEXT: blt a1, a0, .LBB8_2418; RV32I-NEXT: # %bb.1:419; RV32I-NEXT: sub a0, a1, a0420; RV32I-NEXT: neg a0, a0421; RV32I-NEXT: ret422; RV32I-NEXT: .LBB8_2:423; RV32I-NEXT: sub a0, a0, a1424; RV32I-NEXT: neg a0, a0425; RV32I-NEXT: ret426;427; RV64I-LABEL: abd_ext_i32_undef:428; RV64I: # %bb.0:429; RV64I-NEXT: sext.w a0, a0430; RV64I-NEXT: sext.w a1, a1431; RV64I-NEXT: sub a0, a0, a1432; RV64I-NEXT: srai a1, a0, 63433; RV64I-NEXT: xor a0, a0, a1434; RV64I-NEXT: sub a0, a1, a0435; RV64I-NEXT: ret436;437; RV32ZBB-LABEL: abd_ext_i32_undef:438; RV32ZBB: # %bb.0:439; RV32ZBB-NEXT: max a2, a0, a1440; RV32ZBB-NEXT: min a0, a0, a1441; RV32ZBB-NEXT: sub a0, a0, a2442; RV32ZBB-NEXT: ret443;444; RV64ZBB-LABEL: abd_ext_i32_undef:445; RV64ZBB: # %bb.0:446; RV64ZBB-NEXT: sext.w a0, a0447; RV64ZBB-NEXT: sext.w a1, a1448; RV64ZBB-NEXT: sub a0, a0, a1449; RV64ZBB-NEXT: neg a1, a0450; RV64ZBB-NEXT: min a0, a0, a1451; RV64ZBB-NEXT: ret452 %aext = sext i32 %a to i64453 %bext = sext i32 %b to i64454 %sub = sub i64 %aext, %bext455 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)456 %nabs = sub i64 0, %abs457 %trunc = trunc i64 %nabs to i32458 ret i32 %trunc459}460 461define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {462; RV32I-LABEL: abd_ext_i64:463; RV32I: # %bb.0:464; RV32I-NEXT: sltu a4, a2, a0465; RV32I-NEXT: mv a5, a4466; RV32I-NEXT: beq a1, a3, .LBB9_2467; RV32I-NEXT: # %bb.1:468; RV32I-NEXT: slt a5, a3, a1469; RV32I-NEXT: .LBB9_2:470; RV32I-NEXT: bnez a5, .LBB9_4471; RV32I-NEXT: # %bb.3:472; RV32I-NEXT: sub a1, a3, a1473; RV32I-NEXT: sub a1, a1, a4474; RV32I-NEXT: sub a0, a2, a0475; RV32I-NEXT: j .LBB9_5476; RV32I-NEXT: .LBB9_4:477; RV32I-NEXT: sltu a4, a0, a2478; RV32I-NEXT: sub a1, a1, a3479; RV32I-NEXT: sub a1, a1, a4480; RV32I-NEXT: sub a0, a0, a2481; RV32I-NEXT: .LBB9_5:482; RV32I-NEXT: snez a2, a0483; RV32I-NEXT: add a1, a1, a2484; RV32I-NEXT: neg a1, a1485; RV32I-NEXT: neg a0, a0486; RV32I-NEXT: ret487;488; RV64I-LABEL: abd_ext_i64:489; RV64I: # %bb.0:490; RV64I-NEXT: blt a1, a0, .LBB9_2491; RV64I-NEXT: # %bb.1:492; RV64I-NEXT: sub a0, a1, a0493; RV64I-NEXT: neg a0, a0494; RV64I-NEXT: ret495; RV64I-NEXT: .LBB9_2:496; RV64I-NEXT: sub a0, a0, a1497; RV64I-NEXT: neg a0, a0498; RV64I-NEXT: ret499;500; RV32ZBB-LABEL: abd_ext_i64:501; RV32ZBB: # %bb.0:502; RV32ZBB-NEXT: sltu a4, a2, a0503; RV32ZBB-NEXT: mv a5, a4504; RV32ZBB-NEXT: beq a1, a3, .LBB9_2505; RV32ZBB-NEXT: # %bb.1:506; RV32ZBB-NEXT: slt a5, a3, a1507; RV32ZBB-NEXT: .LBB9_2:508; RV32ZBB-NEXT: bnez a5, .LBB9_4509; RV32ZBB-NEXT: # %bb.3:510; RV32ZBB-NEXT: sub a1, a3, a1511; RV32ZBB-NEXT: sub a1, a1, a4512; RV32ZBB-NEXT: sub a0, a2, a0513; RV32ZBB-NEXT: j .LBB9_5514; RV32ZBB-NEXT: .LBB9_4:515; RV32ZBB-NEXT: sltu a4, a0, a2516; RV32ZBB-NEXT: sub a1, a1, a3517; RV32ZBB-NEXT: sub a1, a1, a4518; RV32ZBB-NEXT: sub a0, a0, a2519; RV32ZBB-NEXT: .LBB9_5:520; RV32ZBB-NEXT: snez a2, a0521; RV32ZBB-NEXT: add a1, a1, a2522; RV32ZBB-NEXT: neg a1, a1523; RV32ZBB-NEXT: neg a0, a0524; RV32ZBB-NEXT: ret525;526; RV64ZBB-LABEL: abd_ext_i64:527; RV64ZBB: # %bb.0:528; RV64ZBB-NEXT: max a2, a0, a1529; RV64ZBB-NEXT: min a0, a0, a1530; RV64ZBB-NEXT: sub a0, a0, a2531; RV64ZBB-NEXT: ret532 %aext = sext i64 %a to i128533 %bext = sext i64 %b to i128534 %sub = sub i128 %aext, %bext535 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)536 %nabs = sub i128 0, %abs537 %trunc = trunc i128 %nabs to i64538 ret i64 %trunc539}540 541define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {542; RV32I-LABEL: abd_ext_i64_undef:543; RV32I: # %bb.0:544; RV32I-NEXT: sltu a4, a2, a0545; RV32I-NEXT: mv a5, a4546; RV32I-NEXT: beq a1, a3, .LBB10_2547; RV32I-NEXT: # %bb.1:548; RV32I-NEXT: slt a5, a3, a1549; RV32I-NEXT: .LBB10_2:550; RV32I-NEXT: bnez a5, .LBB10_4551; RV32I-NEXT: # %bb.3:552; RV32I-NEXT: sub a1, a3, a1553; RV32I-NEXT: sub a1, a1, a4554; RV32I-NEXT: sub a0, a2, a0555; RV32I-NEXT: j .LBB10_5556; RV32I-NEXT: .LBB10_4:557; RV32I-NEXT: sltu a4, a0, a2558; RV32I-NEXT: sub a1, a1, a3559; RV32I-NEXT: sub a1, a1, a4560; RV32I-NEXT: sub a0, a0, a2561; RV32I-NEXT: .LBB10_5:562; RV32I-NEXT: snez a2, a0563; RV32I-NEXT: add a1, a1, a2564; RV32I-NEXT: neg a1, a1565; RV32I-NEXT: neg a0, a0566; RV32I-NEXT: ret567;568; RV64I-LABEL: abd_ext_i64_undef:569; RV64I: # %bb.0:570; RV64I-NEXT: blt a1, a0, .LBB10_2571; RV64I-NEXT: # %bb.1:572; RV64I-NEXT: sub a0, a1, a0573; RV64I-NEXT: neg a0, a0574; RV64I-NEXT: ret575; RV64I-NEXT: .LBB10_2:576; RV64I-NEXT: sub a0, a0, a1577; RV64I-NEXT: neg a0, a0578; RV64I-NEXT: ret579;580; RV32ZBB-LABEL: abd_ext_i64_undef:581; RV32ZBB: # %bb.0:582; RV32ZBB-NEXT: sltu a4, a2, a0583; RV32ZBB-NEXT: mv a5, a4584; RV32ZBB-NEXT: beq a1, a3, .LBB10_2585; RV32ZBB-NEXT: # %bb.1:586; RV32ZBB-NEXT: slt a5, a3, a1587; RV32ZBB-NEXT: .LBB10_2:588; RV32ZBB-NEXT: bnez a5, .LBB10_4589; RV32ZBB-NEXT: # %bb.3:590; RV32ZBB-NEXT: sub a1, a3, a1591; RV32ZBB-NEXT: sub a1, a1, a4592; RV32ZBB-NEXT: sub a0, a2, a0593; RV32ZBB-NEXT: j .LBB10_5594; RV32ZBB-NEXT: .LBB10_4:595; RV32ZBB-NEXT: sltu a4, a0, a2596; RV32ZBB-NEXT: sub a1, a1, a3597; RV32ZBB-NEXT: sub a1, a1, a4598; RV32ZBB-NEXT: sub a0, a0, a2599; RV32ZBB-NEXT: .LBB10_5:600; RV32ZBB-NEXT: snez a2, a0601; RV32ZBB-NEXT: add a1, a1, a2602; RV32ZBB-NEXT: neg a1, a1603; RV32ZBB-NEXT: neg a0, a0604; RV32ZBB-NEXT: ret605;606; RV64ZBB-LABEL: abd_ext_i64_undef:607; RV64ZBB: # %bb.0:608; RV64ZBB-NEXT: max a2, a0, a1609; RV64ZBB-NEXT: min a0, a0, a1610; RV64ZBB-NEXT: sub a0, a0, a2611; RV64ZBB-NEXT: ret612 %aext = sext i64 %a to i128613 %bext = sext i64 %b to i128614 %sub = sub i128 %aext, %bext615 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)616 %nabs = sub i128 0, %abs617 %trunc = trunc i128 %nabs to i64618 ret i64 %trunc619}620 621define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {622; RV32I-LABEL: abd_ext_i128:623; RV32I: # %bb.0:624; RV32I-NEXT: lw a3, 0(a1)625; RV32I-NEXT: lw a4, 4(a1)626; RV32I-NEXT: lw a6, 8(a1)627; RV32I-NEXT: lw t1, 12(a1)628; RV32I-NEXT: lw a1, 0(a2)629; RV32I-NEXT: lw t0, 8(a2)630; RV32I-NEXT: lw t2, 12(a2)631; RV32I-NEXT: lw a2, 4(a2)632; RV32I-NEXT: sltu t3, t0, a6633; RV32I-NEXT: mv t4, t3634; RV32I-NEXT: beq t1, t2, .LBB11_2635; RV32I-NEXT: # %bb.1:636; RV32I-NEXT: slt t4, t2, t1637; RV32I-NEXT: .LBB11_2:638; RV32I-NEXT: sltu a5, a1, a3639; RV32I-NEXT: sltu t6, a2, a4640; RV32I-NEXT: mv a7, a5641; RV32I-NEXT: beq a4, a2, .LBB11_4642; RV32I-NEXT: # %bb.3:643; RV32I-NEXT: mv a7, t6644; RV32I-NEXT: .LBB11_4:645; RV32I-NEXT: addi sp, sp, -16646; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill647; RV32I-NEXT: xor t5, t1, t2648; RV32I-NEXT: xor s0, a6, t0649; RV32I-NEXT: or t5, s0, t5650; RV32I-NEXT: beqz t5, .LBB11_6651; RV32I-NEXT: # %bb.5:652; RV32I-NEXT: mv a7, t4653; RV32I-NEXT: .LBB11_6:654; RV32I-NEXT: mv t5, a5655; RV32I-NEXT: beq a2, a4, .LBB11_8656; RV32I-NEXT: # %bb.7:657; RV32I-NEXT: mv t5, t6658; RV32I-NEXT: .LBB11_8:659; RV32I-NEXT: sltu t4, a3, a1660; RV32I-NEXT: mv t6, t4661; RV32I-NEXT: beq a4, a2, .LBB11_10662; RV32I-NEXT: # %bb.9:663; RV32I-NEXT: sltu t6, a4, a2664; RV32I-NEXT: .LBB11_10:665; RV32I-NEXT: bnez a7, .LBB11_12666; RV32I-NEXT: # %bb.11:667; RV32I-NEXT: sub t1, t2, t1668; RV32I-NEXT: sub a6, t0, a6669; RV32I-NEXT: sub t0, t1, t3670; RV32I-NEXT: sltu t1, a6, t5671; RV32I-NEXT: sub t0, t0, t1672; RV32I-NEXT: sub a6, a6, t5673; RV32I-NEXT: j .LBB11_13674; RV32I-NEXT: .LBB11_12:675; RV32I-NEXT: sltu t3, a6, t0676; RV32I-NEXT: sub t1, t1, t2677; RV32I-NEXT: sub a6, a6, t0678; RV32I-NEXT: sub t0, t1, t3679; RV32I-NEXT: sltu t1, a6, t6680; RV32I-NEXT: sub t0, t0, t1681; RV32I-NEXT: sub a6, a6, t6682; RV32I-NEXT: .LBB11_13:683; RV32I-NEXT: snez t1, a6684; RV32I-NEXT: add t0, t0, t1685; RV32I-NEXT: bnez a7, .LBB11_15686; RV32I-NEXT: # %bb.14:687; RV32I-NEXT: sub a2, a2, a4688; RV32I-NEXT: sub a2, a2, a5689; RV32I-NEXT: sub a1, a1, a3690; RV32I-NEXT: j .LBB11_16691; RV32I-NEXT: .LBB11_15:692; RV32I-NEXT: sub a4, a4, a2693; RV32I-NEXT: sub a2, a4, t4694; RV32I-NEXT: sub a1, a3, a1695; RV32I-NEXT: .LBB11_16:696; RV32I-NEXT: or a3, a1, a2697; RV32I-NEXT: neg a4, a6698; RV32I-NEXT: neg a5, t0699; RV32I-NEXT: snez a6, a1700; RV32I-NEXT: neg a1, a1701; RV32I-NEXT: snez a3, a3702; RV32I-NEXT: add a2, a2, a6703; RV32I-NEXT: sltu a6, a4, a3704; RV32I-NEXT: neg a2, a2705; RV32I-NEXT: sub a4, a4, a3706; RV32I-NEXT: sub a3, a5, a6707; RV32I-NEXT: sw a1, 0(a0)708; RV32I-NEXT: sw a2, 4(a0)709; RV32I-NEXT: sw a4, 8(a0)710; RV32I-NEXT: sw a3, 12(a0)711; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload712; RV32I-NEXT: addi sp, sp, 16713; RV32I-NEXT: ret714;715; RV64I-LABEL: abd_ext_i128:716; RV64I: # %bb.0:717; RV64I-NEXT: sltu a4, a2, a0718; RV64I-NEXT: mv a5, a4719; RV64I-NEXT: beq a1, a3, .LBB11_2720; RV64I-NEXT: # %bb.1:721; RV64I-NEXT: slt a5, a3, a1722; RV64I-NEXT: .LBB11_2:723; RV64I-NEXT: bnez a5, .LBB11_4724; RV64I-NEXT: # %bb.3:725; RV64I-NEXT: sub a1, a3, a1726; RV64I-NEXT: sub a1, a1, a4727; RV64I-NEXT: sub a0, a2, a0728; RV64I-NEXT: j .LBB11_5729; RV64I-NEXT: .LBB11_4:730; RV64I-NEXT: sltu a4, a0, a2731; RV64I-NEXT: sub a1, a1, a3732; RV64I-NEXT: sub a1, a1, a4733; RV64I-NEXT: sub a0, a0, a2734; RV64I-NEXT: .LBB11_5:735; RV64I-NEXT: snez a2, a0736; RV64I-NEXT: add a1, a1, a2737; RV64I-NEXT: neg a1, a1738; RV64I-NEXT: neg a0, a0739; RV64I-NEXT: ret740;741; RV32ZBB-LABEL: abd_ext_i128:742; RV32ZBB: # %bb.0:743; RV32ZBB-NEXT: lw a3, 0(a1)744; RV32ZBB-NEXT: lw a4, 4(a1)745; RV32ZBB-NEXT: lw a6, 8(a1)746; RV32ZBB-NEXT: lw t1, 12(a1)747; RV32ZBB-NEXT: lw a1, 0(a2)748; RV32ZBB-NEXT: lw t0, 8(a2)749; RV32ZBB-NEXT: lw t2, 12(a2)750; RV32ZBB-NEXT: lw a2, 4(a2)751; RV32ZBB-NEXT: sltu t3, t0, a6752; RV32ZBB-NEXT: mv t4, t3753; RV32ZBB-NEXT: beq t1, t2, .LBB11_2754; RV32ZBB-NEXT: # %bb.1:755; RV32ZBB-NEXT: slt t4, t2, t1756; RV32ZBB-NEXT: .LBB11_2:757; RV32ZBB-NEXT: sltu a5, a1, a3758; RV32ZBB-NEXT: sltu t6, a2, a4759; RV32ZBB-NEXT: mv a7, a5760; RV32ZBB-NEXT: beq a4, a2, .LBB11_4761; RV32ZBB-NEXT: # %bb.3:762; RV32ZBB-NEXT: mv a7, t6763; RV32ZBB-NEXT: .LBB11_4:764; RV32ZBB-NEXT: addi sp, sp, -16765; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill766; RV32ZBB-NEXT: xor t5, t1, t2767; RV32ZBB-NEXT: xor s0, a6, t0768; RV32ZBB-NEXT: or t5, s0, t5769; RV32ZBB-NEXT: beqz t5, .LBB11_6770; RV32ZBB-NEXT: # %bb.5:771; RV32ZBB-NEXT: mv a7, t4772; RV32ZBB-NEXT: .LBB11_6:773; RV32ZBB-NEXT: mv t5, a5774; RV32ZBB-NEXT: beq a2, a4, .LBB11_8775; RV32ZBB-NEXT: # %bb.7:776; RV32ZBB-NEXT: mv t5, t6777; RV32ZBB-NEXT: .LBB11_8:778; RV32ZBB-NEXT: sltu t4, a3, a1779; RV32ZBB-NEXT: mv t6, t4780; RV32ZBB-NEXT: beq a4, a2, .LBB11_10781; RV32ZBB-NEXT: # %bb.9:782; RV32ZBB-NEXT: sltu t6, a4, a2783; RV32ZBB-NEXT: .LBB11_10:784; RV32ZBB-NEXT: bnez a7, .LBB11_12785; RV32ZBB-NEXT: # %bb.11:786; RV32ZBB-NEXT: sub t1, t2, t1787; RV32ZBB-NEXT: sub a6, t0, a6788; RV32ZBB-NEXT: sub t0, t1, t3789; RV32ZBB-NEXT: sltu t1, a6, t5790; RV32ZBB-NEXT: sub t0, t0, t1791; RV32ZBB-NEXT: sub a6, a6, t5792; RV32ZBB-NEXT: j .LBB11_13793; RV32ZBB-NEXT: .LBB11_12:794; RV32ZBB-NEXT: sltu t3, a6, t0795; RV32ZBB-NEXT: sub t1, t1, t2796; RV32ZBB-NEXT: sub a6, a6, t0797; RV32ZBB-NEXT: sub t0, t1, t3798; RV32ZBB-NEXT: sltu t1, a6, t6799; RV32ZBB-NEXT: sub t0, t0, t1800; RV32ZBB-NEXT: sub a6, a6, t6801; RV32ZBB-NEXT: .LBB11_13:802; RV32ZBB-NEXT: snez t1, a6803; RV32ZBB-NEXT: add t0, t0, t1804; RV32ZBB-NEXT: bnez a7, .LBB11_15805; RV32ZBB-NEXT: # %bb.14:806; RV32ZBB-NEXT: sub a2, a2, a4807; RV32ZBB-NEXT: sub a2, a2, a5808; RV32ZBB-NEXT: sub a1, a1, a3809; RV32ZBB-NEXT: j .LBB11_16810; RV32ZBB-NEXT: .LBB11_15:811; RV32ZBB-NEXT: sub a4, a4, a2812; RV32ZBB-NEXT: sub a2, a4, t4813; RV32ZBB-NEXT: sub a1, a3, a1814; RV32ZBB-NEXT: .LBB11_16:815; RV32ZBB-NEXT: or a3, a1, a2816; RV32ZBB-NEXT: neg a4, a6817; RV32ZBB-NEXT: neg a5, t0818; RV32ZBB-NEXT: snez a6, a1819; RV32ZBB-NEXT: neg a1, a1820; RV32ZBB-NEXT: snez a3, a3821; RV32ZBB-NEXT: add a2, a2, a6822; RV32ZBB-NEXT: sltu a6, a4, a3823; RV32ZBB-NEXT: neg a2, a2824; RV32ZBB-NEXT: sub a4, a4, a3825; RV32ZBB-NEXT: sub a3, a5, a6826; RV32ZBB-NEXT: sw a1, 0(a0)827; RV32ZBB-NEXT: sw a2, 4(a0)828; RV32ZBB-NEXT: sw a4, 8(a0)829; RV32ZBB-NEXT: sw a3, 12(a0)830; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload831; RV32ZBB-NEXT: addi sp, sp, 16832; RV32ZBB-NEXT: ret833;834; RV64ZBB-LABEL: abd_ext_i128:835; RV64ZBB: # %bb.0:836; RV64ZBB-NEXT: sltu a4, a2, a0837; RV64ZBB-NEXT: mv a5, a4838; RV64ZBB-NEXT: beq a1, a3, .LBB11_2839; RV64ZBB-NEXT: # %bb.1:840; RV64ZBB-NEXT: slt a5, a3, a1841; RV64ZBB-NEXT: .LBB11_2:842; RV64ZBB-NEXT: bnez a5, .LBB11_4843; RV64ZBB-NEXT: # %bb.3:844; RV64ZBB-NEXT: sub a1, a3, a1845; RV64ZBB-NEXT: sub a1, a1, a4846; RV64ZBB-NEXT: sub a0, a2, a0847; RV64ZBB-NEXT: j .LBB11_5848; RV64ZBB-NEXT: .LBB11_4:849; RV64ZBB-NEXT: sltu a4, a0, a2850; RV64ZBB-NEXT: sub a1, a1, a3851; RV64ZBB-NEXT: sub a1, a1, a4852; RV64ZBB-NEXT: sub a0, a0, a2853; RV64ZBB-NEXT: .LBB11_5:854; RV64ZBB-NEXT: snez a2, a0855; RV64ZBB-NEXT: add a1, a1, a2856; RV64ZBB-NEXT: neg a1, a1857; RV64ZBB-NEXT: neg a0, a0858; RV64ZBB-NEXT: ret859 %aext = sext i128 %a to i256860 %bext = sext i128 %b to i256861 %sub = sub i256 %aext, %bext862 %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)863 %nabs = sub i256 0, %abs864 %trunc = trunc i256 %nabs to i128865 ret i128 %trunc866}867 868define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {869; RV32I-LABEL: abd_ext_i128_undef:870; RV32I: # %bb.0:871; RV32I-NEXT: lw a3, 0(a1)872; RV32I-NEXT: lw a4, 4(a1)873; RV32I-NEXT: lw a6, 8(a1)874; RV32I-NEXT: lw t1, 12(a1)875; RV32I-NEXT: lw a1, 0(a2)876; RV32I-NEXT: lw t0, 8(a2)877; RV32I-NEXT: lw t2, 12(a2)878; RV32I-NEXT: lw a2, 4(a2)879; RV32I-NEXT: sltu t3, t0, a6880; RV32I-NEXT: mv t4, t3881; RV32I-NEXT: beq t1, t2, .LBB12_2882; RV32I-NEXT: # %bb.1:883; RV32I-NEXT: slt t4, t2, t1884; RV32I-NEXT: .LBB12_2:885; RV32I-NEXT: sltu a5, a1, a3886; RV32I-NEXT: sltu t6, a2, a4887; RV32I-NEXT: mv a7, a5888; RV32I-NEXT: beq a4, a2, .LBB12_4889; RV32I-NEXT: # %bb.3:890; RV32I-NEXT: mv a7, t6891; RV32I-NEXT: .LBB12_4:892; RV32I-NEXT: addi sp, sp, -16893; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill894; RV32I-NEXT: xor t5, t1, t2895; RV32I-NEXT: xor s0, a6, t0896; RV32I-NEXT: or t5, s0, t5897; RV32I-NEXT: beqz t5, .LBB12_6898; RV32I-NEXT: # %bb.5:899; RV32I-NEXT: mv a7, t4900; RV32I-NEXT: .LBB12_6:901; RV32I-NEXT: mv t5, a5902; RV32I-NEXT: beq a2, a4, .LBB12_8903; RV32I-NEXT: # %bb.7:904; RV32I-NEXT: mv t5, t6905; RV32I-NEXT: .LBB12_8:906; RV32I-NEXT: sltu t4, a3, a1907; RV32I-NEXT: mv t6, t4908; RV32I-NEXT: beq a4, a2, .LBB12_10909; RV32I-NEXT: # %bb.9:910; RV32I-NEXT: sltu t6, a4, a2911; RV32I-NEXT: .LBB12_10:912; RV32I-NEXT: bnez a7, .LBB12_12913; RV32I-NEXT: # %bb.11:914; RV32I-NEXT: sub t1, t2, t1915; RV32I-NEXT: sub a6, t0, a6916; RV32I-NEXT: sub t0, t1, t3917; RV32I-NEXT: sltu t1, a6, t5918; RV32I-NEXT: sub t0, t0, t1919; RV32I-NEXT: sub a6, a6, t5920; RV32I-NEXT: j .LBB12_13921; RV32I-NEXT: .LBB12_12:922; RV32I-NEXT: sltu t3, a6, t0923; RV32I-NEXT: sub t1, t1, t2924; RV32I-NEXT: sub a6, a6, t0925; RV32I-NEXT: sub t0, t1, t3926; RV32I-NEXT: sltu t1, a6, t6927; RV32I-NEXT: sub t0, t0, t1928; RV32I-NEXT: sub a6, a6, t6929; RV32I-NEXT: .LBB12_13:930; RV32I-NEXT: snez t1, a6931; RV32I-NEXT: add t0, t0, t1932; RV32I-NEXT: bnez a7, .LBB12_15933; RV32I-NEXT: # %bb.14:934; RV32I-NEXT: sub a2, a2, a4935; RV32I-NEXT: sub a2, a2, a5936; RV32I-NEXT: sub a1, a1, a3937; RV32I-NEXT: j .LBB12_16938; RV32I-NEXT: .LBB12_15:939; RV32I-NEXT: sub a4, a4, a2940; RV32I-NEXT: sub a2, a4, t4941; RV32I-NEXT: sub a1, a3, a1942; RV32I-NEXT: .LBB12_16:943; RV32I-NEXT: or a3, a1, a2944; RV32I-NEXT: neg a4, a6945; RV32I-NEXT: neg a5, t0946; RV32I-NEXT: snez a6, a1947; RV32I-NEXT: neg a1, a1948; RV32I-NEXT: snez a3, a3949; RV32I-NEXT: add a2, a2, a6950; RV32I-NEXT: sltu a6, a4, a3951; RV32I-NEXT: neg a2, a2952; RV32I-NEXT: sub a4, a4, a3953; RV32I-NEXT: sub a3, a5, a6954; RV32I-NEXT: sw a1, 0(a0)955; RV32I-NEXT: sw a2, 4(a0)956; RV32I-NEXT: sw a4, 8(a0)957; RV32I-NEXT: sw a3, 12(a0)958; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload959; RV32I-NEXT: addi sp, sp, 16960; RV32I-NEXT: ret961;962; RV64I-LABEL: abd_ext_i128_undef:963; RV64I: # %bb.0:964; RV64I-NEXT: sltu a4, a2, a0965; RV64I-NEXT: mv a5, a4966; RV64I-NEXT: beq a1, a3, .LBB12_2967; RV64I-NEXT: # %bb.1:968; RV64I-NEXT: slt a5, a3, a1969; RV64I-NEXT: .LBB12_2:970; RV64I-NEXT: bnez a5, .LBB12_4971; RV64I-NEXT: # %bb.3:972; RV64I-NEXT: sub a1, a3, a1973; RV64I-NEXT: sub a1, a1, a4974; RV64I-NEXT: sub a0, a2, a0975; RV64I-NEXT: j .LBB12_5976; RV64I-NEXT: .LBB12_4:977; RV64I-NEXT: sltu a4, a0, a2978; RV64I-NEXT: sub a1, a1, a3979; RV64I-NEXT: sub a1, a1, a4980; RV64I-NEXT: sub a0, a0, a2981; RV64I-NEXT: .LBB12_5:982; RV64I-NEXT: snez a2, a0983; RV64I-NEXT: add a1, a1, a2984; RV64I-NEXT: neg a1, a1985; RV64I-NEXT: neg a0, a0986; RV64I-NEXT: ret987;988; RV32ZBB-LABEL: abd_ext_i128_undef:989; RV32ZBB: # %bb.0:990; RV32ZBB-NEXT: lw a3, 0(a1)991; RV32ZBB-NEXT: lw a4, 4(a1)992; RV32ZBB-NEXT: lw a6, 8(a1)993; RV32ZBB-NEXT: lw t1, 12(a1)994; RV32ZBB-NEXT: lw a1, 0(a2)995; RV32ZBB-NEXT: lw t0, 8(a2)996; RV32ZBB-NEXT: lw t2, 12(a2)997; RV32ZBB-NEXT: lw a2, 4(a2)998; RV32ZBB-NEXT: sltu t3, t0, a6999; RV32ZBB-NEXT: mv t4, t31000; RV32ZBB-NEXT: beq t1, t2, .LBB12_21001; RV32ZBB-NEXT: # %bb.1:1002; RV32ZBB-NEXT: slt t4, t2, t11003; RV32ZBB-NEXT: .LBB12_2:1004; RV32ZBB-NEXT: sltu a5, a1, a31005; RV32ZBB-NEXT: sltu t6, a2, a41006; RV32ZBB-NEXT: mv a7, a51007; RV32ZBB-NEXT: beq a4, a2, .LBB12_41008; RV32ZBB-NEXT: # %bb.3:1009; RV32ZBB-NEXT: mv a7, t61010; RV32ZBB-NEXT: .LBB12_4:1011; RV32ZBB-NEXT: addi sp, sp, -161012; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1013; RV32ZBB-NEXT: xor t5, t1, t21014; RV32ZBB-NEXT: xor s0, a6, t01015; RV32ZBB-NEXT: or t5, s0, t51016; RV32ZBB-NEXT: beqz t5, .LBB12_61017; RV32ZBB-NEXT: # %bb.5:1018; RV32ZBB-NEXT: mv a7, t41019; RV32ZBB-NEXT: .LBB12_6:1020; RV32ZBB-NEXT: mv t5, a51021; RV32ZBB-NEXT: beq a2, a4, .LBB12_81022; RV32ZBB-NEXT: # %bb.7:1023; RV32ZBB-NEXT: mv t5, t61024; RV32ZBB-NEXT: .LBB12_8:1025; RV32ZBB-NEXT: sltu t4, a3, a11026; RV32ZBB-NEXT: mv t6, t41027; RV32ZBB-NEXT: beq a4, a2, .LBB12_101028; RV32ZBB-NEXT: # %bb.9:1029; RV32ZBB-NEXT: sltu t6, a4, a21030; RV32ZBB-NEXT: .LBB12_10:1031; RV32ZBB-NEXT: bnez a7, .LBB12_121032; RV32ZBB-NEXT: # %bb.11:1033; RV32ZBB-NEXT: sub t1, t2, t11034; RV32ZBB-NEXT: sub a6, t0, a61035; RV32ZBB-NEXT: sub t0, t1, t31036; RV32ZBB-NEXT: sltu t1, a6, t51037; RV32ZBB-NEXT: sub t0, t0, t11038; RV32ZBB-NEXT: sub a6, a6, t51039; RV32ZBB-NEXT: j .LBB12_131040; RV32ZBB-NEXT: .LBB12_12:1041; RV32ZBB-NEXT: sltu t3, a6, t01042; RV32ZBB-NEXT: sub t1, t1, t21043; RV32ZBB-NEXT: sub a6, a6, t01044; RV32ZBB-NEXT: sub t0, t1, t31045; RV32ZBB-NEXT: sltu t1, a6, t61046; RV32ZBB-NEXT: sub t0, t0, t11047; RV32ZBB-NEXT: sub a6, a6, t61048; RV32ZBB-NEXT: .LBB12_13:1049; RV32ZBB-NEXT: snez t1, a61050; RV32ZBB-NEXT: add t0, t0, t11051; RV32ZBB-NEXT: bnez a7, .LBB12_151052; RV32ZBB-NEXT: # %bb.14:1053; RV32ZBB-NEXT: sub a2, a2, a41054; RV32ZBB-NEXT: sub a2, a2, a51055; RV32ZBB-NEXT: sub a1, a1, a31056; RV32ZBB-NEXT: j .LBB12_161057; RV32ZBB-NEXT: .LBB12_15:1058; RV32ZBB-NEXT: sub a4, a4, a21059; RV32ZBB-NEXT: sub a2, a4, t41060; RV32ZBB-NEXT: sub a1, a3, a11061; RV32ZBB-NEXT: .LBB12_16:1062; RV32ZBB-NEXT: or a3, a1, a21063; RV32ZBB-NEXT: neg a4, a61064; RV32ZBB-NEXT: neg a5, t01065; RV32ZBB-NEXT: snez a6, a11066; RV32ZBB-NEXT: neg a1, a11067; RV32ZBB-NEXT: snez a3, a31068; RV32ZBB-NEXT: add a2, a2, a61069; RV32ZBB-NEXT: sltu a6, a4, a31070; RV32ZBB-NEXT: neg a2, a21071; RV32ZBB-NEXT: sub a4, a4, a31072; RV32ZBB-NEXT: sub a3, a5, a61073; RV32ZBB-NEXT: sw a1, 0(a0)1074; RV32ZBB-NEXT: sw a2, 4(a0)1075; RV32ZBB-NEXT: sw a4, 8(a0)1076; RV32ZBB-NEXT: sw a3, 12(a0)1077; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1078; RV32ZBB-NEXT: addi sp, sp, 161079; RV32ZBB-NEXT: ret1080;1081; RV64ZBB-LABEL: abd_ext_i128_undef:1082; RV64ZBB: # %bb.0:1083; RV64ZBB-NEXT: sltu a4, a2, a01084; RV64ZBB-NEXT: mv a5, a41085; RV64ZBB-NEXT: beq a1, a3, .LBB12_21086; RV64ZBB-NEXT: # %bb.1:1087; RV64ZBB-NEXT: slt a5, a3, a11088; RV64ZBB-NEXT: .LBB12_2:1089; RV64ZBB-NEXT: bnez a5, .LBB12_41090; RV64ZBB-NEXT: # %bb.3:1091; RV64ZBB-NEXT: sub a1, a3, a11092; RV64ZBB-NEXT: sub a1, a1, a41093; RV64ZBB-NEXT: sub a0, a2, a01094; RV64ZBB-NEXT: j .LBB12_51095; RV64ZBB-NEXT: .LBB12_4:1096; RV64ZBB-NEXT: sltu a4, a0, a21097; RV64ZBB-NEXT: sub a1, a1, a31098; RV64ZBB-NEXT: sub a1, a1, a41099; RV64ZBB-NEXT: sub a0, a0, a21100; RV64ZBB-NEXT: .LBB12_5:1101; RV64ZBB-NEXT: snez a2, a01102; RV64ZBB-NEXT: add a1, a1, a21103; RV64ZBB-NEXT: neg a1, a11104; RV64ZBB-NEXT: neg a0, a01105; RV64ZBB-NEXT: ret1106 %aext = sext i128 %a to i2561107 %bext = sext i128 %b to i2561108 %sub = sub i256 %aext, %bext1109 %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)1110 %nabs = sub i256 0, %abs1111 %trunc = trunc i256 %nabs to i1281112 ret i128 %trunc1113}1114 1115;1116; sub(smin(a,b),smax(a,b)) -> nabds(a,b)1117;1118 1119define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {1120; RV32I-LABEL: abd_minmax_i8:1121; RV32I: # %bb.0:1122; RV32I-NEXT: slli a1, a1, 241123; RV32I-NEXT: slli a0, a0, 241124; RV32I-NEXT: srai a1, a1, 241125; RV32I-NEXT: srai a0, a0, 241126; RV32I-NEXT: mv a2, a01127; RV32I-NEXT: bge a0, a1, .LBB13_31128; RV32I-NEXT: # %bb.1:1129; RV32I-NEXT: bge a1, a0, .LBB13_41130; RV32I-NEXT: .LBB13_2:1131; RV32I-NEXT: sub a0, a2, a01132; RV32I-NEXT: ret1133; RV32I-NEXT: .LBB13_3:1134; RV32I-NEXT: mv a2, a11135; RV32I-NEXT: blt a1, a0, .LBB13_21136; RV32I-NEXT: .LBB13_4:1137; RV32I-NEXT: sub a0, a2, a11138; RV32I-NEXT: ret1139;1140; RV64I-LABEL: abd_minmax_i8:1141; RV64I: # %bb.0:1142; RV64I-NEXT: slli a1, a1, 561143; RV64I-NEXT: slli a0, a0, 561144; RV64I-NEXT: srai a1, a1, 561145; RV64I-NEXT: srai a0, a0, 561146; RV64I-NEXT: mv a2, a01147; RV64I-NEXT: bge a0, a1, .LBB13_31148; RV64I-NEXT: # %bb.1:1149; RV64I-NEXT: bge a1, a0, .LBB13_41150; RV64I-NEXT: .LBB13_2:1151; RV64I-NEXT: sub a0, a2, a01152; RV64I-NEXT: ret1153; RV64I-NEXT: .LBB13_3:1154; RV64I-NEXT: mv a2, a11155; RV64I-NEXT: blt a1, a0, .LBB13_21156; RV64I-NEXT: .LBB13_4:1157; RV64I-NEXT: sub a0, a2, a11158; RV64I-NEXT: ret1159;1160; ZBB-LABEL: abd_minmax_i8:1161; ZBB: # %bb.0:1162; ZBB-NEXT: sext.b a1, a11163; ZBB-NEXT: sext.b a0, a01164; ZBB-NEXT: min a2, a0, a11165; ZBB-NEXT: max a0, a0, a11166; ZBB-NEXT: sub a0, a2, a01167; ZBB-NEXT: ret1168 %min = call i8 @llvm.smin.i8(i8 %a, i8 %b)1169 %max = call i8 @llvm.smax.i8(i8 %a, i8 %b)1170 %sub = sub i8 %min, %max1171 ret i8 %sub1172}1173 1174define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {1175; RV32I-LABEL: abd_minmax_i16:1176; RV32I: # %bb.0:1177; RV32I-NEXT: slli a1, a1, 161178; RV32I-NEXT: slli a0, a0, 161179; RV32I-NEXT: srai a1, a1, 161180; RV32I-NEXT: srai a0, a0, 161181; RV32I-NEXT: mv a2, a01182; RV32I-NEXT: bge a0, a1, .LBB14_31183; RV32I-NEXT: # %bb.1:1184; RV32I-NEXT: bge a1, a0, .LBB14_41185; RV32I-NEXT: .LBB14_2:1186; RV32I-NEXT: sub a0, a2, a01187; RV32I-NEXT: ret1188; RV32I-NEXT: .LBB14_3:1189; RV32I-NEXT: mv a2, a11190; RV32I-NEXT: blt a1, a0, .LBB14_21191; RV32I-NEXT: .LBB14_4:1192; RV32I-NEXT: sub a0, a2, a11193; RV32I-NEXT: ret1194;1195; RV64I-LABEL: abd_minmax_i16:1196; RV64I: # %bb.0:1197; RV64I-NEXT: slli a1, a1, 481198; RV64I-NEXT: slli a0, a0, 481199; RV64I-NEXT: srai a1, a1, 481200; RV64I-NEXT: srai a0, a0, 481201; RV64I-NEXT: mv a2, a01202; RV64I-NEXT: bge a0, a1, .LBB14_31203; RV64I-NEXT: # %bb.1:1204; RV64I-NEXT: bge a1, a0, .LBB14_41205; RV64I-NEXT: .LBB14_2:1206; RV64I-NEXT: sub a0, a2, a01207; RV64I-NEXT: ret1208; RV64I-NEXT: .LBB14_3:1209; RV64I-NEXT: mv a2, a11210; RV64I-NEXT: blt a1, a0, .LBB14_21211; RV64I-NEXT: .LBB14_4:1212; RV64I-NEXT: sub a0, a2, a11213; RV64I-NEXT: ret1214;1215; ZBB-LABEL: abd_minmax_i16:1216; ZBB: # %bb.0:1217; ZBB-NEXT: sext.h a1, a11218; ZBB-NEXT: sext.h a0, a01219; ZBB-NEXT: min a2, a0, a11220; ZBB-NEXT: max a0, a0, a11221; ZBB-NEXT: sub a0, a2, a01222; ZBB-NEXT: ret1223 %min = call i16 @llvm.smin.i16(i16 %a, i16 %b)1224 %max = call i16 @llvm.smax.i16(i16 %a, i16 %b)1225 %sub = sub i16 %min, %max1226 ret i16 %sub1227}1228 1229define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {1230; RV32I-LABEL: abd_minmax_i32:1231; RV32I: # %bb.0:1232; RV32I-NEXT: mv a2, a01233; RV32I-NEXT: bge a0, a1, .LBB15_31234; RV32I-NEXT: # %bb.1:1235; RV32I-NEXT: bge a1, a0, .LBB15_41236; RV32I-NEXT: .LBB15_2:1237; RV32I-NEXT: sub a0, a2, a01238; RV32I-NEXT: ret1239; RV32I-NEXT: .LBB15_3:1240; RV32I-NEXT: mv a2, a11241; RV32I-NEXT: blt a1, a0, .LBB15_21242; RV32I-NEXT: .LBB15_4:1243; RV32I-NEXT: sub a0, a2, a11244; RV32I-NEXT: ret1245;1246; RV64I-LABEL: abd_minmax_i32:1247; RV64I: # %bb.0:1248; RV64I-NEXT: sext.w a1, a11249; RV64I-NEXT: sext.w a0, a01250; RV64I-NEXT: mv a2, a01251; RV64I-NEXT: bge a0, a1, .LBB15_31252; RV64I-NEXT: # %bb.1:1253; RV64I-NEXT: bge a1, a0, .LBB15_41254; RV64I-NEXT: .LBB15_2:1255; RV64I-NEXT: subw a0, a2, a01256; RV64I-NEXT: ret1257; RV64I-NEXT: .LBB15_3:1258; RV64I-NEXT: mv a2, a11259; RV64I-NEXT: blt a1, a0, .LBB15_21260; RV64I-NEXT: .LBB15_4:1261; RV64I-NEXT: subw a0, a2, a11262; RV64I-NEXT: ret1263;1264; RV32ZBB-LABEL: abd_minmax_i32:1265; RV32ZBB: # %bb.0:1266; RV32ZBB-NEXT: min a2, a0, a11267; RV32ZBB-NEXT: max a0, a0, a11268; RV32ZBB-NEXT: sub a0, a2, a01269; RV32ZBB-NEXT: ret1270;1271; RV64ZBB-LABEL: abd_minmax_i32:1272; RV64ZBB: # %bb.0:1273; RV64ZBB-NEXT: sext.w a1, a11274; RV64ZBB-NEXT: sext.w a0, a01275; RV64ZBB-NEXT: min a2, a0, a11276; RV64ZBB-NEXT: max a0, a0, a11277; RV64ZBB-NEXT: subw a0, a2, a01278; RV64ZBB-NEXT: ret1279 %min = call i32 @llvm.smin.i32(i32 %a, i32 %b)1280 %max = call i32 @llvm.smax.i32(i32 %a, i32 %b)1281 %sub = sub i32 %min, %max1282 ret i32 %sub1283}1284 1285define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {1286; RV32I-LABEL: abd_minmax_i64:1287; RV32I: # %bb.0:1288; RV32I-NEXT: beq a1, a3, .LBB16_21289; RV32I-NEXT: # %bb.1:1290; RV32I-NEXT: slt a6, a1, a31291; RV32I-NEXT: j .LBB16_31292; RV32I-NEXT: .LBB16_2:1293; RV32I-NEXT: sltu a6, a0, a21294; RV32I-NEXT: .LBB16_3:1295; RV32I-NEXT: mv a4, a11296; RV32I-NEXT: mv a5, a01297; RV32I-NEXT: bnez a6, .LBB16_51298; RV32I-NEXT: # %bb.4:1299; RV32I-NEXT: mv a4, a31300; RV32I-NEXT: mv a5, a21301; RV32I-NEXT: .LBB16_5:1302; RV32I-NEXT: beq a1, a3, .LBB16_71303; RV32I-NEXT: # %bb.6:1304; RV32I-NEXT: slt a6, a3, a11305; RV32I-NEXT: beqz a6, .LBB16_81306; RV32I-NEXT: j .LBB16_91307; RV32I-NEXT: .LBB16_7:1308; RV32I-NEXT: sltu a6, a2, a01309; RV32I-NEXT: bnez a6, .LBB16_91310; RV32I-NEXT: .LBB16_8:1311; RV32I-NEXT: mv a1, a31312; RV32I-NEXT: mv a0, a21313; RV32I-NEXT: .LBB16_9:1314; RV32I-NEXT: sltu a2, a5, a01315; RV32I-NEXT: sub a1, a4, a11316; RV32I-NEXT: sub a1, a1, a21317; RV32I-NEXT: sub a0, a5, a01318; RV32I-NEXT: ret1319;1320; RV64I-LABEL: abd_minmax_i64:1321; RV64I: # %bb.0:1322; RV64I-NEXT: mv a2, a01323; RV64I-NEXT: bge a0, a1, .LBB16_31324; RV64I-NEXT: # %bb.1:1325; RV64I-NEXT: bge a1, a0, .LBB16_41326; RV64I-NEXT: .LBB16_2:1327; RV64I-NEXT: sub a0, a2, a01328; RV64I-NEXT: ret1329; RV64I-NEXT: .LBB16_3:1330; RV64I-NEXT: mv a2, a11331; RV64I-NEXT: blt a1, a0, .LBB16_21332; RV64I-NEXT: .LBB16_4:1333; RV64I-NEXT: sub a0, a2, a11334; RV64I-NEXT: ret1335;1336; RV32ZBB-LABEL: abd_minmax_i64:1337; RV32ZBB: # %bb.0:1338; RV32ZBB-NEXT: beq a1, a3, .LBB16_21339; RV32ZBB-NEXT: # %bb.1:1340; RV32ZBB-NEXT: slt a6, a1, a31341; RV32ZBB-NEXT: j .LBB16_31342; RV32ZBB-NEXT: .LBB16_2:1343; RV32ZBB-NEXT: sltu a6, a0, a21344; RV32ZBB-NEXT: .LBB16_3:1345; RV32ZBB-NEXT: mv a4, a11346; RV32ZBB-NEXT: mv a5, a01347; RV32ZBB-NEXT: bnez a6, .LBB16_51348; RV32ZBB-NEXT: # %bb.4:1349; RV32ZBB-NEXT: mv a4, a31350; RV32ZBB-NEXT: mv a5, a21351; RV32ZBB-NEXT: .LBB16_5:1352; RV32ZBB-NEXT: beq a1, a3, .LBB16_71353; RV32ZBB-NEXT: # %bb.6:1354; RV32ZBB-NEXT: slt a6, a3, a11355; RV32ZBB-NEXT: beqz a6, .LBB16_81356; RV32ZBB-NEXT: j .LBB16_91357; RV32ZBB-NEXT: .LBB16_7:1358; RV32ZBB-NEXT: sltu a6, a2, a01359; RV32ZBB-NEXT: bnez a6, .LBB16_91360; RV32ZBB-NEXT: .LBB16_8:1361; RV32ZBB-NEXT: mv a1, a31362; RV32ZBB-NEXT: mv a0, a21363; RV32ZBB-NEXT: .LBB16_9:1364; RV32ZBB-NEXT: sltu a2, a5, a01365; RV32ZBB-NEXT: sub a1, a4, a11366; RV32ZBB-NEXT: sub a1, a1, a21367; RV32ZBB-NEXT: sub a0, a5, a01368; RV32ZBB-NEXT: ret1369;1370; RV64ZBB-LABEL: abd_minmax_i64:1371; RV64ZBB: # %bb.0:1372; RV64ZBB-NEXT: min a2, a0, a11373; RV64ZBB-NEXT: max a0, a0, a11374; RV64ZBB-NEXT: sub a0, a2, a01375; RV64ZBB-NEXT: ret1376 %min = call i64 @llvm.smin.i64(i64 %a, i64 %b)1377 %max = call i64 @llvm.smax.i64(i64 %a, i64 %b)1378 %sub = sub i64 %min, %max1379 ret i64 %sub1380}1381 1382define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {1383; RV32I-LABEL: abd_minmax_i128:1384; RV32I: # %bb.0:1385; RV32I-NEXT: lw a6, 4(a2)1386; RV32I-NEXT: lw a7, 8(a2)1387; RV32I-NEXT: lw t0, 12(a2)1388; RV32I-NEXT: lw a3, 4(a1)1389; RV32I-NEXT: lw a5, 12(a1)1390; RV32I-NEXT: lw a4, 8(a1)1391; RV32I-NEXT: beq a5, t0, .LBB17_21392; RV32I-NEXT: # %bb.1:1393; RV32I-NEXT: slt t1, a5, t01394; RV32I-NEXT: j .LBB17_31395; RV32I-NEXT: .LBB17_2:1396; RV32I-NEXT: sltu t1, a4, a71397; RV32I-NEXT: .LBB17_3:1398; RV32I-NEXT: lw t2, 0(a2)1399; RV32I-NEXT: lw a1, 0(a1)1400; RV32I-NEXT: beq a3, a6, .LBB17_51401; RV32I-NEXT: # %bb.4:1402; RV32I-NEXT: sltu t6, a3, a61403; RV32I-NEXT: j .LBB17_61404; RV32I-NEXT: .LBB17_5:1405; RV32I-NEXT: sltu t6, a1, t21406; RV32I-NEXT: .LBB17_6:1407; RV32I-NEXT: xor a2, a5, t01408; RV32I-NEXT: xor t3, a4, a71409; RV32I-NEXT: or t5, t3, a21410; RV32I-NEXT: beqz t5, .LBB17_81411; RV32I-NEXT: # %bb.7:1412; RV32I-NEXT: mv t6, t11413; RV32I-NEXT: .LBB17_8:1414; RV32I-NEXT: mv a2, a11415; RV32I-NEXT: mv t1, a31416; RV32I-NEXT: mv t4, a51417; RV32I-NEXT: mv t3, a41418; RV32I-NEXT: bnez t6, .LBB17_101419; RV32I-NEXT: # %bb.9:1420; RV32I-NEXT: mv a2, t21421; RV32I-NEXT: mv t1, a61422; RV32I-NEXT: mv t4, t01423; RV32I-NEXT: mv t3, a71424; RV32I-NEXT: .LBB17_10:1425; RV32I-NEXT: beq a5, t0, .LBB17_121426; RV32I-NEXT: # %bb.11:1427; RV32I-NEXT: slt t6, t0, a51428; RV32I-NEXT: j .LBB17_131429; RV32I-NEXT: .LBB17_12:1430; RV32I-NEXT: sltu t6, a7, a41431; RV32I-NEXT: .LBB17_13:1432; RV32I-NEXT: addi sp, sp, -161433; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1434; RV32I-NEXT: beq a3, a6, .LBB17_151435; RV32I-NEXT: # %bb.14:1436; RV32I-NEXT: sltu s0, a6, a31437; RV32I-NEXT: bnez t5, .LBB17_161438; RV32I-NEXT: j .LBB17_171439; RV32I-NEXT: .LBB17_15:1440; RV32I-NEXT: sltu s0, t2, a11441; RV32I-NEXT: beqz t5, .LBB17_171442; RV32I-NEXT: .LBB17_16:1443; RV32I-NEXT: mv s0, t61444; RV32I-NEXT: .LBB17_17:1445; RV32I-NEXT: bnez s0, .LBB17_191446; RV32I-NEXT: # %bb.18:1447; RV32I-NEXT: mv a1, t21448; RV32I-NEXT: mv a3, a61449; RV32I-NEXT: mv a5, t01450; RV32I-NEXT: mv a4, a71451; RV32I-NEXT: .LBB17_19:1452; RV32I-NEXT: sltu a7, t3, a41453; RV32I-NEXT: sub a5, t4, a51454; RV32I-NEXT: sltu a6, a2, a11455; RV32I-NEXT: sub a5, a5, a71456; RV32I-NEXT: mv a7, a61457; RV32I-NEXT: beq t1, a3, .LBB17_211458; RV32I-NEXT: # %bb.20:1459; RV32I-NEXT: sltu a7, t1, a31460; RV32I-NEXT: .LBB17_21:1461; RV32I-NEXT: sub a4, t3, a41462; RV32I-NEXT: sub a3, t1, a31463; RV32I-NEXT: sub a2, a2, a11464; RV32I-NEXT: sltu a1, a4, a71465; RV32I-NEXT: sub a4, a4, a71466; RV32I-NEXT: sub a3, a3, a61467; RV32I-NEXT: sub a5, a5, a11468; RV32I-NEXT: sw a2, 0(a0)1469; RV32I-NEXT: sw a3, 4(a0)1470; RV32I-NEXT: sw a4, 8(a0)1471; RV32I-NEXT: sw a5, 12(a0)1472; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1473; RV32I-NEXT: addi sp, sp, 161474; RV32I-NEXT: ret1475;1476; RV64I-LABEL: abd_minmax_i128:1477; RV64I: # %bb.0:1478; RV64I-NEXT: beq a1, a3, .LBB17_21479; RV64I-NEXT: # %bb.1:1480; RV64I-NEXT: slt a6, a1, a31481; RV64I-NEXT: j .LBB17_31482; RV64I-NEXT: .LBB17_2:1483; RV64I-NEXT: sltu a6, a0, a21484; RV64I-NEXT: .LBB17_3:1485; RV64I-NEXT: mv a4, a11486; RV64I-NEXT: mv a5, a01487; RV64I-NEXT: bnez a6, .LBB17_51488; RV64I-NEXT: # %bb.4:1489; RV64I-NEXT: mv a4, a31490; RV64I-NEXT: mv a5, a21491; RV64I-NEXT: .LBB17_5:1492; RV64I-NEXT: beq a1, a3, .LBB17_71493; RV64I-NEXT: # %bb.6:1494; RV64I-NEXT: slt a6, a3, a11495; RV64I-NEXT: beqz a6, .LBB17_81496; RV64I-NEXT: j .LBB17_91497; RV64I-NEXT: .LBB17_7:1498; RV64I-NEXT: sltu a6, a2, a01499; RV64I-NEXT: bnez a6, .LBB17_91500; RV64I-NEXT: .LBB17_8:1501; RV64I-NEXT: mv a1, a31502; RV64I-NEXT: mv a0, a21503; RV64I-NEXT: .LBB17_9:1504; RV64I-NEXT: sltu a2, a5, a01505; RV64I-NEXT: sub a1, a4, a11506; RV64I-NEXT: sub a1, a1, a21507; RV64I-NEXT: sub a0, a5, a01508; RV64I-NEXT: ret1509;1510; RV32ZBB-LABEL: abd_minmax_i128:1511; RV32ZBB: # %bb.0:1512; RV32ZBB-NEXT: lw a6, 4(a2)1513; RV32ZBB-NEXT: lw a7, 8(a2)1514; RV32ZBB-NEXT: lw t0, 12(a2)1515; RV32ZBB-NEXT: lw a3, 4(a1)1516; RV32ZBB-NEXT: lw a5, 12(a1)1517; RV32ZBB-NEXT: lw a4, 8(a1)1518; RV32ZBB-NEXT: beq a5, t0, .LBB17_21519; RV32ZBB-NEXT: # %bb.1:1520; RV32ZBB-NEXT: slt t1, a5, t01521; RV32ZBB-NEXT: j .LBB17_31522; RV32ZBB-NEXT: .LBB17_2:1523; RV32ZBB-NEXT: sltu t1, a4, a71524; RV32ZBB-NEXT: .LBB17_3:1525; RV32ZBB-NEXT: lw t2, 0(a2)1526; RV32ZBB-NEXT: lw a1, 0(a1)1527; RV32ZBB-NEXT: beq a3, a6, .LBB17_51528; RV32ZBB-NEXT: # %bb.4:1529; RV32ZBB-NEXT: sltu t6, a3, a61530; RV32ZBB-NEXT: j .LBB17_61531; RV32ZBB-NEXT: .LBB17_5:1532; RV32ZBB-NEXT: sltu t6, a1, t21533; RV32ZBB-NEXT: .LBB17_6:1534; RV32ZBB-NEXT: xor a2, a5, t01535; RV32ZBB-NEXT: xor t3, a4, a71536; RV32ZBB-NEXT: or t5, t3, a21537; RV32ZBB-NEXT: beqz t5, .LBB17_81538; RV32ZBB-NEXT: # %bb.7:1539; RV32ZBB-NEXT: mv t6, t11540; RV32ZBB-NEXT: .LBB17_8:1541; RV32ZBB-NEXT: mv a2, a11542; RV32ZBB-NEXT: mv t1, a31543; RV32ZBB-NEXT: mv t4, a51544; RV32ZBB-NEXT: mv t3, a41545; RV32ZBB-NEXT: bnez t6, .LBB17_101546; RV32ZBB-NEXT: # %bb.9:1547; RV32ZBB-NEXT: mv a2, t21548; RV32ZBB-NEXT: mv t1, a61549; RV32ZBB-NEXT: mv t4, t01550; RV32ZBB-NEXT: mv t3, a71551; RV32ZBB-NEXT: .LBB17_10:1552; RV32ZBB-NEXT: beq a5, t0, .LBB17_121553; RV32ZBB-NEXT: # %bb.11:1554; RV32ZBB-NEXT: slt t6, t0, a51555; RV32ZBB-NEXT: j .LBB17_131556; RV32ZBB-NEXT: .LBB17_12:1557; RV32ZBB-NEXT: sltu t6, a7, a41558; RV32ZBB-NEXT: .LBB17_13:1559; RV32ZBB-NEXT: addi sp, sp, -161560; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1561; RV32ZBB-NEXT: beq a3, a6, .LBB17_151562; RV32ZBB-NEXT: # %bb.14:1563; RV32ZBB-NEXT: sltu s0, a6, a31564; RV32ZBB-NEXT: bnez t5, .LBB17_161565; RV32ZBB-NEXT: j .LBB17_171566; RV32ZBB-NEXT: .LBB17_15:1567; RV32ZBB-NEXT: sltu s0, t2, a11568; RV32ZBB-NEXT: beqz t5, .LBB17_171569; RV32ZBB-NEXT: .LBB17_16:1570; RV32ZBB-NEXT: mv s0, t61571; RV32ZBB-NEXT: .LBB17_17:1572; RV32ZBB-NEXT: bnez s0, .LBB17_191573; RV32ZBB-NEXT: # %bb.18:1574; RV32ZBB-NEXT: mv a1, t21575; RV32ZBB-NEXT: mv a3, a61576; RV32ZBB-NEXT: mv a5, t01577; RV32ZBB-NEXT: mv a4, a71578; RV32ZBB-NEXT: .LBB17_19:1579; RV32ZBB-NEXT: sltu a7, t3, a41580; RV32ZBB-NEXT: sub a5, t4, a51581; RV32ZBB-NEXT: sltu a6, a2, a11582; RV32ZBB-NEXT: sub a5, a5, a71583; RV32ZBB-NEXT: mv a7, a61584; RV32ZBB-NEXT: beq t1, a3, .LBB17_211585; RV32ZBB-NEXT: # %bb.20:1586; RV32ZBB-NEXT: sltu a7, t1, a31587; RV32ZBB-NEXT: .LBB17_21:1588; RV32ZBB-NEXT: sub a4, t3, a41589; RV32ZBB-NEXT: sub a3, t1, a31590; RV32ZBB-NEXT: sub a2, a2, a11591; RV32ZBB-NEXT: sltu a1, a4, a71592; RV32ZBB-NEXT: sub a4, a4, a71593; RV32ZBB-NEXT: sub a3, a3, a61594; RV32ZBB-NEXT: sub a5, a5, a11595; RV32ZBB-NEXT: sw a2, 0(a0)1596; RV32ZBB-NEXT: sw a3, 4(a0)1597; RV32ZBB-NEXT: sw a4, 8(a0)1598; RV32ZBB-NEXT: sw a5, 12(a0)1599; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1600; RV32ZBB-NEXT: addi sp, sp, 161601; RV32ZBB-NEXT: ret1602;1603; RV64ZBB-LABEL: abd_minmax_i128:1604; RV64ZBB: # %bb.0:1605; RV64ZBB-NEXT: beq a1, a3, .LBB17_21606; RV64ZBB-NEXT: # %bb.1:1607; RV64ZBB-NEXT: slt a6, a1, a31608; RV64ZBB-NEXT: j .LBB17_31609; RV64ZBB-NEXT: .LBB17_2:1610; RV64ZBB-NEXT: sltu a6, a0, a21611; RV64ZBB-NEXT: .LBB17_3:1612; RV64ZBB-NEXT: mv a4, a11613; RV64ZBB-NEXT: mv a5, a01614; RV64ZBB-NEXT: bnez a6, .LBB17_51615; RV64ZBB-NEXT: # %bb.4:1616; RV64ZBB-NEXT: mv a4, a31617; RV64ZBB-NEXT: mv a5, a21618; RV64ZBB-NEXT: .LBB17_5:1619; RV64ZBB-NEXT: beq a1, a3, .LBB17_71620; RV64ZBB-NEXT: # %bb.6:1621; RV64ZBB-NEXT: slt a6, a3, a11622; RV64ZBB-NEXT: beqz a6, .LBB17_81623; RV64ZBB-NEXT: j .LBB17_91624; RV64ZBB-NEXT: .LBB17_7:1625; RV64ZBB-NEXT: sltu a6, a2, a01626; RV64ZBB-NEXT: bnez a6, .LBB17_91627; RV64ZBB-NEXT: .LBB17_8:1628; RV64ZBB-NEXT: mv a1, a31629; RV64ZBB-NEXT: mv a0, a21630; RV64ZBB-NEXT: .LBB17_9:1631; RV64ZBB-NEXT: sltu a2, a5, a01632; RV64ZBB-NEXT: sub a1, a4, a11633; RV64ZBB-NEXT: sub a1, a1, a21634; RV64ZBB-NEXT: sub a0, a5, a01635; RV64ZBB-NEXT: ret1636 %min = call i128 @llvm.smin.i128(i128 %a, i128 %b)1637 %max = call i128 @llvm.smax.i128(i128 %a, i128 %b)1638 %sub = sub i128 %min, %max1639 ret i128 %sub1640}1641 1642;1643; select(icmp(a,b),sub(a,b),sub(b,a)) -> nabds(a,b)1644;1645 1646define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {1647; RV32I-LABEL: abd_cmp_i8:1648; RV32I: # %bb.0:1649; RV32I-NEXT: slli a2, a0, 241650; RV32I-NEXT: slli a3, a1, 241651; RV32I-NEXT: srai a2, a2, 241652; RV32I-NEXT: srai a3, a3, 241653; RV32I-NEXT: bge a3, a2, .LBB18_21654; RV32I-NEXT: # %bb.1:1655; RV32I-NEXT: sub a0, a1, a01656; RV32I-NEXT: ret1657; RV32I-NEXT: .LBB18_2:1658; RV32I-NEXT: sub a0, a0, a11659; RV32I-NEXT: ret1660;1661; RV64I-LABEL: abd_cmp_i8:1662; RV64I: # %bb.0:1663; RV64I-NEXT: slli a2, a0, 561664; RV64I-NEXT: slli a3, a1, 561665; RV64I-NEXT: srai a2, a2, 561666; RV64I-NEXT: srai a3, a3, 561667; RV64I-NEXT: bge a3, a2, .LBB18_21668; RV64I-NEXT: # %bb.1:1669; RV64I-NEXT: sub a0, a1, a01670; RV64I-NEXT: ret1671; RV64I-NEXT: .LBB18_2:1672; RV64I-NEXT: sub a0, a0, a11673; RV64I-NEXT: ret1674;1675; ZBB-LABEL: abd_cmp_i8:1676; ZBB: # %bb.0:1677; ZBB-NEXT: sext.b a2, a01678; ZBB-NEXT: sext.b a3, a11679; ZBB-NEXT: bge a3, a2, .LBB18_21680; ZBB-NEXT: # %bb.1:1681; ZBB-NEXT: sub a0, a1, a01682; ZBB-NEXT: ret1683; ZBB-NEXT: .LBB18_2:1684; ZBB-NEXT: sub a0, a0, a11685; ZBB-NEXT: ret1686 %cmp = icmp sle i8 %a, %b1687 %ab = sub i8 %a, %b1688 %ba = sub i8 %b, %a1689 %sel = select i1 %cmp, i8 %ab, i8 %ba1690 ret i8 %sel1691}1692 1693define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {1694; RV32I-LABEL: abd_cmp_i16:1695; RV32I: # %bb.0:1696; RV32I-NEXT: slli a2, a1, 161697; RV32I-NEXT: slli a3, a0, 161698; RV32I-NEXT: srai a2, a2, 161699; RV32I-NEXT: srai a3, a3, 161700; RV32I-NEXT: blt a3, a2, .LBB19_21701; RV32I-NEXT: # %bb.1:1702; RV32I-NEXT: sub a0, a1, a01703; RV32I-NEXT: ret1704; RV32I-NEXT: .LBB19_2:1705; RV32I-NEXT: sub a0, a0, a11706; RV32I-NEXT: ret1707;1708; RV64I-LABEL: abd_cmp_i16:1709; RV64I: # %bb.0:1710; RV64I-NEXT: slli a2, a1, 481711; RV64I-NEXT: slli a3, a0, 481712; RV64I-NEXT: srai a2, a2, 481713; RV64I-NEXT: srai a3, a3, 481714; RV64I-NEXT: blt a3, a2, .LBB19_21715; RV64I-NEXT: # %bb.1:1716; RV64I-NEXT: sub a0, a1, a01717; RV64I-NEXT: ret1718; RV64I-NEXT: .LBB19_2:1719; RV64I-NEXT: sub a0, a0, a11720; RV64I-NEXT: ret1721;1722; ZBB-LABEL: abd_cmp_i16:1723; ZBB: # %bb.0:1724; ZBB-NEXT: sext.h a2, a11725; ZBB-NEXT: sext.h a3, a01726; ZBB-NEXT: blt a3, a2, .LBB19_21727; ZBB-NEXT: # %bb.1:1728; ZBB-NEXT: sub a0, a1, a01729; ZBB-NEXT: ret1730; ZBB-NEXT: .LBB19_2:1731; ZBB-NEXT: sub a0, a0, a11732; ZBB-NEXT: ret1733 %cmp = icmp slt i16 %a, %b1734 %ab = sub i16 %a, %b1735 %ba = sub i16 %b, %a1736 %sel = select i1 %cmp, i16 %ab, i16 %ba1737 ret i16 %sel1738}1739 1740define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {1741; RV32I-LABEL: abd_cmp_i32:1742; RV32I: # %bb.0:1743; RV32I-NEXT: bge a0, a1, .LBB20_21744; RV32I-NEXT: # %bb.1:1745; RV32I-NEXT: sub a0, a0, a11746; RV32I-NEXT: ret1747; RV32I-NEXT: .LBB20_2:1748; RV32I-NEXT: sub a0, a1, a01749; RV32I-NEXT: ret1750;1751; RV64I-LABEL: abd_cmp_i32:1752; RV64I: # %bb.0:1753; RV64I-NEXT: sext.w a2, a11754; RV64I-NEXT: sext.w a3, a01755; RV64I-NEXT: bge a3, a2, .LBB20_21756; RV64I-NEXT: # %bb.1:1757; RV64I-NEXT: subw a0, a0, a11758; RV64I-NEXT: ret1759; RV64I-NEXT: .LBB20_2:1760; RV64I-NEXT: subw a0, a1, a01761; RV64I-NEXT: ret1762;1763; RV32ZBB-LABEL: abd_cmp_i32:1764; RV32ZBB: # %bb.0:1765; RV32ZBB-NEXT: bge a0, a1, .LBB20_21766; RV32ZBB-NEXT: # %bb.1:1767; RV32ZBB-NEXT: sub a0, a0, a11768; RV32ZBB-NEXT: ret1769; RV32ZBB-NEXT: .LBB20_2:1770; RV32ZBB-NEXT: sub a0, a1, a01771; RV32ZBB-NEXT: ret1772;1773; RV64ZBB-LABEL: abd_cmp_i32:1774; RV64ZBB: # %bb.0:1775; RV64ZBB-NEXT: sext.w a2, a11776; RV64ZBB-NEXT: sext.w a3, a01777; RV64ZBB-NEXT: bge a3, a2, .LBB20_21778; RV64ZBB-NEXT: # %bb.1:1779; RV64ZBB-NEXT: subw a0, a0, a11780; RV64ZBB-NEXT: ret1781; RV64ZBB-NEXT: .LBB20_2:1782; RV64ZBB-NEXT: subw a0, a1, a01783; RV64ZBB-NEXT: ret1784 %cmp = icmp sge i32 %a, %b1785 %ab = sub i32 %a, %b1786 %ba = sub i32 %b, %a1787 %sel = select i1 %cmp, i32 %ba, i32 %ab1788 ret i32 %sel1789}1790 1791define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {1792; RV32I-LABEL: abd_cmp_i64:1793; RV32I: # %bb.0:1794; RV32I-NEXT: sltu a4, a0, a21795; RV32I-NEXT: mv a5, a41796; RV32I-NEXT: beq a1, a3, .LBB21_21797; RV32I-NEXT: # %bb.1:1798; RV32I-NEXT: slt a5, a1, a31799; RV32I-NEXT: .LBB21_2:1800; RV32I-NEXT: bnez a5, .LBB21_41801; RV32I-NEXT: # %bb.3:1802; RV32I-NEXT: sltu a4, a2, a01803; RV32I-NEXT: sub a1, a3, a11804; RV32I-NEXT: sub a1, a1, a41805; RV32I-NEXT: sub a0, a2, a01806; RV32I-NEXT: ret1807; RV32I-NEXT: .LBB21_4:1808; RV32I-NEXT: sub a1, a1, a31809; RV32I-NEXT: sub a1, a1, a41810; RV32I-NEXT: sub a0, a0, a21811; RV32I-NEXT: ret1812;1813; RV64I-LABEL: abd_cmp_i64:1814; RV64I: # %bb.0:1815; RV64I-NEXT: blt a0, a1, .LBB21_21816; RV64I-NEXT: # %bb.1:1817; RV64I-NEXT: sub a0, a1, a01818; RV64I-NEXT: ret1819; RV64I-NEXT: .LBB21_2:1820; RV64I-NEXT: sub a0, a0, a11821; RV64I-NEXT: ret1822;1823; RV32ZBB-LABEL: abd_cmp_i64:1824; RV32ZBB: # %bb.0:1825; RV32ZBB-NEXT: sltu a4, a0, a21826; RV32ZBB-NEXT: mv a5, a41827; RV32ZBB-NEXT: beq a1, a3, .LBB21_21828; RV32ZBB-NEXT: # %bb.1:1829; RV32ZBB-NEXT: slt a5, a1, a31830; RV32ZBB-NEXT: .LBB21_2:1831; RV32ZBB-NEXT: bnez a5, .LBB21_41832; RV32ZBB-NEXT: # %bb.3:1833; RV32ZBB-NEXT: sltu a4, a2, a01834; RV32ZBB-NEXT: sub a1, a3, a11835; RV32ZBB-NEXT: sub a1, a1, a41836; RV32ZBB-NEXT: sub a0, a2, a01837; RV32ZBB-NEXT: ret1838; RV32ZBB-NEXT: .LBB21_4:1839; RV32ZBB-NEXT: sub a1, a1, a31840; RV32ZBB-NEXT: sub a1, a1, a41841; RV32ZBB-NEXT: sub a0, a0, a21842; RV32ZBB-NEXT: ret1843;1844; RV64ZBB-LABEL: abd_cmp_i64:1845; RV64ZBB: # %bb.0:1846; RV64ZBB-NEXT: blt a0, a1, .LBB21_21847; RV64ZBB-NEXT: # %bb.1:1848; RV64ZBB-NEXT: sub a0, a1, a01849; RV64ZBB-NEXT: ret1850; RV64ZBB-NEXT: .LBB21_2:1851; RV64ZBB-NEXT: sub a0, a0, a11852; RV64ZBB-NEXT: ret1853 %cmp = icmp slt i64 %a, %b1854 %ab = sub i64 %a, %b1855 %ba = sub i64 %b, %a1856 %sel = select i1 %cmp, i64 %ab, i64 %ba1857 ret i64 %sel1858}1859 1860define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {1861; RV32I-LABEL: abd_cmp_i128:1862; RV32I: # %bb.0:1863; RV32I-NEXT: lw a3, 0(a2)1864; RV32I-NEXT: lw a4, 4(a2)1865; RV32I-NEXT: lw a5, 8(a2)1866; RV32I-NEXT: lw a7, 12(a2)1867; RV32I-NEXT: lw a2, 0(a1)1868; RV32I-NEXT: lw a6, 8(a1)1869; RV32I-NEXT: lw t1, 12(a1)1870; RV32I-NEXT: lw a1, 4(a1)1871; RV32I-NEXT: sltu t0, a6, a51872; RV32I-NEXT: mv t4, t01873; RV32I-NEXT: beq t1, a7, .LBB22_21874; RV32I-NEXT: # %bb.1:1875; RV32I-NEXT: slt t4, t1, a71876; RV32I-NEXT: .LBB22_2:1877; RV32I-NEXT: sltu t2, a2, a31878; RV32I-NEXT: mv t3, t21879; RV32I-NEXT: beq a1, a4, .LBB22_41880; RV32I-NEXT: # %bb.3:1881; RV32I-NEXT: sltu t3, a1, a41882; RV32I-NEXT: .LBB22_4:1883; RV32I-NEXT: xor t5, t1, a71884; RV32I-NEXT: xor t6, a6, a51885; RV32I-NEXT: or t5, t6, t51886; RV32I-NEXT: mv t6, t31887; RV32I-NEXT: beqz t5, .LBB22_61888; RV32I-NEXT: # %bb.5:1889; RV32I-NEXT: mv t6, t41890; RV32I-NEXT: .LBB22_6:1891; RV32I-NEXT: sltu t4, a3, a21892; RV32I-NEXT: mv t5, t41893; RV32I-NEXT: beq a1, a4, .LBB22_81894; RV32I-NEXT: # %bb.7:1895; RV32I-NEXT: sltu t5, a4, a11896; RV32I-NEXT: .LBB22_8:1897; RV32I-NEXT: bnez t6, .LBB22_101898; RV32I-NEXT: # %bb.9:1899; RV32I-NEXT: sltu t0, a5, a61900; RV32I-NEXT: sub a7, a7, t11901; RV32I-NEXT: sub a5, a5, a61902; RV32I-NEXT: sub a4, a4, a11903; RV32I-NEXT: sub a6, a7, t01904; RV32I-NEXT: sltu a7, a5, t51905; RV32I-NEXT: sub a1, a5, t51906; RV32I-NEXT: sub a5, a4, t41907; RV32I-NEXT: sub a4, a6, a71908; RV32I-NEXT: sub a2, a3, a21909; RV32I-NEXT: j .LBB22_111910; RV32I-NEXT: .LBB22_10:1911; RV32I-NEXT: sub a7, t1, a71912; RV32I-NEXT: sub a5, a6, a51913; RV32I-NEXT: sub a4, a1, a41914; RV32I-NEXT: sub a6, a7, t01915; RV32I-NEXT: sltu a7, a5, t31916; RV32I-NEXT: sub a1, a5, t31917; RV32I-NEXT: sub a5, a4, t21918; RV32I-NEXT: sub a4, a6, a71919; RV32I-NEXT: sub a2, a2, a31920; RV32I-NEXT: .LBB22_11:1921; RV32I-NEXT: sw a2, 0(a0)1922; RV32I-NEXT: sw a5, 4(a0)1923; RV32I-NEXT: sw a1, 8(a0)1924; RV32I-NEXT: sw a4, 12(a0)1925; RV32I-NEXT: ret1926;1927; RV64I-LABEL: abd_cmp_i128:1928; RV64I: # %bb.0:1929; RV64I-NEXT: sltu a4, a0, a21930; RV64I-NEXT: mv a5, a41931; RV64I-NEXT: beq a1, a3, .LBB22_21932; RV64I-NEXT: # %bb.1:1933; RV64I-NEXT: slt a5, a1, a31934; RV64I-NEXT: .LBB22_2:1935; RV64I-NEXT: bnez a5, .LBB22_41936; RV64I-NEXT: # %bb.3:1937; RV64I-NEXT: sltu a4, a2, a01938; RV64I-NEXT: sub a1, a3, a11939; RV64I-NEXT: sub a1, a1, a41940; RV64I-NEXT: sub a0, a2, a01941; RV64I-NEXT: ret1942; RV64I-NEXT: .LBB22_4:1943; RV64I-NEXT: sub a1, a1, a31944; RV64I-NEXT: sub a1, a1, a41945; RV64I-NEXT: sub a0, a0, a21946; RV64I-NEXT: ret1947;1948; RV32ZBB-LABEL: abd_cmp_i128:1949; RV32ZBB: # %bb.0:1950; RV32ZBB-NEXT: lw a3, 0(a2)1951; RV32ZBB-NEXT: lw a4, 4(a2)1952; RV32ZBB-NEXT: lw a5, 8(a2)1953; RV32ZBB-NEXT: lw a7, 12(a2)1954; RV32ZBB-NEXT: lw a2, 0(a1)1955; RV32ZBB-NEXT: lw a6, 8(a1)1956; RV32ZBB-NEXT: lw t1, 12(a1)1957; RV32ZBB-NEXT: lw a1, 4(a1)1958; RV32ZBB-NEXT: sltu t0, a6, a51959; RV32ZBB-NEXT: mv t4, t01960; RV32ZBB-NEXT: beq t1, a7, .LBB22_21961; RV32ZBB-NEXT: # %bb.1:1962; RV32ZBB-NEXT: slt t4, t1, a71963; RV32ZBB-NEXT: .LBB22_2:1964; RV32ZBB-NEXT: sltu t2, a2, a31965; RV32ZBB-NEXT: mv t3, t21966; RV32ZBB-NEXT: beq a1, a4, .LBB22_41967; RV32ZBB-NEXT: # %bb.3:1968; RV32ZBB-NEXT: sltu t3, a1, a41969; RV32ZBB-NEXT: .LBB22_4:1970; RV32ZBB-NEXT: xor t5, t1, a71971; RV32ZBB-NEXT: xor t6, a6, a51972; RV32ZBB-NEXT: or t5, t6, t51973; RV32ZBB-NEXT: mv t6, t31974; RV32ZBB-NEXT: beqz t5, .LBB22_61975; RV32ZBB-NEXT: # %bb.5:1976; RV32ZBB-NEXT: mv t6, t41977; RV32ZBB-NEXT: .LBB22_6:1978; RV32ZBB-NEXT: sltu t4, a3, a21979; RV32ZBB-NEXT: mv t5, t41980; RV32ZBB-NEXT: beq a1, a4, .LBB22_81981; RV32ZBB-NEXT: # %bb.7:1982; RV32ZBB-NEXT: sltu t5, a4, a11983; RV32ZBB-NEXT: .LBB22_8:1984; RV32ZBB-NEXT: bnez t6, .LBB22_101985; RV32ZBB-NEXT: # %bb.9:1986; RV32ZBB-NEXT: sltu t0, a5, a61987; RV32ZBB-NEXT: sub a7, a7, t11988; RV32ZBB-NEXT: sub a5, a5, a61989; RV32ZBB-NEXT: sub a4, a4, a11990; RV32ZBB-NEXT: sub a6, a7, t01991; RV32ZBB-NEXT: sltu a7, a5, t51992; RV32ZBB-NEXT: sub a1, a5, t51993; RV32ZBB-NEXT: sub a5, a4, t41994; RV32ZBB-NEXT: sub a4, a6, a71995; RV32ZBB-NEXT: sub a2, a3, a21996; RV32ZBB-NEXT: j .LBB22_111997; RV32ZBB-NEXT: .LBB22_10:1998; RV32ZBB-NEXT: sub a7, t1, a71999; RV32ZBB-NEXT: sub a5, a6, a52000; RV32ZBB-NEXT: sub a4, a1, a42001; RV32ZBB-NEXT: sub a6, a7, t02002; RV32ZBB-NEXT: sltu a7, a5, t32003; RV32ZBB-NEXT: sub a1, a5, t32004; RV32ZBB-NEXT: sub a5, a4, t22005; RV32ZBB-NEXT: sub a4, a6, a72006; RV32ZBB-NEXT: sub a2, a2, a32007; RV32ZBB-NEXT: .LBB22_11:2008; RV32ZBB-NEXT: sw a2, 0(a0)2009; RV32ZBB-NEXT: sw a5, 4(a0)2010; RV32ZBB-NEXT: sw a1, 8(a0)2011; RV32ZBB-NEXT: sw a4, 12(a0)2012; RV32ZBB-NEXT: ret2013;2014; RV64ZBB-LABEL: abd_cmp_i128:2015; RV64ZBB: # %bb.0:2016; RV64ZBB-NEXT: sltu a4, a0, a22017; RV64ZBB-NEXT: mv a5, a42018; RV64ZBB-NEXT: beq a1, a3, .LBB22_22019; RV64ZBB-NEXT: # %bb.1:2020; RV64ZBB-NEXT: slt a5, a1, a32021; RV64ZBB-NEXT: .LBB22_2:2022; RV64ZBB-NEXT: bnez a5, .LBB22_42023; RV64ZBB-NEXT: # %bb.3:2024; RV64ZBB-NEXT: sltu a4, a2, a02025; RV64ZBB-NEXT: sub a1, a3, a12026; RV64ZBB-NEXT: sub a1, a1, a42027; RV64ZBB-NEXT: sub a0, a2, a02028; RV64ZBB-NEXT: ret2029; RV64ZBB-NEXT: .LBB22_4:2030; RV64ZBB-NEXT: sub a1, a1, a32031; RV64ZBB-NEXT: sub a1, a1, a42032; RV64ZBB-NEXT: sub a0, a0, a22033; RV64ZBB-NEXT: ret2034 %cmp = icmp slt i128 %a, %b2035 %ab = sub i128 %a, %b2036 %ba = sub i128 %b, %a2037 %sel = select i1 %cmp, i128 %ab, i128 %ba2038 ret i128 %sel2039}2040 2041;2042; nabs(sub_nsw(x, y)) -> nabds(a,b)2043;2044 2045define i8 @abd_subnsw_i8(i8 %a, i8 %b) nounwind {2046; RV32I-LABEL: abd_subnsw_i8:2047; RV32I: # %bb.0:2048; RV32I-NEXT: sub a0, a0, a12049; RV32I-NEXT: slli a1, a0, 242050; RV32I-NEXT: srai a1, a1, 312051; RV32I-NEXT: xor a0, a0, a12052; RV32I-NEXT: sub a0, a1, a02053; RV32I-NEXT: ret2054;2055; RV64I-LABEL: abd_subnsw_i8:2056; RV64I: # %bb.0:2057; RV64I-NEXT: sub a0, a0, a12058; RV64I-NEXT: slli a1, a0, 562059; RV64I-NEXT: srai a1, a1, 632060; RV64I-NEXT: xor a0, a0, a12061; RV64I-NEXT: sub a0, a1, a02062; RV64I-NEXT: ret2063;2064; RV32ZBB-LABEL: abd_subnsw_i8:2065; RV32ZBB: # %bb.0:2066; RV32ZBB-NEXT: sub a0, a0, a12067; RV32ZBB-NEXT: slli a1, a0, 242068; RV32ZBB-NEXT: srai a1, a1, 312069; RV32ZBB-NEXT: xor a0, a0, a12070; RV32ZBB-NEXT: sub a0, a1, a02071; RV32ZBB-NEXT: ret2072;2073; RV64ZBB-LABEL: abd_subnsw_i8:2074; RV64ZBB: # %bb.0:2075; RV64ZBB-NEXT: sub a0, a0, a12076; RV64ZBB-NEXT: slli a1, a0, 562077; RV64ZBB-NEXT: srai a1, a1, 632078; RV64ZBB-NEXT: xor a0, a0, a12079; RV64ZBB-NEXT: sub a0, a1, a02080; RV64ZBB-NEXT: ret2081 %sub = sub nsw i8 %a, %b2082 %abs = call i8 @llvm.abs.i8(i8 %sub, i1 false)2083 %nabs = sub i8 0, %abs2084 ret i8 %nabs2085}2086 2087define i8 @abd_subnsw_i8_undef(i8 %a, i8 %b) nounwind {2088; RV32I-LABEL: abd_subnsw_i8_undef:2089; RV32I: # %bb.0:2090; RV32I-NEXT: sub a0, a0, a12091; RV32I-NEXT: slli a1, a0, 242092; RV32I-NEXT: srai a1, a1, 312093; RV32I-NEXT: xor a0, a0, a12094; RV32I-NEXT: sub a0, a1, a02095; RV32I-NEXT: ret2096;2097; RV64I-LABEL: abd_subnsw_i8_undef:2098; RV64I: # %bb.0:2099; RV64I-NEXT: sub a0, a0, a12100; RV64I-NEXT: slli a1, a0, 562101; RV64I-NEXT: srai a1, a1, 632102; RV64I-NEXT: xor a0, a0, a12103; RV64I-NEXT: sub a0, a1, a02104; RV64I-NEXT: ret2105;2106; RV32ZBB-LABEL: abd_subnsw_i8_undef:2107; RV32ZBB: # %bb.0:2108; RV32ZBB-NEXT: sub a0, a0, a12109; RV32ZBB-NEXT: slli a1, a0, 242110; RV32ZBB-NEXT: srai a1, a1, 312111; RV32ZBB-NEXT: xor a0, a0, a12112; RV32ZBB-NEXT: sub a0, a1, a02113; RV32ZBB-NEXT: ret2114;2115; RV64ZBB-LABEL: abd_subnsw_i8_undef:2116; RV64ZBB: # %bb.0:2117; RV64ZBB-NEXT: sub a0, a0, a12118; RV64ZBB-NEXT: slli a1, a0, 562119; RV64ZBB-NEXT: srai a1, a1, 632120; RV64ZBB-NEXT: xor a0, a0, a12121; RV64ZBB-NEXT: sub a0, a1, a02122; RV64ZBB-NEXT: ret2123 %sub = sub nsw i8 %a, %b2124 %abs = call i8 @llvm.abs.i8(i8 %sub, i1 true)2125 %nabs = sub i8 0, %abs2126 ret i8 %nabs2127}2128 2129define i16 @abd_subnsw_i16(i16 %a, i16 %b) nounwind {2130; RV32I-LABEL: abd_subnsw_i16:2131; RV32I: # %bb.0:2132; RV32I-NEXT: sub a0, a0, a12133; RV32I-NEXT: slli a1, a0, 162134; RV32I-NEXT: srai a1, a1, 312135; RV32I-NEXT: xor a0, a0, a12136; RV32I-NEXT: sub a0, a1, a02137; RV32I-NEXT: ret2138;2139; RV64I-LABEL: abd_subnsw_i16:2140; RV64I: # %bb.0:2141; RV64I-NEXT: sub a0, a0, a12142; RV64I-NEXT: slli a1, a0, 482143; RV64I-NEXT: srai a1, a1, 632144; RV64I-NEXT: xor a0, a0, a12145; RV64I-NEXT: sub a0, a1, a02146; RV64I-NEXT: ret2147;2148; RV32ZBB-LABEL: abd_subnsw_i16:2149; RV32ZBB: # %bb.0:2150; RV32ZBB-NEXT: sub a0, a0, a12151; RV32ZBB-NEXT: slli a1, a0, 162152; RV32ZBB-NEXT: srai a1, a1, 312153; RV32ZBB-NEXT: xor a0, a0, a12154; RV32ZBB-NEXT: sub a0, a1, a02155; RV32ZBB-NEXT: ret2156;2157; RV64ZBB-LABEL: abd_subnsw_i16:2158; RV64ZBB: # %bb.0:2159; RV64ZBB-NEXT: sub a0, a0, a12160; RV64ZBB-NEXT: slli a1, a0, 482161; RV64ZBB-NEXT: srai a1, a1, 632162; RV64ZBB-NEXT: xor a0, a0, a12163; RV64ZBB-NEXT: sub a0, a1, a02164; RV64ZBB-NEXT: ret2165 %sub = sub nsw i16 %a, %b2166 %abs = call i16 @llvm.abs.i16(i16 %sub, i1 false)2167 %nabs = sub i16 0, %abs2168 ret i16 %nabs2169}2170 2171define i16 @abd_subnsw_i16_undef(i16 %a, i16 %b) nounwind {2172; RV32I-LABEL: abd_subnsw_i16_undef:2173; RV32I: # %bb.0:2174; RV32I-NEXT: sub a0, a0, a12175; RV32I-NEXT: slli a1, a0, 162176; RV32I-NEXT: srai a1, a1, 312177; RV32I-NEXT: xor a0, a0, a12178; RV32I-NEXT: sub a0, a1, a02179; RV32I-NEXT: ret2180;2181; RV64I-LABEL: abd_subnsw_i16_undef:2182; RV64I: # %bb.0:2183; RV64I-NEXT: sub a0, a0, a12184; RV64I-NEXT: slli a1, a0, 482185; RV64I-NEXT: srai a1, a1, 632186; RV64I-NEXT: xor a0, a0, a12187; RV64I-NEXT: sub a0, a1, a02188; RV64I-NEXT: ret2189;2190; RV32ZBB-LABEL: abd_subnsw_i16_undef:2191; RV32ZBB: # %bb.0:2192; RV32ZBB-NEXT: sub a0, a0, a12193; RV32ZBB-NEXT: slli a1, a0, 162194; RV32ZBB-NEXT: srai a1, a1, 312195; RV32ZBB-NEXT: xor a0, a0, a12196; RV32ZBB-NEXT: sub a0, a1, a02197; RV32ZBB-NEXT: ret2198;2199; RV64ZBB-LABEL: abd_subnsw_i16_undef:2200; RV64ZBB: # %bb.0:2201; RV64ZBB-NEXT: sub a0, a0, a12202; RV64ZBB-NEXT: slli a1, a0, 482203; RV64ZBB-NEXT: srai a1, a1, 632204; RV64ZBB-NEXT: xor a0, a0, a12205; RV64ZBB-NEXT: sub a0, a1, a02206; RV64ZBB-NEXT: ret2207 %sub = sub nsw i16 %a, %b2208 %abs = call i16 @llvm.abs.i16(i16 %sub, i1 true)2209 %nabs = sub i16 0, %abs2210 ret i16 %nabs2211}2212 2213define i32 @abd_subnsw_i32(i32 %a, i32 %b) nounwind {2214; RV32I-LABEL: abd_subnsw_i32:2215; RV32I: # %bb.0:2216; RV32I-NEXT: sub a0, a0, a12217; RV32I-NEXT: srai a1, a0, 312218; RV32I-NEXT: xor a0, a0, a12219; RV32I-NEXT: sub a0, a1, a02220; RV32I-NEXT: ret2221;2222; RV64I-LABEL: abd_subnsw_i32:2223; RV64I: # %bb.0:2224; RV64I-NEXT: sub a0, a0, a12225; RV64I-NEXT: sraiw a1, a0, 312226; RV64I-NEXT: xor a0, a0, a12227; RV64I-NEXT: subw a0, a1, a02228; RV64I-NEXT: ret2229;2230; RV32ZBB-LABEL: abd_subnsw_i32:2231; RV32ZBB: # %bb.0:2232; RV32ZBB-NEXT: sub a0, a0, a12233; RV32ZBB-NEXT: neg a1, a02234; RV32ZBB-NEXT: min a0, a0, a12235; RV32ZBB-NEXT: ret2236;2237; RV64ZBB-LABEL: abd_subnsw_i32:2238; RV64ZBB: # %bb.0:2239; RV64ZBB-NEXT: sub a0, a0, a12240; RV64ZBB-NEXT: sraiw a1, a0, 312241; RV64ZBB-NEXT: xor a0, a0, a12242; RV64ZBB-NEXT: subw a0, a1, a02243; RV64ZBB-NEXT: ret2244 %sub = sub nsw i32 %a, %b2245 %abs = call i32 @llvm.abs.i32(i32 %sub, i1 false)2246 %nabs = sub i32 0, %abs2247 ret i32 %nabs2248}2249 2250define i32 @abd_subnsw_i32_undef(i32 %a, i32 %b) nounwind {2251; RV32I-LABEL: abd_subnsw_i32_undef:2252; RV32I: # %bb.0:2253; RV32I-NEXT: sub a0, a0, a12254; RV32I-NEXT: srai a1, a0, 312255; RV32I-NEXT: xor a0, a0, a12256; RV32I-NEXT: sub a0, a1, a02257; RV32I-NEXT: ret2258;2259; RV64I-LABEL: abd_subnsw_i32_undef:2260; RV64I: # %bb.0:2261; RV64I-NEXT: sub a0, a0, a12262; RV64I-NEXT: sraiw a1, a0, 312263; RV64I-NEXT: xor a0, a0, a12264; RV64I-NEXT: subw a0, a1, a02265; RV64I-NEXT: ret2266;2267; RV32ZBB-LABEL: abd_subnsw_i32_undef:2268; RV32ZBB: # %bb.0:2269; RV32ZBB-NEXT: sub a0, a0, a12270; RV32ZBB-NEXT: neg a1, a02271; RV32ZBB-NEXT: min a0, a0, a12272; RV32ZBB-NEXT: ret2273;2274; RV64ZBB-LABEL: abd_subnsw_i32_undef:2275; RV64ZBB: # %bb.0:2276; RV64ZBB-NEXT: sub a0, a0, a12277; RV64ZBB-NEXT: sraiw a1, a0, 312278; RV64ZBB-NEXT: xor a0, a0, a12279; RV64ZBB-NEXT: subw a0, a1, a02280; RV64ZBB-NEXT: ret2281 %sub = sub nsw i32 %a, %b2282 %abs = call i32 @llvm.abs.i32(i32 %sub, i1 true)2283 %nabs = sub i32 0, %abs2284 ret i32 %nabs2285}2286 2287define i64 @abd_subnsw_i64(i64 %a, i64 %b) nounwind {2288; RV32I-LABEL: abd_subnsw_i64:2289; RV32I: # %bb.0:2290; RV32I-NEXT: sltu a4, a0, a22291; RV32I-NEXT: sub a1, a1, a32292; RV32I-NEXT: sub a0, a0, a22293; RV32I-NEXT: sub a1, a1, a42294; RV32I-NEXT: srai a2, a1, 312295; RV32I-NEXT: xor a0, a0, a22296; RV32I-NEXT: xor a1, a1, a22297; RV32I-NEXT: sltu a3, a2, a02298; RV32I-NEXT: sub a1, a2, a12299; RV32I-NEXT: sub a1, a1, a32300; RV32I-NEXT: sub a0, a2, a02301; RV32I-NEXT: ret2302;2303; RV64I-LABEL: abd_subnsw_i64:2304; RV64I: # %bb.0:2305; RV64I-NEXT: sub a0, a0, a12306; RV64I-NEXT: srai a1, a0, 632307; RV64I-NEXT: xor a0, a0, a12308; RV64I-NEXT: sub a0, a1, a02309; RV64I-NEXT: ret2310;2311; RV32ZBB-LABEL: abd_subnsw_i64:2312; RV32ZBB: # %bb.0:2313; RV32ZBB-NEXT: sltu a4, a0, a22314; RV32ZBB-NEXT: sub a1, a1, a32315; RV32ZBB-NEXT: sub a0, a0, a22316; RV32ZBB-NEXT: sub a1, a1, a42317; RV32ZBB-NEXT: srai a2, a1, 312318; RV32ZBB-NEXT: xor a0, a0, a22319; RV32ZBB-NEXT: xor a1, a1, a22320; RV32ZBB-NEXT: sltu a3, a2, a02321; RV32ZBB-NEXT: sub a1, a2, a12322; RV32ZBB-NEXT: sub a1, a1, a32323; RV32ZBB-NEXT: sub a0, a2, a02324; RV32ZBB-NEXT: ret2325;2326; RV64ZBB-LABEL: abd_subnsw_i64:2327; RV64ZBB: # %bb.0:2328; RV64ZBB-NEXT: sub a0, a0, a12329; RV64ZBB-NEXT: neg a1, a02330; RV64ZBB-NEXT: min a0, a0, a12331; RV64ZBB-NEXT: ret2332 %sub = sub nsw i64 %a, %b2333 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)2334 %nabs = sub i64 0, %abs2335 ret i64 %nabs2336}2337 2338define i64 @abd_subnsw_i64_undef(i64 %a, i64 %b) nounwind {2339; RV32I-LABEL: abd_subnsw_i64_undef:2340; RV32I: # %bb.0:2341; RV32I-NEXT: sltu a4, a0, a22342; RV32I-NEXT: sub a1, a1, a32343; RV32I-NEXT: sub a0, a0, a22344; RV32I-NEXT: sub a1, a1, a42345; RV32I-NEXT: srai a2, a1, 312346; RV32I-NEXT: xor a0, a0, a22347; RV32I-NEXT: xor a1, a1, a22348; RV32I-NEXT: sltu a3, a2, a02349; RV32I-NEXT: sub a1, a2, a12350; RV32I-NEXT: sub a1, a1, a32351; RV32I-NEXT: sub a0, a2, a02352; RV32I-NEXT: ret2353;2354; RV64I-LABEL: abd_subnsw_i64_undef:2355; RV64I: # %bb.0:2356; RV64I-NEXT: sub a0, a0, a12357; RV64I-NEXT: srai a1, a0, 632358; RV64I-NEXT: xor a0, a0, a12359; RV64I-NEXT: sub a0, a1, a02360; RV64I-NEXT: ret2361;2362; RV32ZBB-LABEL: abd_subnsw_i64_undef:2363; RV32ZBB: # %bb.0:2364; RV32ZBB-NEXT: sltu a4, a0, a22365; RV32ZBB-NEXT: sub a1, a1, a32366; RV32ZBB-NEXT: sub a0, a0, a22367; RV32ZBB-NEXT: sub a1, a1, a42368; RV32ZBB-NEXT: srai a2, a1, 312369; RV32ZBB-NEXT: xor a0, a0, a22370; RV32ZBB-NEXT: xor a1, a1, a22371; RV32ZBB-NEXT: sltu a3, a2, a02372; RV32ZBB-NEXT: sub a1, a2, a12373; RV32ZBB-NEXT: sub a1, a1, a32374; RV32ZBB-NEXT: sub a0, a2, a02375; RV32ZBB-NEXT: ret2376;2377; RV64ZBB-LABEL: abd_subnsw_i64_undef:2378; RV64ZBB: # %bb.0:2379; RV64ZBB-NEXT: sub a0, a0, a12380; RV64ZBB-NEXT: neg a1, a02381; RV64ZBB-NEXT: min a0, a0, a12382; RV64ZBB-NEXT: ret2383 %sub = sub nsw i64 %a, %b2384 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)2385 %nabs = sub i64 0, %abs2386 ret i64 %nabs2387}2388 2389define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {2390; RV32I-LABEL: abd_subnsw_i128:2391; RV32I: # %bb.0:2392; RV32I-NEXT: lw a3, 0(a2)2393; RV32I-NEXT: lw a4, 4(a2)2394; RV32I-NEXT: lw a5, 8(a2)2395; RV32I-NEXT: lw a6, 12(a2)2396; RV32I-NEXT: lw t0, 8(a1)2397; RV32I-NEXT: lw t1, 12(a1)2398; RV32I-NEXT: lw a2, 0(a1)2399; RV32I-NEXT: lw a7, 4(a1)2400; RV32I-NEXT: sltu a1, t0, a52401; RV32I-NEXT: sub t1, t1, a62402; RV32I-NEXT: sltu a6, a2, a32403; RV32I-NEXT: sub a1, t1, a12404; RV32I-NEXT: mv t1, a62405; RV32I-NEXT: beq a7, a4, .LBB31_22406; RV32I-NEXT: # %bb.1:2407; RV32I-NEXT: sltu t1, a7, a42408; RV32I-NEXT: .LBB31_2:2409; RV32I-NEXT: sub a5, t0, a52410; RV32I-NEXT: sub a4, a7, a42411; RV32I-NEXT: sub a3, a2, a32412; RV32I-NEXT: sltu a2, a5, t12413; RV32I-NEXT: sub t0, a4, a62414; RV32I-NEXT: sub a4, a5, t12415; RV32I-NEXT: sub a5, a1, a22416; RV32I-NEXT: srai a1, a5, 312417; RV32I-NEXT: xor a2, a4, a12418; RV32I-NEXT: xor a5, a5, a12419; RV32I-NEXT: xor a4, a3, a12420; RV32I-NEXT: sltu a3, a1, a22421; RV32I-NEXT: sub a6, a1, a52422; RV32I-NEXT: sltu a5, a1, a42423; RV32I-NEXT: sub a3, a6, a32424; RV32I-NEXT: xor a7, t0, a12425; RV32I-NEXT: mv a6, a52426; RV32I-NEXT: beqz t0, .LBB31_42427; RV32I-NEXT: # %bb.3:2428; RV32I-NEXT: sltu a6, a1, a72429; RV32I-NEXT: .LBB31_4:2430; RV32I-NEXT: sub a2, a1, a22431; RV32I-NEXT: sub a7, a1, a72432; RV32I-NEXT: sub a1, a1, a42433; RV32I-NEXT: sltu a4, a2, a62434; RV32I-NEXT: sub a2, a2, a62435; RV32I-NEXT: sub a5, a7, a52436; RV32I-NEXT: sub a3, a3, a42437; RV32I-NEXT: sw a1, 0(a0)2438; RV32I-NEXT: sw a5, 4(a0)2439; RV32I-NEXT: sw a2, 8(a0)2440; RV32I-NEXT: sw a3, 12(a0)2441; RV32I-NEXT: ret2442;2443; RV64I-LABEL: abd_subnsw_i128:2444; RV64I: # %bb.0:2445; RV64I-NEXT: sltu a4, a0, a22446; RV64I-NEXT: sub a1, a1, a32447; RV64I-NEXT: sub a0, a0, a22448; RV64I-NEXT: sub a1, a1, a42449; RV64I-NEXT: srai a2, a1, 632450; RV64I-NEXT: xor a0, a0, a22451; RV64I-NEXT: xor a1, a1, a22452; RV64I-NEXT: sltu a3, a2, a02453; RV64I-NEXT: sub a1, a2, a12454; RV64I-NEXT: sub a1, a1, a32455; RV64I-NEXT: sub a0, a2, a02456; RV64I-NEXT: ret2457;2458; RV32ZBB-LABEL: abd_subnsw_i128:2459; RV32ZBB: # %bb.0:2460; RV32ZBB-NEXT: lw a3, 0(a2)2461; RV32ZBB-NEXT: lw a4, 4(a2)2462; RV32ZBB-NEXT: lw a5, 8(a2)2463; RV32ZBB-NEXT: lw a6, 12(a2)2464; RV32ZBB-NEXT: lw t0, 8(a1)2465; RV32ZBB-NEXT: lw t1, 12(a1)2466; RV32ZBB-NEXT: lw a2, 0(a1)2467; RV32ZBB-NEXT: lw a7, 4(a1)2468; RV32ZBB-NEXT: sltu a1, t0, a52469; RV32ZBB-NEXT: sub t1, t1, a62470; RV32ZBB-NEXT: sltu a6, a2, a32471; RV32ZBB-NEXT: sub a1, t1, a12472; RV32ZBB-NEXT: mv t1, a62473; RV32ZBB-NEXT: beq a7, a4, .LBB31_22474; RV32ZBB-NEXT: # %bb.1:2475; RV32ZBB-NEXT: sltu t1, a7, a42476; RV32ZBB-NEXT: .LBB31_2:2477; RV32ZBB-NEXT: sub a5, t0, a52478; RV32ZBB-NEXT: sub a4, a7, a42479; RV32ZBB-NEXT: sub a3, a2, a32480; RV32ZBB-NEXT: sltu a2, a5, t12481; RV32ZBB-NEXT: sub t0, a4, a62482; RV32ZBB-NEXT: sub a4, a5, t12483; RV32ZBB-NEXT: sub a5, a1, a22484; RV32ZBB-NEXT: srai a1, a5, 312485; RV32ZBB-NEXT: xor a2, a4, a12486; RV32ZBB-NEXT: xor a5, a5, a12487; RV32ZBB-NEXT: xor a4, a3, a12488; RV32ZBB-NEXT: sltu a3, a1, a22489; RV32ZBB-NEXT: sub a6, a1, a52490; RV32ZBB-NEXT: sltu a5, a1, a42491; RV32ZBB-NEXT: sub a3, a6, a32492; RV32ZBB-NEXT: xor a7, t0, a12493; RV32ZBB-NEXT: mv a6, a52494; RV32ZBB-NEXT: beqz t0, .LBB31_42495; RV32ZBB-NEXT: # %bb.3:2496; RV32ZBB-NEXT: sltu a6, a1, a72497; RV32ZBB-NEXT: .LBB31_4:2498; RV32ZBB-NEXT: sub a2, a1, a22499; RV32ZBB-NEXT: sub a7, a1, a72500; RV32ZBB-NEXT: sub a1, a1, a42501; RV32ZBB-NEXT: sltu a4, a2, a62502; RV32ZBB-NEXT: sub a2, a2, a62503; RV32ZBB-NEXT: sub a5, a7, a52504; RV32ZBB-NEXT: sub a3, a3, a42505; RV32ZBB-NEXT: sw a1, 0(a0)2506; RV32ZBB-NEXT: sw a5, 4(a0)2507; RV32ZBB-NEXT: sw a2, 8(a0)2508; RV32ZBB-NEXT: sw a3, 12(a0)2509; RV32ZBB-NEXT: ret2510;2511; RV64ZBB-LABEL: abd_subnsw_i128:2512; RV64ZBB: # %bb.0:2513; RV64ZBB-NEXT: sltu a4, a0, a22514; RV64ZBB-NEXT: sub a1, a1, a32515; RV64ZBB-NEXT: sub a0, a0, a22516; RV64ZBB-NEXT: sub a1, a1, a42517; RV64ZBB-NEXT: srai a2, a1, 632518; RV64ZBB-NEXT: xor a0, a0, a22519; RV64ZBB-NEXT: xor a1, a1, a22520; RV64ZBB-NEXT: sltu a3, a2, a02521; RV64ZBB-NEXT: sub a1, a2, a12522; RV64ZBB-NEXT: sub a1, a1, a32523; RV64ZBB-NEXT: sub a0, a2, a02524; RV64ZBB-NEXT: ret2525 %sub = sub nsw i128 %a, %b2526 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)2527 %nabs = sub i128 0, %abs2528 ret i128 %nabs2529}2530 2531define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {2532; RV32I-LABEL: abd_subnsw_i128_undef:2533; RV32I: # %bb.0:2534; RV32I-NEXT: lw a3, 0(a2)2535; RV32I-NEXT: lw a4, 4(a2)2536; RV32I-NEXT: lw a5, 8(a2)2537; RV32I-NEXT: lw a6, 12(a2)2538; RV32I-NEXT: lw t0, 8(a1)2539; RV32I-NEXT: lw t1, 12(a1)2540; RV32I-NEXT: lw a2, 0(a1)2541; RV32I-NEXT: lw a7, 4(a1)2542; RV32I-NEXT: sltu a1, t0, a52543; RV32I-NEXT: sub t1, t1, a62544; RV32I-NEXT: sltu a6, a2, a32545; RV32I-NEXT: sub a1, t1, a12546; RV32I-NEXT: mv t1, a62547; RV32I-NEXT: beq a7, a4, .LBB32_22548; RV32I-NEXT: # %bb.1:2549; RV32I-NEXT: sltu t1, a7, a42550; RV32I-NEXT: .LBB32_2:2551; RV32I-NEXT: sub a5, t0, a52552; RV32I-NEXT: sub a4, a7, a42553; RV32I-NEXT: sub a3, a2, a32554; RV32I-NEXT: sltu a2, a5, t12555; RV32I-NEXT: sub t0, a4, a62556; RV32I-NEXT: sub a4, a5, t12557; RV32I-NEXT: sub a5, a1, a22558; RV32I-NEXT: srai a1, a5, 312559; RV32I-NEXT: xor a2, a4, a12560; RV32I-NEXT: xor a5, a5, a12561; RV32I-NEXT: xor a4, a3, a12562; RV32I-NEXT: sltu a3, a1, a22563; RV32I-NEXT: sub a6, a1, a52564; RV32I-NEXT: sltu a5, a1, a42565; RV32I-NEXT: sub a3, a6, a32566; RV32I-NEXT: xor a7, t0, a12567; RV32I-NEXT: mv a6, a52568; RV32I-NEXT: beqz t0, .LBB32_42569; RV32I-NEXT: # %bb.3:2570; RV32I-NEXT: sltu a6, a1, a72571; RV32I-NEXT: .LBB32_4:2572; RV32I-NEXT: sub a2, a1, a22573; RV32I-NEXT: sub a7, a1, a72574; RV32I-NEXT: sub a1, a1, a42575; RV32I-NEXT: sltu a4, a2, a62576; RV32I-NEXT: sub a2, a2, a62577; RV32I-NEXT: sub a5, a7, a52578; RV32I-NEXT: sub a3, a3, a42579; RV32I-NEXT: sw a1, 0(a0)2580; RV32I-NEXT: sw a5, 4(a0)2581; RV32I-NEXT: sw a2, 8(a0)2582; RV32I-NEXT: sw a3, 12(a0)2583; RV32I-NEXT: ret2584;2585; RV64I-LABEL: abd_subnsw_i128_undef:2586; RV64I: # %bb.0:2587; RV64I-NEXT: sltu a4, a0, a22588; RV64I-NEXT: sub a1, a1, a32589; RV64I-NEXT: sub a0, a0, a22590; RV64I-NEXT: sub a1, a1, a42591; RV64I-NEXT: srai a2, a1, 632592; RV64I-NEXT: xor a0, a0, a22593; RV64I-NEXT: xor a1, a1, a22594; RV64I-NEXT: sltu a3, a2, a02595; RV64I-NEXT: sub a1, a2, a12596; RV64I-NEXT: sub a1, a1, a32597; RV64I-NEXT: sub a0, a2, a02598; RV64I-NEXT: ret2599;2600; RV32ZBB-LABEL: abd_subnsw_i128_undef:2601; RV32ZBB: # %bb.0:2602; RV32ZBB-NEXT: lw a3, 0(a2)2603; RV32ZBB-NEXT: lw a4, 4(a2)2604; RV32ZBB-NEXT: lw a5, 8(a2)2605; RV32ZBB-NEXT: lw a6, 12(a2)2606; RV32ZBB-NEXT: lw t0, 8(a1)2607; RV32ZBB-NEXT: lw t1, 12(a1)2608; RV32ZBB-NEXT: lw a2, 0(a1)2609; RV32ZBB-NEXT: lw a7, 4(a1)2610; RV32ZBB-NEXT: sltu a1, t0, a52611; RV32ZBB-NEXT: sub t1, t1, a62612; RV32ZBB-NEXT: sltu a6, a2, a32613; RV32ZBB-NEXT: sub a1, t1, a12614; RV32ZBB-NEXT: mv t1, a62615; RV32ZBB-NEXT: beq a7, a4, .LBB32_22616; RV32ZBB-NEXT: # %bb.1:2617; RV32ZBB-NEXT: sltu t1, a7, a42618; RV32ZBB-NEXT: .LBB32_2:2619; RV32ZBB-NEXT: sub a5, t0, a52620; RV32ZBB-NEXT: sub a4, a7, a42621; RV32ZBB-NEXT: sub a3, a2, a32622; RV32ZBB-NEXT: sltu a2, a5, t12623; RV32ZBB-NEXT: sub t0, a4, a62624; RV32ZBB-NEXT: sub a4, a5, t12625; RV32ZBB-NEXT: sub a5, a1, a22626; RV32ZBB-NEXT: srai a1, a5, 312627; RV32ZBB-NEXT: xor a2, a4, a12628; RV32ZBB-NEXT: xor a5, a5, a12629; RV32ZBB-NEXT: xor a4, a3, a12630; RV32ZBB-NEXT: sltu a3, a1, a22631; RV32ZBB-NEXT: sub a6, a1, a52632; RV32ZBB-NEXT: sltu a5, a1, a42633; RV32ZBB-NEXT: sub a3, a6, a32634; RV32ZBB-NEXT: xor a7, t0, a12635; RV32ZBB-NEXT: mv a6, a52636; RV32ZBB-NEXT: beqz t0, .LBB32_42637; RV32ZBB-NEXT: # %bb.3:2638; RV32ZBB-NEXT: sltu a6, a1, a72639; RV32ZBB-NEXT: .LBB32_4:2640; RV32ZBB-NEXT: sub a2, a1, a22641; RV32ZBB-NEXT: sub a7, a1, a72642; RV32ZBB-NEXT: sub a1, a1, a42643; RV32ZBB-NEXT: sltu a4, a2, a62644; RV32ZBB-NEXT: sub a2, a2, a62645; RV32ZBB-NEXT: sub a5, a7, a52646; RV32ZBB-NEXT: sub a3, a3, a42647; RV32ZBB-NEXT: sw a1, 0(a0)2648; RV32ZBB-NEXT: sw a5, 4(a0)2649; RV32ZBB-NEXT: sw a2, 8(a0)2650; RV32ZBB-NEXT: sw a3, 12(a0)2651; RV32ZBB-NEXT: ret2652;2653; RV64ZBB-LABEL: abd_subnsw_i128_undef:2654; RV64ZBB: # %bb.0:2655; RV64ZBB-NEXT: sltu a4, a0, a22656; RV64ZBB-NEXT: sub a1, a1, a32657; RV64ZBB-NEXT: sub a0, a0, a22658; RV64ZBB-NEXT: sub a1, a1, a42659; RV64ZBB-NEXT: srai a2, a1, 632660; RV64ZBB-NEXT: xor a0, a0, a22661; RV64ZBB-NEXT: xor a1, a1, a22662; RV64ZBB-NEXT: sltu a3, a2, a02663; RV64ZBB-NEXT: sub a1, a2, a12664; RV64ZBB-NEXT: sub a1, a1, a32665; RV64ZBB-NEXT: sub a0, a2, a02666; RV64ZBB-NEXT: ret2667 %sub = sub nsw i128 %a, %b2668 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)2669 %nabs = sub i128 0, %abs2670 ret i128 %nabs2671}2672 2673