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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=ZBB,RV32ZBB5; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=ZBB,RV64ZBB6 7;8; trunc(abs(sub(sext(a),sext(b)))) -> abds(a,b)9;10 11define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {12; RV32I-LABEL: abd_ext_i8:13; RV32I: # %bb.0:14; RV32I-NEXT: slli a1, a1, 2415; RV32I-NEXT: slli a0, a0, 2416; RV32I-NEXT: srai a1, a1, 2417; RV32I-NEXT: srai a0, a0, 2418; RV32I-NEXT: sub a0, a0, a119; RV32I-NEXT: srai a1, a0, 3120; RV32I-NEXT: xor a0, a0, a121; RV32I-NEXT: sub a0, a0, a122; RV32I-NEXT: ret23;24; RV64I-LABEL: abd_ext_i8:25; RV64I: # %bb.0:26; RV64I-NEXT: slli a1, a1, 5627; RV64I-NEXT: slli a0, a0, 5628; RV64I-NEXT: srai a1, a1, 5629; RV64I-NEXT: srai a0, a0, 5630; RV64I-NEXT: sub a0, a0, a131; RV64I-NEXT: srai a1, a0, 6332; RV64I-NEXT: xor a0, a0, a133; RV64I-NEXT: sub a0, a0, a134; RV64I-NEXT: ret35;36; ZBB-LABEL: abd_ext_i8:37; ZBB: # %bb.0:38; ZBB-NEXT: sext.b a1, a139; ZBB-NEXT: sext.b a0, a040; ZBB-NEXT: min a2, a0, a141; ZBB-NEXT: max a0, a0, a142; ZBB-NEXT: sub a0, a0, a243; ZBB-NEXT: ret44 %aext = sext i8 %a to i6445 %bext = sext i8 %b to i6446 %sub = sub i64 %aext, %bext47 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)48 %trunc = trunc i64 %abs to i849 ret i8 %trunc50}51 52define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {53; RV32I-LABEL: abd_ext_i8_i16:54; RV32I: # %bb.0:55; RV32I-NEXT: slli a1, a1, 1656; RV32I-NEXT: slli a0, a0, 2457; RV32I-NEXT: srai a1, a1, 1658; RV32I-NEXT: srai a0, a0, 2459; RV32I-NEXT: sub a0, a0, a160; RV32I-NEXT: srai a1, a0, 3161; RV32I-NEXT: xor a0, a0, a162; RV32I-NEXT: sub a0, a0, a163; RV32I-NEXT: ret64;65; RV64I-LABEL: abd_ext_i8_i16:66; RV64I: # %bb.0:67; RV64I-NEXT: slli a1, a1, 4868; RV64I-NEXT: slli a0, a0, 5669; RV64I-NEXT: srai a1, a1, 4870; RV64I-NEXT: srai a0, a0, 5671; RV64I-NEXT: sub a0, a0, a172; RV64I-NEXT: srai a1, a0, 6373; RV64I-NEXT: xor a0, a0, a174; RV64I-NEXT: sub a0, a0, a175; RV64I-NEXT: ret76;77; ZBB-LABEL: abd_ext_i8_i16:78; ZBB: # %bb.0:79; ZBB-NEXT: sext.h a1, a180; ZBB-NEXT: sext.b a0, a081; ZBB-NEXT: min a2, a0, a182; ZBB-NEXT: max a0, a0, a183; ZBB-NEXT: sub a0, a0, a284; ZBB-NEXT: ret85 %aext = sext i8 %a to i6486 %bext = sext i16 %b to i6487 %sub = sub i64 %aext, %bext88 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)89 %trunc = trunc i64 %abs to i890 ret i8 %trunc91}92 93define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {94; RV32I-LABEL: abd_ext_i8_undef:95; RV32I: # %bb.0:96; RV32I-NEXT: slli a1, a1, 2497; RV32I-NEXT: slli a0, a0, 2498; RV32I-NEXT: srai a1, a1, 2499; RV32I-NEXT: srai a0, a0, 24100; RV32I-NEXT: sub a0, a0, a1101; RV32I-NEXT: srai a1, a0, 31102; RV32I-NEXT: xor a0, a0, a1103; RV32I-NEXT: sub a0, a0, a1104; RV32I-NEXT: ret105;106; RV64I-LABEL: abd_ext_i8_undef:107; RV64I: # %bb.0:108; RV64I-NEXT: slli a1, a1, 56109; RV64I-NEXT: slli a0, a0, 56110; RV64I-NEXT: srai a1, a1, 56111; RV64I-NEXT: srai a0, a0, 56112; RV64I-NEXT: sub a0, a0, a1113; RV64I-NEXT: srai a1, a0, 63114; RV64I-NEXT: xor a0, a0, a1115; RV64I-NEXT: sub a0, a0, a1116; RV64I-NEXT: ret117;118; ZBB-LABEL: abd_ext_i8_undef:119; ZBB: # %bb.0:120; ZBB-NEXT: sext.b a1, a1121; ZBB-NEXT: sext.b a0, a0122; ZBB-NEXT: min a2, a0, a1123; ZBB-NEXT: max a0, a0, a1124; ZBB-NEXT: sub a0, a0, a2125; ZBB-NEXT: ret126 %aext = sext i8 %a to i64127 %bext = sext i8 %b to i64128 %sub = sub i64 %aext, %bext129 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)130 %trunc = trunc i64 %abs to i8131 ret i8 %trunc132}133 134define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {135; RV32I-LABEL: abd_ext_i16:136; RV32I: # %bb.0:137; RV32I-NEXT: slli a1, a1, 16138; RV32I-NEXT: slli a0, a0, 16139; RV32I-NEXT: srai a1, a1, 16140; RV32I-NEXT: srai a0, a0, 16141; RV32I-NEXT: sub a0, a0, a1142; RV32I-NEXT: srai a1, a0, 31143; RV32I-NEXT: xor a0, a0, a1144; RV32I-NEXT: sub a0, a0, a1145; RV32I-NEXT: ret146;147; RV64I-LABEL: abd_ext_i16:148; RV64I: # %bb.0:149; RV64I-NEXT: slli a1, a1, 48150; RV64I-NEXT: slli a0, a0, 48151; RV64I-NEXT: srai a1, a1, 48152; RV64I-NEXT: srai a0, a0, 48153; RV64I-NEXT: sub a0, a0, a1154; RV64I-NEXT: srai a1, a0, 63155; RV64I-NEXT: xor a0, a0, a1156; RV64I-NEXT: sub a0, a0, a1157; RV64I-NEXT: ret158;159; ZBB-LABEL: abd_ext_i16:160; ZBB: # %bb.0:161; ZBB-NEXT: sext.h a1, a1162; ZBB-NEXT: sext.h a0, a0163; ZBB-NEXT: min a2, a0, a1164; ZBB-NEXT: max a0, a0, a1165; ZBB-NEXT: sub a0, a0, a2166; ZBB-NEXT: ret167 %aext = sext i16 %a to i64168 %bext = sext i16 %b to i64169 %sub = sub i64 %aext, %bext170 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)171 %trunc = trunc i64 %abs to i16172 ret i16 %trunc173}174 175define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {176; RV32I-LABEL: abd_ext_i16_i32:177; RV32I: # %bb.0:178; RV32I-NEXT: slli a0, a0, 16179; RV32I-NEXT: srai a0, a0, 16180; RV32I-NEXT: blt a1, a0, .LBB4_2181; RV32I-NEXT: # %bb.1:182; RV32I-NEXT: sub a0, a1, a0183; RV32I-NEXT: ret184; RV32I-NEXT: .LBB4_2:185; RV32I-NEXT: sub a0, a0, a1186; RV32I-NEXT: ret187;188; RV64I-LABEL: abd_ext_i16_i32:189; RV64I: # %bb.0:190; RV64I-NEXT: sext.w a1, a1191; RV64I-NEXT: slli a0, a0, 48192; RV64I-NEXT: srai a0, a0, 48193; RV64I-NEXT: sub a0, a0, a1194; RV64I-NEXT: srai a1, a0, 63195; RV64I-NEXT: xor a0, a0, a1196; RV64I-NEXT: sub a0, a0, a1197; RV64I-NEXT: ret198;199; RV32ZBB-LABEL: abd_ext_i16_i32:200; RV32ZBB: # %bb.0:201; RV32ZBB-NEXT: sext.h a0, a0202; RV32ZBB-NEXT: min a2, a0, a1203; RV32ZBB-NEXT: max a0, a0, a1204; RV32ZBB-NEXT: sub a0, a0, a2205; RV32ZBB-NEXT: ret206;207; RV64ZBB-LABEL: abd_ext_i16_i32:208; RV64ZBB: # %bb.0:209; RV64ZBB-NEXT: sext.w a1, a1210; RV64ZBB-NEXT: sext.h a0, a0211; RV64ZBB-NEXT: min a2, a0, a1212; RV64ZBB-NEXT: max a0, a0, a1213; RV64ZBB-NEXT: sub a0, a0, a2214; RV64ZBB-NEXT: ret215 %aext = sext i16 %a to i64216 %bext = sext i32 %b to i64217 %sub = sub i64 %aext, %bext218 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)219 %trunc = trunc i64 %abs to i16220 ret i16 %trunc221}222 223define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {224; RV32I-LABEL: abd_ext_i16_undef:225; RV32I: # %bb.0:226; RV32I-NEXT: slli a1, a1, 16227; RV32I-NEXT: slli a0, a0, 16228; RV32I-NEXT: srai a1, a1, 16229; RV32I-NEXT: srai a0, a0, 16230; RV32I-NEXT: sub a0, a0, a1231; RV32I-NEXT: srai a1, a0, 31232; RV32I-NEXT: xor a0, a0, a1233; RV32I-NEXT: sub a0, a0, a1234; RV32I-NEXT: ret235;236; RV64I-LABEL: abd_ext_i16_undef:237; RV64I: # %bb.0:238; RV64I-NEXT: slli a1, a1, 48239; RV64I-NEXT: slli a0, a0, 48240; RV64I-NEXT: srai a1, a1, 48241; RV64I-NEXT: srai a0, a0, 48242; RV64I-NEXT: sub a0, a0, a1243; RV64I-NEXT: srai a1, a0, 63244; RV64I-NEXT: xor a0, a0, a1245; RV64I-NEXT: sub a0, a0, a1246; RV64I-NEXT: ret247;248; ZBB-LABEL: abd_ext_i16_undef:249; ZBB: # %bb.0:250; ZBB-NEXT: sext.h a1, a1251; ZBB-NEXT: sext.h a0, a0252; ZBB-NEXT: min a2, a0, a1253; ZBB-NEXT: max a0, a0, a1254; ZBB-NEXT: sub a0, a0, a2255; ZBB-NEXT: ret256 %aext = sext i16 %a to i64257 %bext = sext i16 %b to i64258 %sub = sub i64 %aext, %bext259 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)260 %trunc = trunc i64 %abs to i16261 ret i16 %trunc262}263 264define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {265; RV32I-LABEL: abd_ext_i32:266; RV32I: # %bb.0:267; RV32I-NEXT: blt a1, a0, .LBB6_2268; RV32I-NEXT: # %bb.1:269; RV32I-NEXT: sub a0, a1, a0270; RV32I-NEXT: ret271; RV32I-NEXT: .LBB6_2:272; RV32I-NEXT: sub a0, a0, a1273; RV32I-NEXT: ret274;275; RV64I-LABEL: abd_ext_i32:276; RV64I: # %bb.0:277; RV64I-NEXT: sext.w a1, a1278; RV64I-NEXT: sext.w a0, a0279; RV64I-NEXT: sub a0, a0, a1280; RV64I-NEXT: srai a1, a0, 63281; RV64I-NEXT: xor a0, a0, a1282; RV64I-NEXT: sub a0, a0, a1283; RV64I-NEXT: ret284;285; RV32ZBB-LABEL: abd_ext_i32:286; RV32ZBB: # %bb.0:287; RV32ZBB-NEXT: min a2, a0, a1288; RV32ZBB-NEXT: max a0, a0, a1289; RV32ZBB-NEXT: sub a0, a0, a2290; RV32ZBB-NEXT: ret291;292; RV64ZBB-LABEL: abd_ext_i32:293; RV64ZBB: # %bb.0:294; RV64ZBB-NEXT: sext.w a1, a1295; RV64ZBB-NEXT: sext.w a0, a0296; RV64ZBB-NEXT: min a2, a0, a1297; RV64ZBB-NEXT: max a0, a0, a1298; RV64ZBB-NEXT: sub a0, a0, a2299; RV64ZBB-NEXT: ret300 %aext = sext i32 %a to i64301 %bext = sext i32 %b to i64302 %sub = sub i64 %aext, %bext303 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)304 %trunc = trunc i64 %abs to i32305 ret i32 %trunc306}307 308define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {309; RV32I-LABEL: abd_ext_i32_i16:310; RV32I: # %bb.0:311; RV32I-NEXT: slli a1, a1, 16312; RV32I-NEXT: srai a1, a1, 16313; RV32I-NEXT: blt a1, a0, .LBB7_2314; RV32I-NEXT: # %bb.1:315; RV32I-NEXT: sub a0, a1, a0316; RV32I-NEXT: ret317; RV32I-NEXT: .LBB7_2:318; RV32I-NEXT: sub a0, a0, a1319; RV32I-NEXT: ret320;321; RV64I-LABEL: abd_ext_i32_i16:322; RV64I: # %bb.0:323; RV64I-NEXT: sext.w a0, a0324; RV64I-NEXT: slli a1, a1, 48325; RV64I-NEXT: srai a1, a1, 48326; RV64I-NEXT: sub a0, a0, a1327; RV64I-NEXT: srai a1, a0, 63328; RV64I-NEXT: xor a0, a0, a1329; RV64I-NEXT: sub a0, a0, a1330; RV64I-NEXT: ret331;332; RV32ZBB-LABEL: abd_ext_i32_i16:333; RV32ZBB: # %bb.0:334; RV32ZBB-NEXT: sext.h a1, a1335; RV32ZBB-NEXT: min a2, a0, a1336; RV32ZBB-NEXT: max a0, a0, a1337; RV32ZBB-NEXT: sub a0, a0, a2338; RV32ZBB-NEXT: ret339;340; RV64ZBB-LABEL: abd_ext_i32_i16:341; RV64ZBB: # %bb.0:342; RV64ZBB-NEXT: sext.w a0, a0343; RV64ZBB-NEXT: sext.h a1, a1344; RV64ZBB-NEXT: min a2, a0, a1345; RV64ZBB-NEXT: max a0, a0, a1346; RV64ZBB-NEXT: sub a0, a0, a2347; RV64ZBB-NEXT: ret348 %aext = sext i32 %a to i64349 %bext = sext i16 %b to i64350 %sub = sub i64 %aext, %bext351 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)352 %trunc = trunc i64 %abs to i32353 ret i32 %trunc354}355 356define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {357; RV32I-LABEL: abd_ext_i32_undef:358; RV32I: # %bb.0:359; RV32I-NEXT: blt a1, a0, .LBB8_2360; RV32I-NEXT: # %bb.1:361; RV32I-NEXT: sub a0, a1, a0362; RV32I-NEXT: ret363; RV32I-NEXT: .LBB8_2:364; RV32I-NEXT: sub a0, a0, a1365; RV32I-NEXT: ret366;367; RV64I-LABEL: abd_ext_i32_undef:368; RV64I: # %bb.0:369; RV64I-NEXT: sext.w a1, a1370; RV64I-NEXT: sext.w a0, a0371; RV64I-NEXT: sub a0, a0, a1372; RV64I-NEXT: srai a1, a0, 63373; RV64I-NEXT: xor a0, a0, a1374; RV64I-NEXT: sub a0, a0, a1375; RV64I-NEXT: ret376;377; RV32ZBB-LABEL: abd_ext_i32_undef:378; RV32ZBB: # %bb.0:379; RV32ZBB-NEXT: min a2, a0, a1380; RV32ZBB-NEXT: max a0, a0, a1381; RV32ZBB-NEXT: sub a0, a0, a2382; RV32ZBB-NEXT: ret383;384; RV64ZBB-LABEL: abd_ext_i32_undef:385; RV64ZBB: # %bb.0:386; RV64ZBB-NEXT: sext.w a1, a1387; RV64ZBB-NEXT: sext.w a0, a0388; RV64ZBB-NEXT: min a2, a0, a1389; RV64ZBB-NEXT: max a0, a0, a1390; RV64ZBB-NEXT: sub a0, a0, a2391; RV64ZBB-NEXT: ret392 %aext = sext i32 %a to i64393 %bext = sext i32 %b to i64394 %sub = sub i64 %aext, %bext395 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)396 %trunc = trunc i64 %abs to i32397 ret i32 %trunc398}399 400define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {401; RV32I-LABEL: abd_ext_i64:402; RV32I: # %bb.0:403; RV32I-NEXT: sltu a4, a2, a0404; RV32I-NEXT: mv a5, a4405; RV32I-NEXT: beq a1, a3, .LBB9_2406; RV32I-NEXT: # %bb.1:407; RV32I-NEXT: slt a5, a3, a1408; RV32I-NEXT: .LBB9_2:409; RV32I-NEXT: bnez a5, .LBB9_4410; RV32I-NEXT: # %bb.3:411; RV32I-NEXT: sub a1, a3, a1412; RV32I-NEXT: sub a1, a1, a4413; RV32I-NEXT: sub a0, a2, a0414; RV32I-NEXT: ret415; RV32I-NEXT: .LBB9_4:416; RV32I-NEXT: sltu a4, a0, a2417; RV32I-NEXT: sub a1, a1, a3418; RV32I-NEXT: sub a1, a1, a4419; RV32I-NEXT: sub a0, a0, a2420; RV32I-NEXT: ret421;422; RV64I-LABEL: abd_ext_i64:423; RV64I: # %bb.0:424; RV64I-NEXT: blt a1, a0, .LBB9_2425; RV64I-NEXT: # %bb.1:426; RV64I-NEXT: sub a0, a1, a0427; RV64I-NEXT: ret428; RV64I-NEXT: .LBB9_2:429; RV64I-NEXT: sub a0, a0, a1430; RV64I-NEXT: ret431;432; RV32ZBB-LABEL: abd_ext_i64:433; RV32ZBB: # %bb.0:434; RV32ZBB-NEXT: sltu a4, a2, a0435; RV32ZBB-NEXT: mv a5, a4436; RV32ZBB-NEXT: beq a1, a3, .LBB9_2437; RV32ZBB-NEXT: # %bb.1:438; RV32ZBB-NEXT: slt a5, a3, a1439; RV32ZBB-NEXT: .LBB9_2:440; RV32ZBB-NEXT: bnez a5, .LBB9_4441; RV32ZBB-NEXT: # %bb.3:442; RV32ZBB-NEXT: sub a1, a3, a1443; RV32ZBB-NEXT: sub a1, a1, a4444; RV32ZBB-NEXT: sub a0, a2, a0445; RV32ZBB-NEXT: ret446; RV32ZBB-NEXT: .LBB9_4:447; RV32ZBB-NEXT: sltu a4, a0, a2448; RV32ZBB-NEXT: sub a1, a1, a3449; RV32ZBB-NEXT: sub a1, a1, a4450; RV32ZBB-NEXT: sub a0, a0, a2451; RV32ZBB-NEXT: ret452;453; RV64ZBB-LABEL: abd_ext_i64:454; RV64ZBB: # %bb.0:455; RV64ZBB-NEXT: min a2, a0, a1456; RV64ZBB-NEXT: max a0, a0, a1457; RV64ZBB-NEXT: sub a0, a0, a2458; RV64ZBB-NEXT: ret459 %aext = sext i64 %a to i128460 %bext = sext i64 %b to i128461 %sub = sub i128 %aext, %bext462 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)463 %trunc = trunc i128 %abs to i64464 ret i64 %trunc465}466 467define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {468; RV32I-LABEL: abd_ext_i64_undef:469; RV32I: # %bb.0:470; RV32I-NEXT: sltu a4, a2, a0471; RV32I-NEXT: mv a5, a4472; RV32I-NEXT: beq a1, a3, .LBB10_2473; RV32I-NEXT: # %bb.1:474; RV32I-NEXT: slt a5, a3, a1475; RV32I-NEXT: .LBB10_2:476; RV32I-NEXT: bnez a5, .LBB10_4477; RV32I-NEXT: # %bb.3:478; RV32I-NEXT: sub a1, a3, a1479; RV32I-NEXT: sub a1, a1, a4480; RV32I-NEXT: sub a0, a2, a0481; RV32I-NEXT: ret482; RV32I-NEXT: .LBB10_4:483; RV32I-NEXT: sltu a4, a0, a2484; RV32I-NEXT: sub a1, a1, a3485; RV32I-NEXT: sub a1, a1, a4486; RV32I-NEXT: sub a0, a0, a2487; RV32I-NEXT: ret488;489; RV64I-LABEL: abd_ext_i64_undef:490; RV64I: # %bb.0:491; RV64I-NEXT: blt a1, a0, .LBB10_2492; RV64I-NEXT: # %bb.1:493; RV64I-NEXT: sub a0, a1, a0494; RV64I-NEXT: ret495; RV64I-NEXT: .LBB10_2:496; RV64I-NEXT: sub a0, a0, a1497; RV64I-NEXT: ret498;499; RV32ZBB-LABEL: abd_ext_i64_undef:500; RV32ZBB: # %bb.0:501; RV32ZBB-NEXT: sltu a4, a2, a0502; RV32ZBB-NEXT: mv a5, a4503; RV32ZBB-NEXT: beq a1, a3, .LBB10_2504; RV32ZBB-NEXT: # %bb.1:505; RV32ZBB-NEXT: slt a5, a3, a1506; RV32ZBB-NEXT: .LBB10_2:507; RV32ZBB-NEXT: bnez a5, .LBB10_4508; RV32ZBB-NEXT: # %bb.3:509; RV32ZBB-NEXT: sub a1, a3, a1510; RV32ZBB-NEXT: sub a1, a1, a4511; RV32ZBB-NEXT: sub a0, a2, a0512; RV32ZBB-NEXT: ret513; RV32ZBB-NEXT: .LBB10_4:514; RV32ZBB-NEXT: sltu a4, a0, a2515; RV32ZBB-NEXT: sub a1, a1, a3516; RV32ZBB-NEXT: sub a1, a1, a4517; RV32ZBB-NEXT: sub a0, a0, a2518; RV32ZBB-NEXT: ret519;520; RV64ZBB-LABEL: abd_ext_i64_undef:521; RV64ZBB: # %bb.0:522; RV64ZBB-NEXT: min a2, a0, a1523; RV64ZBB-NEXT: max a0, a0, a1524; RV64ZBB-NEXT: sub a0, a0, a2525; RV64ZBB-NEXT: ret526 %aext = sext i64 %a to i128527 %bext = sext i64 %b to i128528 %sub = sub i128 %aext, %bext529 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)530 %trunc = trunc i128 %abs to i64531 ret i64 %trunc532}533 534define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {535; RV32I-LABEL: abd_ext_i128:536; RV32I: # %bb.0:537; RV32I-NEXT: lw a3, 0(a1)538; RV32I-NEXT: lw a4, 4(a1)539; RV32I-NEXT: lw a5, 8(a1)540; RV32I-NEXT: lw a7, 12(a1)541; RV32I-NEXT: lw a1, 0(a2)542; RV32I-NEXT: lw a6, 8(a2)543; RV32I-NEXT: lw t1, 12(a2)544; RV32I-NEXT: lw a2, 4(a2)545; RV32I-NEXT: sltu t0, a6, a5546; RV32I-NEXT: mv t4, t0547; RV32I-NEXT: beq a7, t1, .LBB11_2548; RV32I-NEXT: # %bb.1:549; RV32I-NEXT: slt t4, t1, a7550; RV32I-NEXT: .LBB11_2:551; RV32I-NEXT: sltu t2, a1, a3552; RV32I-NEXT: sltu t5, a2, a4553; RV32I-NEXT: mv t3, t2554; RV32I-NEXT: beq a4, a2, .LBB11_4555; RV32I-NEXT: # %bb.3:556; RV32I-NEXT: mv t3, t5557; RV32I-NEXT: .LBB11_4:558; RV32I-NEXT: addi sp, sp, -16559; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill560; RV32I-NEXT: xor t6, a7, t1561; RV32I-NEXT: xor s0, a5, a6562; RV32I-NEXT: or t6, s0, t6563; RV32I-NEXT: beqz t6, .LBB11_6564; RV32I-NEXT: # %bb.5:565; RV32I-NEXT: mv t3, t4566; RV32I-NEXT: .LBB11_6:567; RV32I-NEXT: mv t4, t2568; RV32I-NEXT: beq a2, a4, .LBB11_8569; RV32I-NEXT: # %bb.7:570; RV32I-NEXT: mv t4, t5571; RV32I-NEXT: .LBB11_8:572; RV32I-NEXT: sltu t5, a3, a1573; RV32I-NEXT: mv t6, t5574; RV32I-NEXT: beq a4, a2, .LBB11_10575; RV32I-NEXT: # %bb.9:576; RV32I-NEXT: sltu t6, a4, a2577; RV32I-NEXT: .LBB11_10:578; RV32I-NEXT: bnez t3, .LBB11_12579; RV32I-NEXT: # %bb.11:580; RV32I-NEXT: sub a7, t1, a7581; RV32I-NEXT: sub a5, a6, a5582; RV32I-NEXT: sub a1, a1, a3583; RV32I-NEXT: sub a2, a2, a4584; RV32I-NEXT: sub a4, a7, t0585; RV32I-NEXT: sltu a6, a5, t4586; RV32I-NEXT: sub a3, a2, t2587; RV32I-NEXT: sub a2, a4, a6588; RV32I-NEXT: sub a4, a5, t4589; RV32I-NEXT: j .LBB11_13590; RV32I-NEXT: .LBB11_12:591; RV32I-NEXT: sltu t0, a5, a6592; RV32I-NEXT: sub a7, a7, t1593; RV32I-NEXT: sub a5, a5, a6594; RV32I-NEXT: sub a1, a3, a1595; RV32I-NEXT: sub a4, a4, a2596; RV32I-NEXT: sub a2, a7, t0597; RV32I-NEXT: sltu a6, a5, t6598; RV32I-NEXT: sub a3, a4, t5599; RV32I-NEXT: sub a2, a2, a6600; RV32I-NEXT: sub a4, a5, t6601; RV32I-NEXT: .LBB11_13:602; RV32I-NEXT: sw a1, 0(a0)603; RV32I-NEXT: sw a3, 4(a0)604; RV32I-NEXT: sw a4, 8(a0)605; RV32I-NEXT: sw a2, 12(a0)606; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload607; RV32I-NEXT: addi sp, sp, 16608; RV32I-NEXT: ret609;610; RV64I-LABEL: abd_ext_i128:611; RV64I: # %bb.0:612; RV64I-NEXT: sltu a4, a2, a0613; RV64I-NEXT: mv a5, a4614; RV64I-NEXT: beq a1, a3, .LBB11_2615; RV64I-NEXT: # %bb.1:616; RV64I-NEXT: slt a5, a3, a1617; RV64I-NEXT: .LBB11_2:618; RV64I-NEXT: bnez a5, .LBB11_4619; RV64I-NEXT: # %bb.3:620; RV64I-NEXT: sub a1, a3, a1621; RV64I-NEXT: sub a1, a1, a4622; RV64I-NEXT: sub a0, a2, a0623; RV64I-NEXT: ret624; RV64I-NEXT: .LBB11_4:625; RV64I-NEXT: sltu a4, a0, a2626; RV64I-NEXT: sub a1, a1, a3627; RV64I-NEXT: sub a1, a1, a4628; RV64I-NEXT: sub a0, a0, a2629; RV64I-NEXT: ret630;631; RV32ZBB-LABEL: abd_ext_i128:632; RV32ZBB: # %bb.0:633; RV32ZBB-NEXT: lw a3, 0(a1)634; RV32ZBB-NEXT: lw a4, 4(a1)635; RV32ZBB-NEXT: lw a5, 8(a1)636; RV32ZBB-NEXT: lw a7, 12(a1)637; RV32ZBB-NEXT: lw a1, 0(a2)638; RV32ZBB-NEXT: lw a6, 8(a2)639; RV32ZBB-NEXT: lw t1, 12(a2)640; RV32ZBB-NEXT: lw a2, 4(a2)641; RV32ZBB-NEXT: sltu t0, a6, a5642; RV32ZBB-NEXT: mv t4, t0643; RV32ZBB-NEXT: beq a7, t1, .LBB11_2644; RV32ZBB-NEXT: # %bb.1:645; RV32ZBB-NEXT: slt t4, t1, a7646; RV32ZBB-NEXT: .LBB11_2:647; RV32ZBB-NEXT: sltu t2, a1, a3648; RV32ZBB-NEXT: sltu t5, a2, a4649; RV32ZBB-NEXT: mv t3, t2650; RV32ZBB-NEXT: beq a4, a2, .LBB11_4651; RV32ZBB-NEXT: # %bb.3:652; RV32ZBB-NEXT: mv t3, t5653; RV32ZBB-NEXT: .LBB11_4:654; RV32ZBB-NEXT: addi sp, sp, -16655; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill656; RV32ZBB-NEXT: xor t6, a7, t1657; RV32ZBB-NEXT: xor s0, a5, a6658; RV32ZBB-NEXT: or t6, s0, t6659; RV32ZBB-NEXT: beqz t6, .LBB11_6660; RV32ZBB-NEXT: # %bb.5:661; RV32ZBB-NEXT: mv t3, t4662; RV32ZBB-NEXT: .LBB11_6:663; RV32ZBB-NEXT: mv t4, t2664; RV32ZBB-NEXT: beq a2, a4, .LBB11_8665; RV32ZBB-NEXT: # %bb.7:666; RV32ZBB-NEXT: mv t4, t5667; RV32ZBB-NEXT: .LBB11_8:668; RV32ZBB-NEXT: sltu t5, a3, a1669; RV32ZBB-NEXT: mv t6, t5670; RV32ZBB-NEXT: beq a4, a2, .LBB11_10671; RV32ZBB-NEXT: # %bb.9:672; RV32ZBB-NEXT: sltu t6, a4, a2673; RV32ZBB-NEXT: .LBB11_10:674; RV32ZBB-NEXT: bnez t3, .LBB11_12675; RV32ZBB-NEXT: # %bb.11:676; RV32ZBB-NEXT: sub a7, t1, a7677; RV32ZBB-NEXT: sub a5, a6, a5678; RV32ZBB-NEXT: sub a1, a1, a3679; RV32ZBB-NEXT: sub a2, a2, a4680; RV32ZBB-NEXT: sub a4, a7, t0681; RV32ZBB-NEXT: sltu a6, a5, t4682; RV32ZBB-NEXT: sub a3, a2, t2683; RV32ZBB-NEXT: sub a2, a4, a6684; RV32ZBB-NEXT: sub a4, a5, t4685; RV32ZBB-NEXT: j .LBB11_13686; RV32ZBB-NEXT: .LBB11_12:687; RV32ZBB-NEXT: sltu t0, a5, a6688; RV32ZBB-NEXT: sub a7, a7, t1689; RV32ZBB-NEXT: sub a5, a5, a6690; RV32ZBB-NEXT: sub a1, a3, a1691; RV32ZBB-NEXT: sub a4, a4, a2692; RV32ZBB-NEXT: sub a2, a7, t0693; RV32ZBB-NEXT: sltu a6, a5, t6694; RV32ZBB-NEXT: sub a3, a4, t5695; RV32ZBB-NEXT: sub a2, a2, a6696; RV32ZBB-NEXT: sub a4, a5, t6697; RV32ZBB-NEXT: .LBB11_13:698; RV32ZBB-NEXT: sw a1, 0(a0)699; RV32ZBB-NEXT: sw a3, 4(a0)700; RV32ZBB-NEXT: sw a4, 8(a0)701; RV32ZBB-NEXT: sw a2, 12(a0)702; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload703; RV32ZBB-NEXT: addi sp, sp, 16704; RV32ZBB-NEXT: ret705;706; RV64ZBB-LABEL: abd_ext_i128:707; RV64ZBB: # %bb.0:708; RV64ZBB-NEXT: sltu a4, a2, a0709; RV64ZBB-NEXT: mv a5, a4710; RV64ZBB-NEXT: beq a1, a3, .LBB11_2711; RV64ZBB-NEXT: # %bb.1:712; RV64ZBB-NEXT: slt a5, a3, a1713; RV64ZBB-NEXT: .LBB11_2:714; RV64ZBB-NEXT: bnez a5, .LBB11_4715; RV64ZBB-NEXT: # %bb.3:716; RV64ZBB-NEXT: sub a1, a3, a1717; RV64ZBB-NEXT: sub a1, a1, a4718; RV64ZBB-NEXT: sub a0, a2, a0719; RV64ZBB-NEXT: ret720; RV64ZBB-NEXT: .LBB11_4:721; RV64ZBB-NEXT: sltu a4, a0, a2722; RV64ZBB-NEXT: sub a1, a1, a3723; RV64ZBB-NEXT: sub a1, a1, a4724; RV64ZBB-NEXT: sub a0, a0, a2725; RV64ZBB-NEXT: ret726 %aext = sext i128 %a to i256727 %bext = sext i128 %b to i256728 %sub = sub i256 %aext, %bext729 %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)730 %trunc = trunc i256 %abs to i128731 ret i128 %trunc732}733 734define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {735; RV32I-LABEL: abd_ext_i128_undef:736; RV32I: # %bb.0:737; RV32I-NEXT: lw a3, 0(a1)738; RV32I-NEXT: lw a4, 4(a1)739; RV32I-NEXT: lw a5, 8(a1)740; RV32I-NEXT: lw a7, 12(a1)741; RV32I-NEXT: lw a1, 0(a2)742; RV32I-NEXT: lw a6, 8(a2)743; RV32I-NEXT: lw t1, 12(a2)744; RV32I-NEXT: lw a2, 4(a2)745; RV32I-NEXT: sltu t0, a6, a5746; RV32I-NEXT: mv t4, t0747; RV32I-NEXT: beq a7, t1, .LBB12_2748; RV32I-NEXT: # %bb.1:749; RV32I-NEXT: slt t4, t1, a7750; RV32I-NEXT: .LBB12_2:751; RV32I-NEXT: sltu t2, a1, a3752; RV32I-NEXT: sltu t5, a2, a4753; RV32I-NEXT: mv t3, t2754; RV32I-NEXT: beq a4, a2, .LBB12_4755; RV32I-NEXT: # %bb.3:756; RV32I-NEXT: mv t3, t5757; RV32I-NEXT: .LBB12_4:758; RV32I-NEXT: addi sp, sp, -16759; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill760; RV32I-NEXT: xor t6, a7, t1761; RV32I-NEXT: xor s0, a5, a6762; RV32I-NEXT: or t6, s0, t6763; RV32I-NEXT: beqz t6, .LBB12_6764; RV32I-NEXT: # %bb.5:765; RV32I-NEXT: mv t3, t4766; RV32I-NEXT: .LBB12_6:767; RV32I-NEXT: mv t4, t2768; RV32I-NEXT: beq a2, a4, .LBB12_8769; RV32I-NEXT: # %bb.7:770; RV32I-NEXT: mv t4, t5771; RV32I-NEXT: .LBB12_8:772; RV32I-NEXT: sltu t5, a3, a1773; RV32I-NEXT: mv t6, t5774; RV32I-NEXT: beq a4, a2, .LBB12_10775; RV32I-NEXT: # %bb.9:776; RV32I-NEXT: sltu t6, a4, a2777; RV32I-NEXT: .LBB12_10:778; RV32I-NEXT: bnez t3, .LBB12_12779; RV32I-NEXT: # %bb.11:780; RV32I-NEXT: sub a7, t1, a7781; RV32I-NEXT: sub a5, a6, a5782; RV32I-NEXT: sub a1, a1, a3783; RV32I-NEXT: sub a2, a2, a4784; RV32I-NEXT: sub a4, a7, t0785; RV32I-NEXT: sltu a6, a5, t4786; RV32I-NEXT: sub a3, a2, t2787; RV32I-NEXT: sub a2, a4, a6788; RV32I-NEXT: sub a4, a5, t4789; RV32I-NEXT: j .LBB12_13790; RV32I-NEXT: .LBB12_12:791; RV32I-NEXT: sltu t0, a5, a6792; RV32I-NEXT: sub a7, a7, t1793; RV32I-NEXT: sub a5, a5, a6794; RV32I-NEXT: sub a1, a3, a1795; RV32I-NEXT: sub a4, a4, a2796; RV32I-NEXT: sub a2, a7, t0797; RV32I-NEXT: sltu a6, a5, t6798; RV32I-NEXT: sub a3, a4, t5799; RV32I-NEXT: sub a2, a2, a6800; RV32I-NEXT: sub a4, a5, t6801; RV32I-NEXT: .LBB12_13:802; RV32I-NEXT: sw a1, 0(a0)803; RV32I-NEXT: sw a3, 4(a0)804; RV32I-NEXT: sw a4, 8(a0)805; RV32I-NEXT: sw a2, 12(a0)806; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload807; RV32I-NEXT: addi sp, sp, 16808; RV32I-NEXT: ret809;810; RV64I-LABEL: abd_ext_i128_undef:811; RV64I: # %bb.0:812; RV64I-NEXT: sltu a4, a2, a0813; RV64I-NEXT: mv a5, a4814; RV64I-NEXT: beq a1, a3, .LBB12_2815; RV64I-NEXT: # %bb.1:816; RV64I-NEXT: slt a5, a3, a1817; RV64I-NEXT: .LBB12_2:818; RV64I-NEXT: bnez a5, .LBB12_4819; RV64I-NEXT: # %bb.3:820; RV64I-NEXT: sub a1, a3, a1821; RV64I-NEXT: sub a1, a1, a4822; RV64I-NEXT: sub a0, a2, a0823; RV64I-NEXT: ret824; RV64I-NEXT: .LBB12_4:825; RV64I-NEXT: sltu a4, a0, a2826; RV64I-NEXT: sub a1, a1, a3827; RV64I-NEXT: sub a1, a1, a4828; RV64I-NEXT: sub a0, a0, a2829; RV64I-NEXT: ret830;831; RV32ZBB-LABEL: abd_ext_i128_undef:832; RV32ZBB: # %bb.0:833; RV32ZBB-NEXT: lw a3, 0(a1)834; RV32ZBB-NEXT: lw a4, 4(a1)835; RV32ZBB-NEXT: lw a5, 8(a1)836; RV32ZBB-NEXT: lw a7, 12(a1)837; RV32ZBB-NEXT: lw a1, 0(a2)838; RV32ZBB-NEXT: lw a6, 8(a2)839; RV32ZBB-NEXT: lw t1, 12(a2)840; RV32ZBB-NEXT: lw a2, 4(a2)841; RV32ZBB-NEXT: sltu t0, a6, a5842; RV32ZBB-NEXT: mv t4, t0843; RV32ZBB-NEXT: beq a7, t1, .LBB12_2844; RV32ZBB-NEXT: # %bb.1:845; RV32ZBB-NEXT: slt t4, t1, a7846; RV32ZBB-NEXT: .LBB12_2:847; RV32ZBB-NEXT: sltu t2, a1, a3848; RV32ZBB-NEXT: sltu t5, a2, a4849; RV32ZBB-NEXT: mv t3, t2850; RV32ZBB-NEXT: beq a4, a2, .LBB12_4851; RV32ZBB-NEXT: # %bb.3:852; RV32ZBB-NEXT: mv t3, t5853; RV32ZBB-NEXT: .LBB12_4:854; RV32ZBB-NEXT: addi sp, sp, -16855; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill856; RV32ZBB-NEXT: xor t6, a7, t1857; RV32ZBB-NEXT: xor s0, a5, a6858; RV32ZBB-NEXT: or t6, s0, t6859; RV32ZBB-NEXT: beqz t6, .LBB12_6860; RV32ZBB-NEXT: # %bb.5:861; RV32ZBB-NEXT: mv t3, t4862; RV32ZBB-NEXT: .LBB12_6:863; RV32ZBB-NEXT: mv t4, t2864; RV32ZBB-NEXT: beq a2, a4, .LBB12_8865; RV32ZBB-NEXT: # %bb.7:866; RV32ZBB-NEXT: mv t4, t5867; RV32ZBB-NEXT: .LBB12_8:868; RV32ZBB-NEXT: sltu t5, a3, a1869; RV32ZBB-NEXT: mv t6, t5870; RV32ZBB-NEXT: beq a4, a2, .LBB12_10871; RV32ZBB-NEXT: # %bb.9:872; RV32ZBB-NEXT: sltu t6, a4, a2873; RV32ZBB-NEXT: .LBB12_10:874; RV32ZBB-NEXT: bnez t3, .LBB12_12875; RV32ZBB-NEXT: # %bb.11:876; RV32ZBB-NEXT: sub a7, t1, a7877; RV32ZBB-NEXT: sub a5, a6, a5878; RV32ZBB-NEXT: sub a1, a1, a3879; RV32ZBB-NEXT: sub a2, a2, a4880; RV32ZBB-NEXT: sub a4, a7, t0881; RV32ZBB-NEXT: sltu a6, a5, t4882; RV32ZBB-NEXT: sub a3, a2, t2883; RV32ZBB-NEXT: sub a2, a4, a6884; RV32ZBB-NEXT: sub a4, a5, t4885; RV32ZBB-NEXT: j .LBB12_13886; RV32ZBB-NEXT: .LBB12_12:887; RV32ZBB-NEXT: sltu t0, a5, a6888; RV32ZBB-NEXT: sub a7, a7, t1889; RV32ZBB-NEXT: sub a5, a5, a6890; RV32ZBB-NEXT: sub a1, a3, a1891; RV32ZBB-NEXT: sub a4, a4, a2892; RV32ZBB-NEXT: sub a2, a7, t0893; RV32ZBB-NEXT: sltu a6, a5, t6894; RV32ZBB-NEXT: sub a3, a4, t5895; RV32ZBB-NEXT: sub a2, a2, a6896; RV32ZBB-NEXT: sub a4, a5, t6897; RV32ZBB-NEXT: .LBB12_13:898; RV32ZBB-NEXT: sw a1, 0(a0)899; RV32ZBB-NEXT: sw a3, 4(a0)900; RV32ZBB-NEXT: sw a4, 8(a0)901; RV32ZBB-NEXT: sw a2, 12(a0)902; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload903; RV32ZBB-NEXT: addi sp, sp, 16904; RV32ZBB-NEXT: ret905;906; RV64ZBB-LABEL: abd_ext_i128_undef:907; RV64ZBB: # %bb.0:908; RV64ZBB-NEXT: sltu a4, a2, a0909; RV64ZBB-NEXT: mv a5, a4910; RV64ZBB-NEXT: beq a1, a3, .LBB12_2911; RV64ZBB-NEXT: # %bb.1:912; RV64ZBB-NEXT: slt a5, a3, a1913; RV64ZBB-NEXT: .LBB12_2:914; RV64ZBB-NEXT: bnez a5, .LBB12_4915; RV64ZBB-NEXT: # %bb.3:916; RV64ZBB-NEXT: sub a1, a3, a1917; RV64ZBB-NEXT: sub a1, a1, a4918; RV64ZBB-NEXT: sub a0, a2, a0919; RV64ZBB-NEXT: ret920; RV64ZBB-NEXT: .LBB12_4:921; RV64ZBB-NEXT: sltu a4, a0, a2922; RV64ZBB-NEXT: sub a1, a1, a3923; RV64ZBB-NEXT: sub a1, a1, a4924; RV64ZBB-NEXT: sub a0, a0, a2925; RV64ZBB-NEXT: ret926 %aext = sext i128 %a to i256927 %bext = sext i128 %b to i256928 %sub = sub i256 %aext, %bext929 %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)930 %trunc = trunc i256 %abs to i128931 ret i128 %trunc932}933 934;935; sub(smax(a,b),smin(a,b)) -> abds(a,b)936;937 938define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {939; RV32I-LABEL: abd_minmax_i8:940; RV32I: # %bb.0:941; RV32I-NEXT: slli a1, a1, 24942; RV32I-NEXT: slli a0, a0, 24943; RV32I-NEXT: srai a1, a1, 24944; RV32I-NEXT: srai a0, a0, 24945; RV32I-NEXT: sub a0, a0, a1946; RV32I-NEXT: srai a1, a0, 31947; RV32I-NEXT: xor a0, a0, a1948; RV32I-NEXT: sub a0, a0, a1949; RV32I-NEXT: ret950;951; RV64I-LABEL: abd_minmax_i8:952; RV64I: # %bb.0:953; RV64I-NEXT: slli a1, a1, 56954; RV64I-NEXT: slli a0, a0, 56955; RV64I-NEXT: srai a1, a1, 56956; RV64I-NEXT: srai a0, a0, 56957; RV64I-NEXT: sub a0, a0, a1958; RV64I-NEXT: srai a1, a0, 63959; RV64I-NEXT: xor a0, a0, a1960; RV64I-NEXT: sub a0, a0, a1961; RV64I-NEXT: ret962;963; ZBB-LABEL: abd_minmax_i8:964; ZBB: # %bb.0:965; ZBB-NEXT: sext.b a1, a1966; ZBB-NEXT: sext.b a0, a0967; ZBB-NEXT: min a2, a0, a1968; ZBB-NEXT: max a0, a0, a1969; ZBB-NEXT: sub a0, a0, a2970; ZBB-NEXT: ret971 %min = call i8 @llvm.smin.i8(i8 %a, i8 %b)972 %max = call i8 @llvm.smax.i8(i8 %a, i8 %b)973 %sub = sub i8 %max, %min974 ret i8 %sub975}976 977define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {978; RV32I-LABEL: abd_minmax_i16:979; RV32I: # %bb.0:980; RV32I-NEXT: slli a1, a1, 16981; RV32I-NEXT: slli a0, a0, 16982; RV32I-NEXT: srai a1, a1, 16983; RV32I-NEXT: srai a0, a0, 16984; RV32I-NEXT: sub a0, a0, a1985; RV32I-NEXT: srai a1, a0, 31986; RV32I-NEXT: xor a0, a0, a1987; RV32I-NEXT: sub a0, a0, a1988; RV32I-NEXT: ret989;990; RV64I-LABEL: abd_minmax_i16:991; RV64I: # %bb.0:992; RV64I-NEXT: slli a1, a1, 48993; RV64I-NEXT: slli a0, a0, 48994; RV64I-NEXT: srai a1, a1, 48995; RV64I-NEXT: srai a0, a0, 48996; RV64I-NEXT: sub a0, a0, a1997; RV64I-NEXT: srai a1, a0, 63998; RV64I-NEXT: xor a0, a0, a1999; RV64I-NEXT: sub a0, a0, a11000; RV64I-NEXT: ret1001;1002; ZBB-LABEL: abd_minmax_i16:1003; ZBB: # %bb.0:1004; ZBB-NEXT: sext.h a1, a11005; ZBB-NEXT: sext.h a0, a01006; ZBB-NEXT: min a2, a0, a11007; ZBB-NEXT: max a0, a0, a11008; ZBB-NEXT: sub a0, a0, a21009; ZBB-NEXT: ret1010 %min = call i16 @llvm.smin.i16(i16 %a, i16 %b)1011 %max = call i16 @llvm.smax.i16(i16 %a, i16 %b)1012 %sub = sub i16 %max, %min1013 ret i16 %sub1014}1015 1016define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {1017; RV32I-LABEL: abd_minmax_i32:1018; RV32I: # %bb.0:1019; RV32I-NEXT: blt a1, a0, .LBB15_21020; RV32I-NEXT: # %bb.1:1021; RV32I-NEXT: sub a0, a1, a01022; RV32I-NEXT: ret1023; RV32I-NEXT: .LBB15_2:1024; RV32I-NEXT: sub a0, a0, a11025; RV32I-NEXT: ret1026;1027; RV64I-LABEL: abd_minmax_i32:1028; RV64I: # %bb.0:1029; RV64I-NEXT: sext.w a1, a11030; RV64I-NEXT: sext.w a0, a01031; RV64I-NEXT: sub a0, a0, a11032; RV64I-NEXT: srai a1, a0, 631033; RV64I-NEXT: xor a0, a0, a11034; RV64I-NEXT: sub a0, a0, a11035; RV64I-NEXT: ret1036;1037; RV32ZBB-LABEL: abd_minmax_i32:1038; RV32ZBB: # %bb.0:1039; RV32ZBB-NEXT: min a2, a0, a11040; RV32ZBB-NEXT: max a0, a0, a11041; RV32ZBB-NEXT: sub a0, a0, a21042; RV32ZBB-NEXT: ret1043;1044; RV64ZBB-LABEL: abd_minmax_i32:1045; RV64ZBB: # %bb.0:1046; RV64ZBB-NEXT: sext.w a1, a11047; RV64ZBB-NEXT: sext.w a0, a01048; RV64ZBB-NEXT: min a2, a0, a11049; RV64ZBB-NEXT: max a0, a0, a11050; RV64ZBB-NEXT: sub a0, a0, a21051; RV64ZBB-NEXT: ret1052 %min = call i32 @llvm.smin.i32(i32 %a, i32 %b)1053 %max = call i32 @llvm.smax.i32(i32 %a, i32 %b)1054 %sub = sub i32 %max, %min1055 ret i32 %sub1056}1057 1058define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {1059; RV32I-LABEL: abd_minmax_i64:1060; RV32I: # %bb.0:1061; RV32I-NEXT: sltu a4, a2, a01062; RV32I-NEXT: mv a5, a41063; RV32I-NEXT: beq a1, a3, .LBB16_21064; RV32I-NEXT: # %bb.1:1065; RV32I-NEXT: slt a5, a3, a11066; RV32I-NEXT: .LBB16_2:1067; RV32I-NEXT: bnez a5, .LBB16_41068; RV32I-NEXT: # %bb.3:1069; RV32I-NEXT: sub a1, a3, a11070; RV32I-NEXT: sub a1, a1, a41071; RV32I-NEXT: sub a0, a2, a01072; RV32I-NEXT: ret1073; RV32I-NEXT: .LBB16_4:1074; RV32I-NEXT: sltu a4, a0, a21075; RV32I-NEXT: sub a1, a1, a31076; RV32I-NEXT: sub a1, a1, a41077; RV32I-NEXT: sub a0, a0, a21078; RV32I-NEXT: ret1079;1080; RV64I-LABEL: abd_minmax_i64:1081; RV64I: # %bb.0:1082; RV64I-NEXT: blt a1, a0, .LBB16_21083; RV64I-NEXT: # %bb.1:1084; RV64I-NEXT: sub a0, a1, a01085; RV64I-NEXT: ret1086; RV64I-NEXT: .LBB16_2:1087; RV64I-NEXT: sub a0, a0, a11088; RV64I-NEXT: ret1089;1090; RV32ZBB-LABEL: abd_minmax_i64:1091; RV32ZBB: # %bb.0:1092; RV32ZBB-NEXT: sltu a4, a2, a01093; RV32ZBB-NEXT: mv a5, a41094; RV32ZBB-NEXT: beq a1, a3, .LBB16_21095; RV32ZBB-NEXT: # %bb.1:1096; RV32ZBB-NEXT: slt a5, a3, a11097; RV32ZBB-NEXT: .LBB16_2:1098; RV32ZBB-NEXT: bnez a5, .LBB16_41099; RV32ZBB-NEXT: # %bb.3:1100; RV32ZBB-NEXT: sub a1, a3, a11101; RV32ZBB-NEXT: sub a1, a1, a41102; RV32ZBB-NEXT: sub a0, a2, a01103; RV32ZBB-NEXT: ret1104; RV32ZBB-NEXT: .LBB16_4:1105; RV32ZBB-NEXT: sltu a4, a0, a21106; RV32ZBB-NEXT: sub a1, a1, a31107; RV32ZBB-NEXT: sub a1, a1, a41108; RV32ZBB-NEXT: sub a0, a0, a21109; RV32ZBB-NEXT: ret1110;1111; RV64ZBB-LABEL: abd_minmax_i64:1112; RV64ZBB: # %bb.0:1113; RV64ZBB-NEXT: min a2, a0, a11114; RV64ZBB-NEXT: max a0, a0, a11115; RV64ZBB-NEXT: sub a0, a0, a21116; RV64ZBB-NEXT: ret1117 %min = call i64 @llvm.smin.i64(i64 %a, i64 %b)1118 %max = call i64 @llvm.smax.i64(i64 %a, i64 %b)1119 %sub = sub i64 %max, %min1120 ret i64 %sub1121}1122 1123define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {1124; RV32I-LABEL: abd_minmax_i128:1125; RV32I: # %bb.0:1126; RV32I-NEXT: lw a3, 0(a1)1127; RV32I-NEXT: lw a4, 4(a1)1128; RV32I-NEXT: lw a5, 8(a1)1129; RV32I-NEXT: lw a7, 12(a1)1130; RV32I-NEXT: lw a1, 0(a2)1131; RV32I-NEXT: lw a6, 8(a2)1132; RV32I-NEXT: lw t1, 12(a2)1133; RV32I-NEXT: lw a2, 4(a2)1134; RV32I-NEXT: sltu t0, a6, a51135; RV32I-NEXT: mv t4, t01136; RV32I-NEXT: beq a7, t1, .LBB17_21137; RV32I-NEXT: # %bb.1:1138; RV32I-NEXT: slt t4, t1, a71139; RV32I-NEXT: .LBB17_2:1140; RV32I-NEXT: sltu t2, a1, a31141; RV32I-NEXT: sltu t5, a2, a41142; RV32I-NEXT: mv t3, t21143; RV32I-NEXT: beq a4, a2, .LBB17_41144; RV32I-NEXT: # %bb.3:1145; RV32I-NEXT: mv t3, t51146; RV32I-NEXT: .LBB17_4:1147; RV32I-NEXT: addi sp, sp, -161148; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1149; RV32I-NEXT: xor t6, a7, t11150; RV32I-NEXT: xor s0, a5, a61151; RV32I-NEXT: or t6, s0, t61152; RV32I-NEXT: beqz t6, .LBB17_61153; RV32I-NEXT: # %bb.5:1154; RV32I-NEXT: mv t3, t41155; RV32I-NEXT: .LBB17_6:1156; RV32I-NEXT: mv t4, t21157; RV32I-NEXT: beq a2, a4, .LBB17_81158; RV32I-NEXT: # %bb.7:1159; RV32I-NEXT: mv t4, t51160; RV32I-NEXT: .LBB17_8:1161; RV32I-NEXT: sltu t5, a3, a11162; RV32I-NEXT: mv t6, t51163; RV32I-NEXT: beq a4, a2, .LBB17_101164; RV32I-NEXT: # %bb.9:1165; RV32I-NEXT: sltu t6, a4, a21166; RV32I-NEXT: .LBB17_10:1167; RV32I-NEXT: bnez t3, .LBB17_121168; RV32I-NEXT: # %bb.11:1169; RV32I-NEXT: sub a7, t1, a71170; RV32I-NEXT: sub a5, a6, a51171; RV32I-NEXT: sub a1, a1, a31172; RV32I-NEXT: sub a2, a2, a41173; RV32I-NEXT: sub a4, a7, t01174; RV32I-NEXT: sltu a6, a5, t41175; RV32I-NEXT: sub a3, a2, t21176; RV32I-NEXT: sub a2, a4, a61177; RV32I-NEXT: sub a4, a5, t41178; RV32I-NEXT: j .LBB17_131179; RV32I-NEXT: .LBB17_12:1180; RV32I-NEXT: sltu t0, a5, a61181; RV32I-NEXT: sub a7, a7, t11182; RV32I-NEXT: sub a5, a5, a61183; RV32I-NEXT: sub a1, a3, a11184; RV32I-NEXT: sub a4, a4, a21185; RV32I-NEXT: sub a2, a7, t01186; RV32I-NEXT: sltu a6, a5, t61187; RV32I-NEXT: sub a3, a4, t51188; RV32I-NEXT: sub a2, a2, a61189; RV32I-NEXT: sub a4, a5, t61190; RV32I-NEXT: .LBB17_13:1191; RV32I-NEXT: sw a1, 0(a0)1192; RV32I-NEXT: sw a3, 4(a0)1193; RV32I-NEXT: sw a4, 8(a0)1194; RV32I-NEXT: sw a2, 12(a0)1195; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1196; RV32I-NEXT: addi sp, sp, 161197; RV32I-NEXT: ret1198;1199; RV64I-LABEL: abd_minmax_i128:1200; RV64I: # %bb.0:1201; RV64I-NEXT: sltu a4, a2, a01202; RV64I-NEXT: mv a5, a41203; RV64I-NEXT: beq a1, a3, .LBB17_21204; RV64I-NEXT: # %bb.1:1205; RV64I-NEXT: slt a5, a3, a11206; RV64I-NEXT: .LBB17_2:1207; RV64I-NEXT: bnez a5, .LBB17_41208; RV64I-NEXT: # %bb.3:1209; RV64I-NEXT: sub a1, a3, a11210; RV64I-NEXT: sub a1, a1, a41211; RV64I-NEXT: sub a0, a2, a01212; RV64I-NEXT: ret1213; RV64I-NEXT: .LBB17_4:1214; RV64I-NEXT: sltu a4, a0, a21215; RV64I-NEXT: sub a1, a1, a31216; RV64I-NEXT: sub a1, a1, a41217; RV64I-NEXT: sub a0, a0, a21218; RV64I-NEXT: ret1219;1220; RV32ZBB-LABEL: abd_minmax_i128:1221; RV32ZBB: # %bb.0:1222; RV32ZBB-NEXT: lw a3, 0(a1)1223; RV32ZBB-NEXT: lw a4, 4(a1)1224; RV32ZBB-NEXT: lw a5, 8(a1)1225; RV32ZBB-NEXT: lw a7, 12(a1)1226; RV32ZBB-NEXT: lw a1, 0(a2)1227; RV32ZBB-NEXT: lw a6, 8(a2)1228; RV32ZBB-NEXT: lw t1, 12(a2)1229; RV32ZBB-NEXT: lw a2, 4(a2)1230; RV32ZBB-NEXT: sltu t0, a6, a51231; RV32ZBB-NEXT: mv t4, t01232; RV32ZBB-NEXT: beq a7, t1, .LBB17_21233; RV32ZBB-NEXT: # %bb.1:1234; RV32ZBB-NEXT: slt t4, t1, a71235; RV32ZBB-NEXT: .LBB17_2:1236; RV32ZBB-NEXT: sltu t2, a1, a31237; RV32ZBB-NEXT: sltu t5, a2, a41238; RV32ZBB-NEXT: mv t3, t21239; RV32ZBB-NEXT: beq a4, a2, .LBB17_41240; RV32ZBB-NEXT: # %bb.3:1241; RV32ZBB-NEXT: mv t3, t51242; RV32ZBB-NEXT: .LBB17_4:1243; RV32ZBB-NEXT: addi sp, sp, -161244; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1245; RV32ZBB-NEXT: xor t6, a7, t11246; RV32ZBB-NEXT: xor s0, a5, a61247; RV32ZBB-NEXT: or t6, s0, t61248; RV32ZBB-NEXT: beqz t6, .LBB17_61249; RV32ZBB-NEXT: # %bb.5:1250; RV32ZBB-NEXT: mv t3, t41251; RV32ZBB-NEXT: .LBB17_6:1252; RV32ZBB-NEXT: mv t4, t21253; RV32ZBB-NEXT: beq a2, a4, .LBB17_81254; RV32ZBB-NEXT: # %bb.7:1255; RV32ZBB-NEXT: mv t4, t51256; RV32ZBB-NEXT: .LBB17_8:1257; RV32ZBB-NEXT: sltu t5, a3, a11258; RV32ZBB-NEXT: mv t6, t51259; RV32ZBB-NEXT: beq a4, a2, .LBB17_101260; RV32ZBB-NEXT: # %bb.9:1261; RV32ZBB-NEXT: sltu t6, a4, a21262; RV32ZBB-NEXT: .LBB17_10:1263; RV32ZBB-NEXT: bnez t3, .LBB17_121264; RV32ZBB-NEXT: # %bb.11:1265; RV32ZBB-NEXT: sub a7, t1, a71266; RV32ZBB-NEXT: sub a5, a6, a51267; RV32ZBB-NEXT: sub a1, a1, a31268; RV32ZBB-NEXT: sub a2, a2, a41269; RV32ZBB-NEXT: sub a4, a7, t01270; RV32ZBB-NEXT: sltu a6, a5, t41271; RV32ZBB-NEXT: sub a3, a2, t21272; RV32ZBB-NEXT: sub a2, a4, a61273; RV32ZBB-NEXT: sub a4, a5, t41274; RV32ZBB-NEXT: j .LBB17_131275; RV32ZBB-NEXT: .LBB17_12:1276; RV32ZBB-NEXT: sltu t0, a5, a61277; RV32ZBB-NEXT: sub a7, a7, t11278; RV32ZBB-NEXT: sub a5, a5, a61279; RV32ZBB-NEXT: sub a1, a3, a11280; RV32ZBB-NEXT: sub a4, a4, a21281; RV32ZBB-NEXT: sub a2, a7, t01282; RV32ZBB-NEXT: sltu a6, a5, t61283; RV32ZBB-NEXT: sub a3, a4, t51284; RV32ZBB-NEXT: sub a2, a2, a61285; RV32ZBB-NEXT: sub a4, a5, t61286; RV32ZBB-NEXT: .LBB17_13:1287; RV32ZBB-NEXT: sw a1, 0(a0)1288; RV32ZBB-NEXT: sw a3, 4(a0)1289; RV32ZBB-NEXT: sw a4, 8(a0)1290; RV32ZBB-NEXT: sw a2, 12(a0)1291; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1292; RV32ZBB-NEXT: addi sp, sp, 161293; RV32ZBB-NEXT: ret1294;1295; RV64ZBB-LABEL: abd_minmax_i128:1296; RV64ZBB: # %bb.0:1297; RV64ZBB-NEXT: sltu a4, a2, a01298; RV64ZBB-NEXT: mv a5, a41299; RV64ZBB-NEXT: beq a1, a3, .LBB17_21300; RV64ZBB-NEXT: # %bb.1:1301; RV64ZBB-NEXT: slt a5, a3, a11302; RV64ZBB-NEXT: .LBB17_2:1303; RV64ZBB-NEXT: bnez a5, .LBB17_41304; RV64ZBB-NEXT: # %bb.3:1305; RV64ZBB-NEXT: sub a1, a3, a11306; RV64ZBB-NEXT: sub a1, a1, a41307; RV64ZBB-NEXT: sub a0, a2, a01308; RV64ZBB-NEXT: ret1309; RV64ZBB-NEXT: .LBB17_4:1310; RV64ZBB-NEXT: sltu a4, a0, a21311; RV64ZBB-NEXT: sub a1, a1, a31312; RV64ZBB-NEXT: sub a1, a1, a41313; RV64ZBB-NEXT: sub a0, a0, a21314; RV64ZBB-NEXT: ret1315 %min = call i128 @llvm.smin.i128(i128 %a, i128 %b)1316 %max = call i128 @llvm.smax.i128(i128 %a, i128 %b)1317 %sub = sub i128 %max, %min1318 ret i128 %sub1319}1320 1321;1322; select(icmp(a,b),sub(a,b),sub(b,a)) -> abds(a,b)1323;1324 1325define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {1326; RV32I-LABEL: abd_cmp_i8:1327; RV32I: # %bb.0:1328; RV32I-NEXT: slli a1, a1, 241329; RV32I-NEXT: slli a0, a0, 241330; RV32I-NEXT: srai a1, a1, 241331; RV32I-NEXT: srai a0, a0, 241332; RV32I-NEXT: sub a0, a0, a11333; RV32I-NEXT: srai a1, a0, 311334; RV32I-NEXT: xor a0, a0, a11335; RV32I-NEXT: sub a0, a0, a11336; RV32I-NEXT: ret1337;1338; RV64I-LABEL: abd_cmp_i8:1339; RV64I: # %bb.0:1340; RV64I-NEXT: slli a1, a1, 561341; RV64I-NEXT: slli a0, a0, 561342; RV64I-NEXT: srai a1, a1, 561343; RV64I-NEXT: srai a0, a0, 561344; RV64I-NEXT: sub a0, a0, a11345; RV64I-NEXT: srai a1, a0, 631346; RV64I-NEXT: xor a0, a0, a11347; RV64I-NEXT: sub a0, a0, a11348; RV64I-NEXT: ret1349;1350; ZBB-LABEL: abd_cmp_i8:1351; ZBB: # %bb.0:1352; ZBB-NEXT: sext.b a1, a11353; ZBB-NEXT: sext.b a0, a01354; ZBB-NEXT: min a2, a0, a11355; ZBB-NEXT: max a0, a0, a11356; ZBB-NEXT: sub a0, a0, a21357; ZBB-NEXT: ret1358 %cmp = icmp sgt i8 %a, %b1359 %ab = sub i8 %a, %b1360 %ba = sub i8 %b, %a1361 %sel = select i1 %cmp, i8 %ab, i8 %ba1362 ret i8 %sel1363}1364 1365define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {1366; RV32I-LABEL: abd_cmp_i16:1367; RV32I: # %bb.0:1368; RV32I-NEXT: slli a1, a1, 161369; RV32I-NEXT: slli a0, a0, 161370; RV32I-NEXT: srai a1, a1, 161371; RV32I-NEXT: srai a0, a0, 161372; RV32I-NEXT: sub a0, a0, a11373; RV32I-NEXT: srai a1, a0, 311374; RV32I-NEXT: xor a0, a0, a11375; RV32I-NEXT: sub a0, a0, a11376; RV32I-NEXT: ret1377;1378; RV64I-LABEL: abd_cmp_i16:1379; RV64I: # %bb.0:1380; RV64I-NEXT: slli a1, a1, 481381; RV64I-NEXT: slli a0, a0, 481382; RV64I-NEXT: srai a1, a1, 481383; RV64I-NEXT: srai a0, a0, 481384; RV64I-NEXT: sub a0, a0, a11385; RV64I-NEXT: srai a1, a0, 631386; RV64I-NEXT: xor a0, a0, a11387; RV64I-NEXT: sub a0, a0, a11388; RV64I-NEXT: ret1389;1390; ZBB-LABEL: abd_cmp_i16:1391; ZBB: # %bb.0:1392; ZBB-NEXT: sext.h a1, a11393; ZBB-NEXT: sext.h a0, a01394; ZBB-NEXT: min a2, a0, a11395; ZBB-NEXT: max a0, a0, a11396; ZBB-NEXT: sub a0, a0, a21397; ZBB-NEXT: ret1398 %cmp = icmp sge i16 %a, %b1399 %ab = sub i16 %a, %b1400 %ba = sub i16 %b, %a1401 %sel = select i1 %cmp, i16 %ab, i16 %ba1402 ret i16 %sel1403}1404 1405define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {1406; RV32I-LABEL: abd_cmp_i32:1407; RV32I: # %bb.0:1408; RV32I-NEXT: blt a1, a0, .LBB20_21409; RV32I-NEXT: # %bb.1:1410; RV32I-NEXT: sub a0, a1, a01411; RV32I-NEXT: ret1412; RV32I-NEXT: .LBB20_2:1413; RV32I-NEXT: sub a0, a0, a11414; RV32I-NEXT: ret1415;1416; RV64I-LABEL: abd_cmp_i32:1417; RV64I: # %bb.0:1418; RV64I-NEXT: sext.w a1, a11419; RV64I-NEXT: sext.w a0, a01420; RV64I-NEXT: sub a0, a0, a11421; RV64I-NEXT: srai a1, a0, 631422; RV64I-NEXT: xor a0, a0, a11423; RV64I-NEXT: sub a0, a0, a11424; RV64I-NEXT: ret1425;1426; RV32ZBB-LABEL: abd_cmp_i32:1427; RV32ZBB: # %bb.0:1428; RV32ZBB-NEXT: min a2, a0, a11429; RV32ZBB-NEXT: max a0, a0, a11430; RV32ZBB-NEXT: sub a0, a0, a21431; RV32ZBB-NEXT: ret1432;1433; RV64ZBB-LABEL: abd_cmp_i32:1434; RV64ZBB: # %bb.0:1435; RV64ZBB-NEXT: sext.w a1, a11436; RV64ZBB-NEXT: sext.w a0, a01437; RV64ZBB-NEXT: min a2, a0, a11438; RV64ZBB-NEXT: max a0, a0, a11439; RV64ZBB-NEXT: sub a0, a0, a21440; RV64ZBB-NEXT: ret1441 %cmp = icmp slt i32 %a, %b1442 %ab = sub i32 %a, %b1443 %ba = sub i32 %b, %a1444 %sel = select i1 %cmp, i32 %ba, i32 %ab1445 ret i32 %sel1446}1447 1448define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {1449; RV32I-LABEL: abd_cmp_i64:1450; RV32I: # %bb.0:1451; RV32I-NEXT: sltu a4, a2, a01452; RV32I-NEXT: mv a5, a41453; RV32I-NEXT: beq a1, a3, .LBB21_21454; RV32I-NEXT: # %bb.1:1455; RV32I-NEXT: slt a5, a3, a11456; RV32I-NEXT: .LBB21_2:1457; RV32I-NEXT: bnez a5, .LBB21_41458; RV32I-NEXT: # %bb.3:1459; RV32I-NEXT: sub a1, a3, a11460; RV32I-NEXT: sub a1, a1, a41461; RV32I-NEXT: sub a0, a2, a01462; RV32I-NEXT: ret1463; RV32I-NEXT: .LBB21_4:1464; RV32I-NEXT: sltu a4, a0, a21465; RV32I-NEXT: sub a1, a1, a31466; RV32I-NEXT: sub a1, a1, a41467; RV32I-NEXT: sub a0, a0, a21468; RV32I-NEXT: ret1469;1470; RV64I-LABEL: abd_cmp_i64:1471; RV64I: # %bb.0:1472; RV64I-NEXT: blt a1, a0, .LBB21_21473; RV64I-NEXT: # %bb.1:1474; RV64I-NEXT: sub a0, a1, a01475; RV64I-NEXT: ret1476; RV64I-NEXT: .LBB21_2:1477; RV64I-NEXT: sub a0, a0, a11478; RV64I-NEXT: ret1479;1480; RV32ZBB-LABEL: abd_cmp_i64:1481; RV32ZBB: # %bb.0:1482; RV32ZBB-NEXT: sltu a4, a2, a01483; RV32ZBB-NEXT: mv a5, a41484; RV32ZBB-NEXT: beq a1, a3, .LBB21_21485; RV32ZBB-NEXT: # %bb.1:1486; RV32ZBB-NEXT: slt a5, a3, a11487; RV32ZBB-NEXT: .LBB21_2:1488; RV32ZBB-NEXT: bnez a5, .LBB21_41489; RV32ZBB-NEXT: # %bb.3:1490; RV32ZBB-NEXT: sub a1, a3, a11491; RV32ZBB-NEXT: sub a1, a1, a41492; RV32ZBB-NEXT: sub a0, a2, a01493; RV32ZBB-NEXT: ret1494; RV32ZBB-NEXT: .LBB21_4:1495; RV32ZBB-NEXT: sltu a4, a0, a21496; RV32ZBB-NEXT: sub a1, a1, a31497; RV32ZBB-NEXT: sub a1, a1, a41498; RV32ZBB-NEXT: sub a0, a0, a21499; RV32ZBB-NEXT: ret1500;1501; RV64ZBB-LABEL: abd_cmp_i64:1502; RV64ZBB: # %bb.0:1503; RV64ZBB-NEXT: min a2, a0, a11504; RV64ZBB-NEXT: max a0, a0, a11505; RV64ZBB-NEXT: sub a0, a0, a21506; RV64ZBB-NEXT: ret1507 %cmp = icmp sge i64 %a, %b1508 %ab = sub i64 %a, %b1509 %ba = sub i64 %b, %a1510 %sel = select i1 %cmp, i64 %ab, i64 %ba1511 ret i64 %sel1512}1513 1514define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {1515; RV32I-LABEL: abd_cmp_i128:1516; RV32I: # %bb.0:1517; RV32I-NEXT: lw a3, 0(a1)1518; RV32I-NEXT: lw a4, 4(a1)1519; RV32I-NEXT: lw a5, 8(a1)1520; RV32I-NEXT: lw a7, 12(a1)1521; RV32I-NEXT: lw a1, 0(a2)1522; RV32I-NEXT: lw a6, 8(a2)1523; RV32I-NEXT: lw t1, 12(a2)1524; RV32I-NEXT: lw a2, 4(a2)1525; RV32I-NEXT: sltu t0, a6, a51526; RV32I-NEXT: mv t4, t01527; RV32I-NEXT: beq a7, t1, .LBB22_21528; RV32I-NEXT: # %bb.1:1529; RV32I-NEXT: slt t4, t1, a71530; RV32I-NEXT: .LBB22_2:1531; RV32I-NEXT: sltu t2, a1, a31532; RV32I-NEXT: sltu t5, a2, a41533; RV32I-NEXT: mv t3, t21534; RV32I-NEXT: beq a4, a2, .LBB22_41535; RV32I-NEXT: # %bb.3:1536; RV32I-NEXT: mv t3, t51537; RV32I-NEXT: .LBB22_4:1538; RV32I-NEXT: addi sp, sp, -161539; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1540; RV32I-NEXT: xor t6, a7, t11541; RV32I-NEXT: xor s0, a5, a61542; RV32I-NEXT: or t6, s0, t61543; RV32I-NEXT: beqz t6, .LBB22_61544; RV32I-NEXT: # %bb.5:1545; RV32I-NEXT: mv t3, t41546; RV32I-NEXT: .LBB22_6:1547; RV32I-NEXT: mv t4, t21548; RV32I-NEXT: beq a2, a4, .LBB22_81549; RV32I-NEXT: # %bb.7:1550; RV32I-NEXT: mv t4, t51551; RV32I-NEXT: .LBB22_8:1552; RV32I-NEXT: sltu t5, a3, a11553; RV32I-NEXT: mv t6, t51554; RV32I-NEXT: beq a4, a2, .LBB22_101555; RV32I-NEXT: # %bb.9:1556; RV32I-NEXT: sltu t6, a4, a21557; RV32I-NEXT: .LBB22_10:1558; RV32I-NEXT: bnez t3, .LBB22_121559; RV32I-NEXT: # %bb.11:1560; RV32I-NEXT: sub a7, t1, a71561; RV32I-NEXT: sub a5, a6, a51562; RV32I-NEXT: sub a1, a1, a31563; RV32I-NEXT: sub a2, a2, a41564; RV32I-NEXT: sub a4, a7, t01565; RV32I-NEXT: sltu a6, a5, t41566; RV32I-NEXT: sub a3, a2, t21567; RV32I-NEXT: sub a2, a4, a61568; RV32I-NEXT: sub a4, a5, t41569; RV32I-NEXT: j .LBB22_131570; RV32I-NEXT: .LBB22_12:1571; RV32I-NEXT: sltu t0, a5, a61572; RV32I-NEXT: sub a7, a7, t11573; RV32I-NEXT: sub a5, a5, a61574; RV32I-NEXT: sub a1, a3, a11575; RV32I-NEXT: sub a4, a4, a21576; RV32I-NEXT: sub a2, a7, t01577; RV32I-NEXT: sltu a6, a5, t61578; RV32I-NEXT: sub a3, a4, t51579; RV32I-NEXT: sub a2, a2, a61580; RV32I-NEXT: sub a4, a5, t61581; RV32I-NEXT: .LBB22_13:1582; RV32I-NEXT: sw a1, 0(a0)1583; RV32I-NEXT: sw a3, 4(a0)1584; RV32I-NEXT: sw a4, 8(a0)1585; RV32I-NEXT: sw a2, 12(a0)1586; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1587; RV32I-NEXT: addi sp, sp, 161588; RV32I-NEXT: ret1589;1590; RV64I-LABEL: abd_cmp_i128:1591; RV64I: # %bb.0:1592; RV64I-NEXT: sltu a4, a2, a01593; RV64I-NEXT: mv a5, a41594; RV64I-NEXT: beq a1, a3, .LBB22_21595; RV64I-NEXT: # %bb.1:1596; RV64I-NEXT: slt a5, a3, a11597; RV64I-NEXT: .LBB22_2:1598; RV64I-NEXT: bnez a5, .LBB22_41599; RV64I-NEXT: # %bb.3:1600; RV64I-NEXT: sub a1, a3, a11601; RV64I-NEXT: sub a1, a1, a41602; RV64I-NEXT: sub a0, a2, a01603; RV64I-NEXT: ret1604; RV64I-NEXT: .LBB22_4:1605; RV64I-NEXT: sltu a4, a0, a21606; RV64I-NEXT: sub a1, a1, a31607; RV64I-NEXT: sub a1, a1, a41608; RV64I-NEXT: sub a0, a0, a21609; RV64I-NEXT: ret1610;1611; RV32ZBB-LABEL: abd_cmp_i128:1612; RV32ZBB: # %bb.0:1613; RV32ZBB-NEXT: lw a3, 0(a1)1614; RV32ZBB-NEXT: lw a4, 4(a1)1615; RV32ZBB-NEXT: lw a5, 8(a1)1616; RV32ZBB-NEXT: lw a7, 12(a1)1617; RV32ZBB-NEXT: lw a1, 0(a2)1618; RV32ZBB-NEXT: lw a6, 8(a2)1619; RV32ZBB-NEXT: lw t1, 12(a2)1620; RV32ZBB-NEXT: lw a2, 4(a2)1621; RV32ZBB-NEXT: sltu t0, a6, a51622; RV32ZBB-NEXT: mv t4, t01623; RV32ZBB-NEXT: beq a7, t1, .LBB22_21624; RV32ZBB-NEXT: # %bb.1:1625; RV32ZBB-NEXT: slt t4, t1, a71626; RV32ZBB-NEXT: .LBB22_2:1627; RV32ZBB-NEXT: sltu t2, a1, a31628; RV32ZBB-NEXT: sltu t5, a2, a41629; RV32ZBB-NEXT: mv t3, t21630; RV32ZBB-NEXT: beq a4, a2, .LBB22_41631; RV32ZBB-NEXT: # %bb.3:1632; RV32ZBB-NEXT: mv t3, t51633; RV32ZBB-NEXT: .LBB22_4:1634; RV32ZBB-NEXT: addi sp, sp, -161635; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1636; RV32ZBB-NEXT: xor t6, a7, t11637; RV32ZBB-NEXT: xor s0, a5, a61638; RV32ZBB-NEXT: or t6, s0, t61639; RV32ZBB-NEXT: beqz t6, .LBB22_61640; RV32ZBB-NEXT: # %bb.5:1641; RV32ZBB-NEXT: mv t3, t41642; RV32ZBB-NEXT: .LBB22_6:1643; RV32ZBB-NEXT: mv t4, t21644; RV32ZBB-NEXT: beq a2, a4, .LBB22_81645; RV32ZBB-NEXT: # %bb.7:1646; RV32ZBB-NEXT: mv t4, t51647; RV32ZBB-NEXT: .LBB22_8:1648; RV32ZBB-NEXT: sltu t5, a3, a11649; RV32ZBB-NEXT: mv t6, t51650; RV32ZBB-NEXT: beq a4, a2, .LBB22_101651; RV32ZBB-NEXT: # %bb.9:1652; RV32ZBB-NEXT: sltu t6, a4, a21653; RV32ZBB-NEXT: .LBB22_10:1654; RV32ZBB-NEXT: bnez t3, .LBB22_121655; RV32ZBB-NEXT: # %bb.11:1656; RV32ZBB-NEXT: sub a7, t1, a71657; RV32ZBB-NEXT: sub a5, a6, a51658; RV32ZBB-NEXT: sub a1, a1, a31659; RV32ZBB-NEXT: sub a2, a2, a41660; RV32ZBB-NEXT: sub a4, a7, t01661; RV32ZBB-NEXT: sltu a6, a5, t41662; RV32ZBB-NEXT: sub a3, a2, t21663; RV32ZBB-NEXT: sub a2, a4, a61664; RV32ZBB-NEXT: sub a4, a5, t41665; RV32ZBB-NEXT: j .LBB22_131666; RV32ZBB-NEXT: .LBB22_12:1667; RV32ZBB-NEXT: sltu t0, a5, a61668; RV32ZBB-NEXT: sub a7, a7, t11669; RV32ZBB-NEXT: sub a5, a5, a61670; RV32ZBB-NEXT: sub a1, a3, a11671; RV32ZBB-NEXT: sub a4, a4, a21672; RV32ZBB-NEXT: sub a2, a7, t01673; RV32ZBB-NEXT: sltu a6, a5, t61674; RV32ZBB-NEXT: sub a3, a4, t51675; RV32ZBB-NEXT: sub a2, a2, a61676; RV32ZBB-NEXT: sub a4, a5, t61677; RV32ZBB-NEXT: .LBB22_13:1678; RV32ZBB-NEXT: sw a1, 0(a0)1679; RV32ZBB-NEXT: sw a3, 4(a0)1680; RV32ZBB-NEXT: sw a4, 8(a0)1681; RV32ZBB-NEXT: sw a2, 12(a0)1682; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1683; RV32ZBB-NEXT: addi sp, sp, 161684; RV32ZBB-NEXT: ret1685;1686; RV64ZBB-LABEL: abd_cmp_i128:1687; RV64ZBB: # %bb.0:1688; RV64ZBB-NEXT: sltu a4, a2, a01689; RV64ZBB-NEXT: mv a5, a41690; RV64ZBB-NEXT: beq a1, a3, .LBB22_21691; RV64ZBB-NEXT: # %bb.1:1692; RV64ZBB-NEXT: slt a5, a3, a11693; RV64ZBB-NEXT: .LBB22_2:1694; RV64ZBB-NEXT: bnez a5, .LBB22_41695; RV64ZBB-NEXT: # %bb.3:1696; RV64ZBB-NEXT: sub a1, a3, a11697; RV64ZBB-NEXT: sub a1, a1, a41698; RV64ZBB-NEXT: sub a0, a2, a01699; RV64ZBB-NEXT: ret1700; RV64ZBB-NEXT: .LBB22_4:1701; RV64ZBB-NEXT: sltu a4, a0, a21702; RV64ZBB-NEXT: sub a1, a1, a31703; RV64ZBB-NEXT: sub a1, a1, a41704; RV64ZBB-NEXT: sub a0, a0, a21705; RV64ZBB-NEXT: ret1706 %cmp = icmp sge i128 %a, %b1707 %ab = sub i128 %a, %b1708 %ba = sub i128 %b, %a1709 %sel = select i1 %cmp, i128 %ab, i128 %ba1710 ret i128 %sel1711}1712 1713;1714; abs(sub_nsw(x, y)) -> abds(a,b)1715;1716 1717define i8 @abd_subnsw_i8(i8 %a, i8 %b) nounwind {1718; RV32I-LABEL: abd_subnsw_i8:1719; RV32I: # %bb.0:1720; RV32I-NEXT: sub a0, a0, a11721; RV32I-NEXT: slli a1, a0, 241722; RV32I-NEXT: srai a1, a1, 311723; RV32I-NEXT: xor a0, a0, a11724; RV32I-NEXT: sub a0, a0, a11725; RV32I-NEXT: ret1726;1727; RV64I-LABEL: abd_subnsw_i8:1728; RV64I: # %bb.0:1729; RV64I-NEXT: sub a0, a0, a11730; RV64I-NEXT: slli a1, a0, 561731; RV64I-NEXT: srai a1, a1, 631732; RV64I-NEXT: xor a0, a0, a11733; RV64I-NEXT: sub a0, a0, a11734; RV64I-NEXT: ret1735;1736; ZBB-LABEL: abd_subnsw_i8:1737; ZBB: # %bb.0:1738; ZBB-NEXT: sub a0, a0, a11739; ZBB-NEXT: sext.b a0, a01740; ZBB-NEXT: neg a1, a01741; ZBB-NEXT: max a0, a0, a11742; ZBB-NEXT: ret1743 %sub = sub nsw i8 %a, %b1744 %abs = call i8 @llvm.abs.i8(i8 %sub, i1 false)1745 ret i8 %abs1746}1747 1748define i8 @abd_subnsw_i8_undef(i8 %a, i8 %b) nounwind {1749; RV32I-LABEL: abd_subnsw_i8_undef:1750; RV32I: # %bb.0:1751; RV32I-NEXT: sub a0, a0, a11752; RV32I-NEXT: slli a1, a0, 241753; RV32I-NEXT: srai a1, a1, 311754; RV32I-NEXT: xor a0, a0, a11755; RV32I-NEXT: sub a0, a0, a11756; RV32I-NEXT: ret1757;1758; RV64I-LABEL: abd_subnsw_i8_undef:1759; RV64I: # %bb.0:1760; RV64I-NEXT: sub a0, a0, a11761; RV64I-NEXT: slli a1, a0, 561762; RV64I-NEXT: srai a1, a1, 631763; RV64I-NEXT: xor a0, a0, a11764; RV64I-NEXT: sub a0, a0, a11765; RV64I-NEXT: ret1766;1767; ZBB-LABEL: abd_subnsw_i8_undef:1768; ZBB: # %bb.0:1769; ZBB-NEXT: sub a0, a0, a11770; ZBB-NEXT: sext.b a0, a01771; ZBB-NEXT: neg a1, a01772; ZBB-NEXT: max a0, a0, a11773; ZBB-NEXT: ret1774 %sub = sub nsw i8 %a, %b1775 %abs = call i8 @llvm.abs.i8(i8 %sub, i1 true)1776 ret i8 %abs1777}1778 1779define i16 @abd_subnsw_i16(i16 %a, i16 %b) nounwind {1780; RV32I-LABEL: abd_subnsw_i16:1781; RV32I: # %bb.0:1782; RV32I-NEXT: sub a0, a0, a11783; RV32I-NEXT: slli a1, a0, 161784; RV32I-NEXT: srai a1, a1, 311785; RV32I-NEXT: xor a0, a0, a11786; RV32I-NEXT: sub a0, a0, a11787; RV32I-NEXT: ret1788;1789; RV64I-LABEL: abd_subnsw_i16:1790; RV64I: # %bb.0:1791; RV64I-NEXT: sub a0, a0, a11792; RV64I-NEXT: slli a1, a0, 481793; RV64I-NEXT: srai a1, a1, 631794; RV64I-NEXT: xor a0, a0, a11795; RV64I-NEXT: sub a0, a0, a11796; RV64I-NEXT: ret1797;1798; ZBB-LABEL: abd_subnsw_i16:1799; ZBB: # %bb.0:1800; ZBB-NEXT: sub a0, a0, a11801; ZBB-NEXT: sext.h a0, a01802; ZBB-NEXT: neg a1, a01803; ZBB-NEXT: max a0, a0, a11804; ZBB-NEXT: ret1805 %sub = sub nsw i16 %a, %b1806 %abs = call i16 @llvm.abs.i16(i16 %sub, i1 false)1807 ret i16 %abs1808}1809 1810define i16 @abd_subnsw_i16_undef(i16 %a, i16 %b) nounwind {1811; RV32I-LABEL: abd_subnsw_i16_undef:1812; RV32I: # %bb.0:1813; RV32I-NEXT: sub a0, a0, a11814; RV32I-NEXT: slli a1, a0, 161815; RV32I-NEXT: srai a1, a1, 311816; RV32I-NEXT: xor a0, a0, a11817; RV32I-NEXT: sub a0, a0, a11818; RV32I-NEXT: ret1819;1820; RV64I-LABEL: abd_subnsw_i16_undef:1821; RV64I: # %bb.0:1822; RV64I-NEXT: sub a0, a0, a11823; RV64I-NEXT: slli a1, a0, 481824; RV64I-NEXT: srai a1, a1, 631825; RV64I-NEXT: xor a0, a0, a11826; RV64I-NEXT: sub a0, a0, a11827; RV64I-NEXT: ret1828;1829; ZBB-LABEL: abd_subnsw_i16_undef:1830; ZBB: # %bb.0:1831; ZBB-NEXT: sub a0, a0, a11832; ZBB-NEXT: sext.h a0, a01833; ZBB-NEXT: neg a1, a01834; ZBB-NEXT: max a0, a0, a11835; ZBB-NEXT: ret1836 %sub = sub nsw i16 %a, %b1837 %abs = call i16 @llvm.abs.i16(i16 %sub, i1 true)1838 ret i16 %abs1839}1840 1841define i32 @abd_subnsw_i32(i32 %a, i32 %b) nounwind {1842; RV32I-LABEL: abd_subnsw_i32:1843; RV32I: # %bb.0:1844; RV32I-NEXT: sub a0, a0, a11845; RV32I-NEXT: srai a1, a0, 311846; RV32I-NEXT: xor a0, a0, a11847; RV32I-NEXT: sub a0, a0, a11848; RV32I-NEXT: ret1849;1850; RV64I-LABEL: abd_subnsw_i32:1851; RV64I: # %bb.0:1852; RV64I-NEXT: sub a0, a0, a11853; RV64I-NEXT: sraiw a1, a0, 311854; RV64I-NEXT: xor a0, a0, a11855; RV64I-NEXT: subw a0, a0, a11856; RV64I-NEXT: ret1857;1858; RV32ZBB-LABEL: abd_subnsw_i32:1859; RV32ZBB: # %bb.0:1860; RV32ZBB-NEXT: sub a0, a0, a11861; RV32ZBB-NEXT: neg a1, a01862; RV32ZBB-NEXT: max a0, a0, a11863; RV32ZBB-NEXT: ret1864;1865; RV64ZBB-LABEL: abd_subnsw_i32:1866; RV64ZBB: # %bb.0:1867; RV64ZBB-NEXT: subw a0, a0, a11868; RV64ZBB-NEXT: negw a1, a01869; RV64ZBB-NEXT: max a0, a0, a11870; RV64ZBB-NEXT: ret1871 %sub = sub nsw i32 %a, %b1872 %abs = call i32 @llvm.abs.i32(i32 %sub, i1 false)1873 ret i32 %abs1874}1875 1876define i32 @abd_subnsw_i32_undef(i32 %a, i32 %b) nounwind {1877; RV32I-LABEL: abd_subnsw_i32_undef:1878; RV32I: # %bb.0:1879; RV32I-NEXT: sub a0, a0, a11880; RV32I-NEXT: srai a1, a0, 311881; RV32I-NEXT: xor a0, a0, a11882; RV32I-NEXT: sub a0, a0, a11883; RV32I-NEXT: ret1884;1885; RV64I-LABEL: abd_subnsw_i32_undef:1886; RV64I: # %bb.0:1887; RV64I-NEXT: sub a0, a0, a11888; RV64I-NEXT: sraiw a1, a0, 311889; RV64I-NEXT: xor a0, a0, a11890; RV64I-NEXT: subw a0, a0, a11891; RV64I-NEXT: ret1892;1893; RV32ZBB-LABEL: abd_subnsw_i32_undef:1894; RV32ZBB: # %bb.0:1895; RV32ZBB-NEXT: sub a0, a0, a11896; RV32ZBB-NEXT: neg a1, a01897; RV32ZBB-NEXT: max a0, a0, a11898; RV32ZBB-NEXT: ret1899;1900; RV64ZBB-LABEL: abd_subnsw_i32_undef:1901; RV64ZBB: # %bb.0:1902; RV64ZBB-NEXT: subw a0, a0, a11903; RV64ZBB-NEXT: negw a1, a01904; RV64ZBB-NEXT: max a0, a0, a11905; RV64ZBB-NEXT: ret1906 %sub = sub nsw i32 %a, %b1907 %abs = call i32 @llvm.abs.i32(i32 %sub, i1 true)1908 ret i32 %abs1909}1910 1911define i64 @abd_subnsw_i64(i64 %a, i64 %b) nounwind {1912; RV32I-LABEL: abd_subnsw_i64:1913; RV32I: # %bb.0:1914; RV32I-NEXT: sltu a4, a0, a21915; RV32I-NEXT: sub a1, a1, a31916; RV32I-NEXT: sub a1, a1, a41917; RV32I-NEXT: sub a0, a0, a21918; RV32I-NEXT: bgez a1, .LBB29_21919; RV32I-NEXT: # %bb.1:1920; RV32I-NEXT: snez a2, a01921; RV32I-NEXT: add a1, a1, a21922; RV32I-NEXT: neg a1, a11923; RV32I-NEXT: neg a0, a01924; RV32I-NEXT: .LBB29_2:1925; RV32I-NEXT: ret1926;1927; RV64I-LABEL: abd_subnsw_i64:1928; RV64I: # %bb.0:1929; RV64I-NEXT: sub a0, a0, a11930; RV64I-NEXT: srai a1, a0, 631931; RV64I-NEXT: xor a0, a0, a11932; RV64I-NEXT: sub a0, a0, a11933; RV64I-NEXT: ret1934;1935; RV32ZBB-LABEL: abd_subnsw_i64:1936; RV32ZBB: # %bb.0:1937; RV32ZBB-NEXT: sltu a4, a0, a21938; RV32ZBB-NEXT: sub a1, a1, a31939; RV32ZBB-NEXT: sub a1, a1, a41940; RV32ZBB-NEXT: sub a0, a0, a21941; RV32ZBB-NEXT: bgez a1, .LBB29_21942; RV32ZBB-NEXT: # %bb.1:1943; RV32ZBB-NEXT: snez a2, a01944; RV32ZBB-NEXT: add a1, a1, a21945; RV32ZBB-NEXT: neg a1, a11946; RV32ZBB-NEXT: neg a0, a01947; RV32ZBB-NEXT: .LBB29_2:1948; RV32ZBB-NEXT: ret1949;1950; RV64ZBB-LABEL: abd_subnsw_i64:1951; RV64ZBB: # %bb.0:1952; RV64ZBB-NEXT: sub a0, a0, a11953; RV64ZBB-NEXT: neg a1, a01954; RV64ZBB-NEXT: max a0, a0, a11955; RV64ZBB-NEXT: ret1956 %sub = sub nsw i64 %a, %b1957 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)1958 ret i64 %abs1959}1960 1961define i64 @abd_subnsw_i64_undef(i64 %a, i64 %b) nounwind {1962; RV32I-LABEL: abd_subnsw_i64_undef:1963; RV32I: # %bb.0:1964; RV32I-NEXT: sltu a4, a0, a21965; RV32I-NEXT: sub a1, a1, a31966; RV32I-NEXT: sub a1, a1, a41967; RV32I-NEXT: sub a0, a0, a21968; RV32I-NEXT: bgez a1, .LBB30_21969; RV32I-NEXT: # %bb.1:1970; RV32I-NEXT: snez a2, a01971; RV32I-NEXT: add a1, a1, a21972; RV32I-NEXT: neg a1, a11973; RV32I-NEXT: neg a0, a01974; RV32I-NEXT: .LBB30_2:1975; RV32I-NEXT: ret1976;1977; RV64I-LABEL: abd_subnsw_i64_undef:1978; RV64I: # %bb.0:1979; RV64I-NEXT: sub a0, a0, a11980; RV64I-NEXT: srai a1, a0, 631981; RV64I-NEXT: xor a0, a0, a11982; RV64I-NEXT: sub a0, a0, a11983; RV64I-NEXT: ret1984;1985; RV32ZBB-LABEL: abd_subnsw_i64_undef:1986; RV32ZBB: # %bb.0:1987; RV32ZBB-NEXT: sltu a4, a0, a21988; RV32ZBB-NEXT: sub a1, a1, a31989; RV32ZBB-NEXT: sub a1, a1, a41990; RV32ZBB-NEXT: sub a0, a0, a21991; RV32ZBB-NEXT: bgez a1, .LBB30_21992; RV32ZBB-NEXT: # %bb.1:1993; RV32ZBB-NEXT: snez a2, a01994; RV32ZBB-NEXT: add a1, a1, a21995; RV32ZBB-NEXT: neg a1, a11996; RV32ZBB-NEXT: neg a0, a01997; RV32ZBB-NEXT: .LBB30_2:1998; RV32ZBB-NEXT: ret1999;2000; RV64ZBB-LABEL: abd_subnsw_i64_undef:2001; RV64ZBB: # %bb.0:2002; RV64ZBB-NEXT: sub a0, a0, a12003; RV64ZBB-NEXT: neg a1, a02004; RV64ZBB-NEXT: max a0, a0, a12005; RV64ZBB-NEXT: ret2006 %sub = sub nsw i64 %a, %b2007 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)2008 ret i64 %abs2009}2010 2011define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {2012; RV32I-LABEL: abd_subnsw_i128:2013; RV32I: # %bb.0:2014; RV32I-NEXT: lw a3, 0(a2)2015; RV32I-NEXT: lw a4, 4(a2)2016; RV32I-NEXT: lw a5, 8(a2)2017; RV32I-NEXT: lw a2, 12(a2)2018; RV32I-NEXT: lw a7, 8(a1)2019; RV32I-NEXT: lw t0, 12(a1)2020; RV32I-NEXT: lw a6, 0(a1)2021; RV32I-NEXT: lw a1, 4(a1)2022; RV32I-NEXT: sltu t1, a7, a52023; RV32I-NEXT: sub t0, t0, a22024; RV32I-NEXT: sltu a2, a6, a32025; RV32I-NEXT: sub t0, t0, t12026; RV32I-NEXT: mv t1, a22027; RV32I-NEXT: beq a1, a4, .LBB31_22028; RV32I-NEXT: # %bb.1:2029; RV32I-NEXT: sltu t1, a1, a42030; RV32I-NEXT: .LBB31_2:2031; RV32I-NEXT: sub a5, a7, a52032; RV32I-NEXT: sub a1, a1, a42033; RV32I-NEXT: sltu a4, a5, t12034; RV32I-NEXT: sub a5, a5, t12035; RV32I-NEXT: sub a4, t0, a42036; RV32I-NEXT: sub a2, a1, a22037; RV32I-NEXT: sub a1, a6, a32038; RV32I-NEXT: bgez a4, .LBB31_42039; RV32I-NEXT: # %bb.3:2040; RV32I-NEXT: snez a3, a22041; RV32I-NEXT: snez a6, a12042; RV32I-NEXT: neg a7, a52043; RV32I-NEXT: snez a5, a52044; RV32I-NEXT: or a3, a6, a32045; RV32I-NEXT: add a4, a4, a52046; RV32I-NEXT: add a2, a2, a62047; RV32I-NEXT: sltu a6, a7, a32048; RV32I-NEXT: neg a4, a42049; RV32I-NEXT: sub a5, a7, a32050; RV32I-NEXT: neg a2, a22051; RV32I-NEXT: sub a4, a4, a62052; RV32I-NEXT: neg a1, a12053; RV32I-NEXT: .LBB31_4:2054; RV32I-NEXT: sw a1, 0(a0)2055; RV32I-NEXT: sw a2, 4(a0)2056; RV32I-NEXT: sw a5, 8(a0)2057; RV32I-NEXT: sw a4, 12(a0)2058; RV32I-NEXT: ret2059;2060; RV64I-LABEL: abd_subnsw_i128:2061; RV64I: # %bb.0:2062; RV64I-NEXT: sltu a4, a0, a22063; RV64I-NEXT: sub a1, a1, a32064; RV64I-NEXT: sub a1, a1, a42065; RV64I-NEXT: sub a0, a0, a22066; RV64I-NEXT: bgez a1, .LBB31_22067; RV64I-NEXT: # %bb.1:2068; RV64I-NEXT: snez a2, a02069; RV64I-NEXT: add a1, a1, a22070; RV64I-NEXT: neg a1, a12071; RV64I-NEXT: neg a0, a02072; RV64I-NEXT: .LBB31_2:2073; RV64I-NEXT: ret2074;2075; RV32ZBB-LABEL: abd_subnsw_i128:2076; RV32ZBB: # %bb.0:2077; RV32ZBB-NEXT: lw a3, 0(a2)2078; RV32ZBB-NEXT: lw a4, 4(a2)2079; RV32ZBB-NEXT: lw a5, 8(a2)2080; RV32ZBB-NEXT: lw a2, 12(a2)2081; RV32ZBB-NEXT: lw a7, 8(a1)2082; RV32ZBB-NEXT: lw t0, 12(a1)2083; RV32ZBB-NEXT: lw a6, 0(a1)2084; RV32ZBB-NEXT: lw a1, 4(a1)2085; RV32ZBB-NEXT: sltu t1, a7, a52086; RV32ZBB-NEXT: sub t0, t0, a22087; RV32ZBB-NEXT: sltu a2, a6, a32088; RV32ZBB-NEXT: sub t0, t0, t12089; RV32ZBB-NEXT: mv t1, a22090; RV32ZBB-NEXT: beq a1, a4, .LBB31_22091; RV32ZBB-NEXT: # %bb.1:2092; RV32ZBB-NEXT: sltu t1, a1, a42093; RV32ZBB-NEXT: .LBB31_2:2094; RV32ZBB-NEXT: sub a5, a7, a52095; RV32ZBB-NEXT: sub a1, a1, a42096; RV32ZBB-NEXT: sltu a4, a5, t12097; RV32ZBB-NEXT: sub a5, a5, t12098; RV32ZBB-NEXT: sub a4, t0, a42099; RV32ZBB-NEXT: sub a2, a1, a22100; RV32ZBB-NEXT: sub a1, a6, a32101; RV32ZBB-NEXT: bgez a4, .LBB31_42102; RV32ZBB-NEXT: # %bb.3:2103; RV32ZBB-NEXT: snez a3, a22104; RV32ZBB-NEXT: snez a6, a12105; RV32ZBB-NEXT: neg a7, a52106; RV32ZBB-NEXT: snez a5, a52107; RV32ZBB-NEXT: or a3, a6, a32108; RV32ZBB-NEXT: add a4, a4, a52109; RV32ZBB-NEXT: add a2, a2, a62110; RV32ZBB-NEXT: sltu a6, a7, a32111; RV32ZBB-NEXT: neg a4, a42112; RV32ZBB-NEXT: sub a5, a7, a32113; RV32ZBB-NEXT: neg a2, a22114; RV32ZBB-NEXT: sub a4, a4, a62115; RV32ZBB-NEXT: neg a1, a12116; RV32ZBB-NEXT: .LBB31_4:2117; RV32ZBB-NEXT: sw a1, 0(a0)2118; RV32ZBB-NEXT: sw a2, 4(a0)2119; RV32ZBB-NEXT: sw a5, 8(a0)2120; RV32ZBB-NEXT: sw a4, 12(a0)2121; RV32ZBB-NEXT: ret2122;2123; RV64ZBB-LABEL: abd_subnsw_i128:2124; RV64ZBB: # %bb.0:2125; RV64ZBB-NEXT: sltu a4, a0, a22126; RV64ZBB-NEXT: sub a1, a1, a32127; RV64ZBB-NEXT: sub a1, a1, a42128; RV64ZBB-NEXT: sub a0, a0, a22129; RV64ZBB-NEXT: bgez a1, .LBB31_22130; RV64ZBB-NEXT: # %bb.1:2131; RV64ZBB-NEXT: snez a2, a02132; RV64ZBB-NEXT: add a1, a1, a22133; RV64ZBB-NEXT: neg a1, a12134; RV64ZBB-NEXT: neg a0, a02135; RV64ZBB-NEXT: .LBB31_2:2136; RV64ZBB-NEXT: ret2137 %sub = sub nsw i128 %a, %b2138 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)2139 ret i128 %abs2140}2141 2142define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {2143; RV32I-LABEL: abd_subnsw_i128_undef:2144; RV32I: # %bb.0:2145; RV32I-NEXT: lw a3, 0(a2)2146; RV32I-NEXT: lw a4, 4(a2)2147; RV32I-NEXT: lw a5, 8(a2)2148; RV32I-NEXT: lw a2, 12(a2)2149; RV32I-NEXT: lw a7, 8(a1)2150; RV32I-NEXT: lw t0, 12(a1)2151; RV32I-NEXT: lw a6, 0(a1)2152; RV32I-NEXT: lw a1, 4(a1)2153; RV32I-NEXT: sltu t1, a7, a52154; RV32I-NEXT: sub t0, t0, a22155; RV32I-NEXT: sltu a2, a6, a32156; RV32I-NEXT: sub t0, t0, t12157; RV32I-NEXT: mv t1, a22158; RV32I-NEXT: beq a1, a4, .LBB32_22159; RV32I-NEXT: # %bb.1:2160; RV32I-NEXT: sltu t1, a1, a42161; RV32I-NEXT: .LBB32_2:2162; RV32I-NEXT: sub a5, a7, a52163; RV32I-NEXT: sub a1, a1, a42164; RV32I-NEXT: sltu a4, a5, t12165; RV32I-NEXT: sub a5, a5, t12166; RV32I-NEXT: sub a4, t0, a42167; RV32I-NEXT: sub a2, a1, a22168; RV32I-NEXT: sub a1, a6, a32169; RV32I-NEXT: bgez a4, .LBB32_42170; RV32I-NEXT: # %bb.3:2171; RV32I-NEXT: snez a3, a22172; RV32I-NEXT: snez a6, a12173; RV32I-NEXT: neg a7, a52174; RV32I-NEXT: snez a5, a52175; RV32I-NEXT: or a3, a6, a32176; RV32I-NEXT: add a4, a4, a52177; RV32I-NEXT: add a2, a2, a62178; RV32I-NEXT: sltu a6, a7, a32179; RV32I-NEXT: neg a4, a42180; RV32I-NEXT: sub a5, a7, a32181; RV32I-NEXT: neg a2, a22182; RV32I-NEXT: sub a4, a4, a62183; RV32I-NEXT: neg a1, a12184; RV32I-NEXT: .LBB32_4:2185; RV32I-NEXT: sw a1, 0(a0)2186; RV32I-NEXT: sw a2, 4(a0)2187; RV32I-NEXT: sw a5, 8(a0)2188; RV32I-NEXT: sw a4, 12(a0)2189; RV32I-NEXT: ret2190;2191; RV64I-LABEL: abd_subnsw_i128_undef:2192; RV64I: # %bb.0:2193; RV64I-NEXT: sltu a4, a0, a22194; RV64I-NEXT: sub a1, a1, a32195; RV64I-NEXT: sub a1, a1, a42196; RV64I-NEXT: sub a0, a0, a22197; RV64I-NEXT: bgez a1, .LBB32_22198; RV64I-NEXT: # %bb.1:2199; RV64I-NEXT: snez a2, a02200; RV64I-NEXT: add a1, a1, a22201; RV64I-NEXT: neg a1, a12202; RV64I-NEXT: neg a0, a02203; RV64I-NEXT: .LBB32_2:2204; RV64I-NEXT: ret2205;2206; RV32ZBB-LABEL: abd_subnsw_i128_undef:2207; RV32ZBB: # %bb.0:2208; RV32ZBB-NEXT: lw a3, 0(a2)2209; RV32ZBB-NEXT: lw a4, 4(a2)2210; RV32ZBB-NEXT: lw a5, 8(a2)2211; RV32ZBB-NEXT: lw a2, 12(a2)2212; RV32ZBB-NEXT: lw a7, 8(a1)2213; RV32ZBB-NEXT: lw t0, 12(a1)2214; RV32ZBB-NEXT: lw a6, 0(a1)2215; RV32ZBB-NEXT: lw a1, 4(a1)2216; RV32ZBB-NEXT: sltu t1, a7, a52217; RV32ZBB-NEXT: sub t0, t0, a22218; RV32ZBB-NEXT: sltu a2, a6, a32219; RV32ZBB-NEXT: sub t0, t0, t12220; RV32ZBB-NEXT: mv t1, a22221; RV32ZBB-NEXT: beq a1, a4, .LBB32_22222; RV32ZBB-NEXT: # %bb.1:2223; RV32ZBB-NEXT: sltu t1, a1, a42224; RV32ZBB-NEXT: .LBB32_2:2225; RV32ZBB-NEXT: sub a5, a7, a52226; RV32ZBB-NEXT: sub a1, a1, a42227; RV32ZBB-NEXT: sltu a4, a5, t12228; RV32ZBB-NEXT: sub a5, a5, t12229; RV32ZBB-NEXT: sub a4, t0, a42230; RV32ZBB-NEXT: sub a2, a1, a22231; RV32ZBB-NEXT: sub a1, a6, a32232; RV32ZBB-NEXT: bgez a4, .LBB32_42233; RV32ZBB-NEXT: # %bb.3:2234; RV32ZBB-NEXT: snez a3, a22235; RV32ZBB-NEXT: snez a6, a12236; RV32ZBB-NEXT: neg a7, a52237; RV32ZBB-NEXT: snez a5, a52238; RV32ZBB-NEXT: or a3, a6, a32239; RV32ZBB-NEXT: add a4, a4, a52240; RV32ZBB-NEXT: add a2, a2, a62241; RV32ZBB-NEXT: sltu a6, a7, a32242; RV32ZBB-NEXT: neg a4, a42243; RV32ZBB-NEXT: sub a5, a7, a32244; RV32ZBB-NEXT: neg a2, a22245; RV32ZBB-NEXT: sub a4, a4, a62246; RV32ZBB-NEXT: neg a1, a12247; RV32ZBB-NEXT: .LBB32_4:2248; RV32ZBB-NEXT: sw a1, 0(a0)2249; RV32ZBB-NEXT: sw a2, 4(a0)2250; RV32ZBB-NEXT: sw a5, 8(a0)2251; RV32ZBB-NEXT: sw a4, 12(a0)2252; RV32ZBB-NEXT: ret2253;2254; RV64ZBB-LABEL: abd_subnsw_i128_undef:2255; RV64ZBB: # %bb.0:2256; RV64ZBB-NEXT: sltu a4, a0, a22257; RV64ZBB-NEXT: sub a1, a1, a32258; RV64ZBB-NEXT: sub a1, a1, a42259; RV64ZBB-NEXT: sub a0, a0, a22260; RV64ZBB-NEXT: bgez a1, .LBB32_22261; RV64ZBB-NEXT: # %bb.1:2262; RV64ZBB-NEXT: snez a2, a02263; RV64ZBB-NEXT: add a1, a1, a22264; RV64ZBB-NEXT: neg a1, a12265; RV64ZBB-NEXT: neg a0, a02266; RV64ZBB-NEXT: .LBB32_2:2267; RV64ZBB-NEXT: ret2268 %sub = sub nsw i128 %a, %b2269 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)2270 ret i128 %abs2271}2272 2273;2274; negative tests2275;2276 2277define i32 @abd_sub_i32(i32 %a, i32 %b) nounwind {2278; RV32I-LABEL: abd_sub_i32:2279; RV32I: # %bb.0:2280; RV32I-NEXT: sub a0, a0, a12281; RV32I-NEXT: srai a1, a0, 312282; RV32I-NEXT: xor a0, a0, a12283; RV32I-NEXT: sub a0, a0, a12284; RV32I-NEXT: ret2285;2286; RV64I-LABEL: abd_sub_i32:2287; RV64I: # %bb.0:2288; RV64I-NEXT: sub a0, a0, a12289; RV64I-NEXT: sraiw a1, a0, 312290; RV64I-NEXT: xor a0, a0, a12291; RV64I-NEXT: subw a0, a0, a12292; RV64I-NEXT: ret2293;2294; RV32ZBB-LABEL: abd_sub_i32:2295; RV32ZBB: # %bb.0:2296; RV32ZBB-NEXT: sub a0, a0, a12297; RV32ZBB-NEXT: neg a1, a02298; RV32ZBB-NEXT: max a0, a0, a12299; RV32ZBB-NEXT: ret2300;2301; RV64ZBB-LABEL: abd_sub_i32:2302; RV64ZBB: # %bb.0:2303; RV64ZBB-NEXT: subw a0, a0, a12304; RV64ZBB-NEXT: negw a1, a02305; RV64ZBB-NEXT: max a0, a0, a12306; RV64ZBB-NEXT: ret2307 %sub = sub i32 %a, %b2308 %abs = call i32 @llvm.abs.i32(i32 %sub, i1 false)2309 ret i32 %abs2310}2311 2312;2313; sub(select(icmp(a,b),a,b),select(icmp(a,b),b,a)) -> abds(a,b)2314;2315 2316define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {2317; RV32I-LABEL: abd_select_i8:2318; RV32I: # %bb.0:2319; RV32I-NEXT: slli a1, a1, 242320; RV32I-NEXT: slli a0, a0, 242321; RV32I-NEXT: srai a1, a1, 242322; RV32I-NEXT: srai a0, a0, 242323; RV32I-NEXT: sub a0, a0, a12324; RV32I-NEXT: srai a1, a0, 312325; RV32I-NEXT: xor a0, a0, a12326; RV32I-NEXT: sub a0, a0, a12327; RV32I-NEXT: ret2328;2329; RV64I-LABEL: abd_select_i8:2330; RV64I: # %bb.0:2331; RV64I-NEXT: slli a1, a1, 562332; RV64I-NEXT: slli a0, a0, 562333; RV64I-NEXT: srai a1, a1, 562334; RV64I-NEXT: srai a0, a0, 562335; RV64I-NEXT: sub a0, a0, a12336; RV64I-NEXT: srai a1, a0, 632337; RV64I-NEXT: xor a0, a0, a12338; RV64I-NEXT: sub a0, a0, a12339; RV64I-NEXT: ret2340;2341; ZBB-LABEL: abd_select_i8:2342; ZBB: # %bb.0:2343; ZBB-NEXT: sext.b a1, a12344; ZBB-NEXT: sext.b a0, a02345; ZBB-NEXT: min a2, a0, a12346; ZBB-NEXT: max a0, a0, a12347; ZBB-NEXT: sub a0, a0, a22348; ZBB-NEXT: ret2349 %cmp = icmp slt i8 %a, %b2350 %ab = select i1 %cmp, i8 %a, i8 %b2351 %ba = select i1 %cmp, i8 %b, i8 %a2352 %sub = sub i8 %ba, %ab2353 ret i8 %sub2354}2355 2356define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {2357; RV32I-LABEL: abd_select_i16:2358; RV32I: # %bb.0:2359; RV32I-NEXT: slli a1, a1, 162360; RV32I-NEXT: slli a0, a0, 162361; RV32I-NEXT: srai a1, a1, 162362; RV32I-NEXT: srai a0, a0, 162363; RV32I-NEXT: sub a0, a0, a12364; RV32I-NEXT: srai a1, a0, 312365; RV32I-NEXT: xor a0, a0, a12366; RV32I-NEXT: sub a0, a0, a12367; RV32I-NEXT: ret2368;2369; RV64I-LABEL: abd_select_i16:2370; RV64I: # %bb.0:2371; RV64I-NEXT: slli a1, a1, 482372; RV64I-NEXT: slli a0, a0, 482373; RV64I-NEXT: srai a1, a1, 482374; RV64I-NEXT: srai a0, a0, 482375; RV64I-NEXT: sub a0, a0, a12376; RV64I-NEXT: srai a1, a0, 632377; RV64I-NEXT: xor a0, a0, a12378; RV64I-NEXT: sub a0, a0, a12379; RV64I-NEXT: ret2380;2381; ZBB-LABEL: abd_select_i16:2382; ZBB: # %bb.0:2383; ZBB-NEXT: sext.h a1, a12384; ZBB-NEXT: sext.h a0, a02385; ZBB-NEXT: min a2, a0, a12386; ZBB-NEXT: max a0, a0, a12387; ZBB-NEXT: sub a0, a0, a22388; ZBB-NEXT: ret2389 %cmp = icmp sle i16 %a, %b2390 %ab = select i1 %cmp, i16 %a, i16 %b2391 %ba = select i1 %cmp, i16 %b, i16 %a2392 %sub = sub i16 %ba, %ab2393 ret i16 %sub2394}2395 2396define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {2397; RV32I-LABEL: abd_select_i32:2398; RV32I: # %bb.0:2399; RV32I-NEXT: blt a1, a0, .LBB36_22400; RV32I-NEXT: # %bb.1:2401; RV32I-NEXT: sub a0, a1, a02402; RV32I-NEXT: ret2403; RV32I-NEXT: .LBB36_2:2404; RV32I-NEXT: sub a0, a0, a12405; RV32I-NEXT: ret2406;2407; RV64I-LABEL: abd_select_i32:2408; RV64I: # %bb.0:2409; RV64I-NEXT: sext.w a1, a12410; RV64I-NEXT: sext.w a0, a02411; RV64I-NEXT: sub a0, a0, a12412; RV64I-NEXT: srai a1, a0, 632413; RV64I-NEXT: xor a0, a0, a12414; RV64I-NEXT: sub a0, a0, a12415; RV64I-NEXT: ret2416;2417; RV32ZBB-LABEL: abd_select_i32:2418; RV32ZBB: # %bb.0:2419; RV32ZBB-NEXT: min a2, a0, a12420; RV32ZBB-NEXT: max a0, a0, a12421; RV32ZBB-NEXT: sub a0, a0, a22422; RV32ZBB-NEXT: ret2423;2424; RV64ZBB-LABEL: abd_select_i32:2425; RV64ZBB: # %bb.0:2426; RV64ZBB-NEXT: sext.w a1, a12427; RV64ZBB-NEXT: sext.w a0, a02428; RV64ZBB-NEXT: min a2, a0, a12429; RV64ZBB-NEXT: max a0, a0, a12430; RV64ZBB-NEXT: sub a0, a0, a22431; RV64ZBB-NEXT: ret2432 %cmp = icmp sgt i32 %a, %b2433 %ab = select i1 %cmp, i32 %a, i32 %b2434 %ba = select i1 %cmp, i32 %b, i32 %a2435 %sub = sub i32 %ab, %ba2436 ret i32 %sub2437}2438 2439define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {2440; RV32I-LABEL: abd_select_i64:2441; RV32I: # %bb.0:2442; RV32I-NEXT: sltu a4, a2, a02443; RV32I-NEXT: mv a5, a42444; RV32I-NEXT: beq a1, a3, .LBB37_22445; RV32I-NEXT: # %bb.1:2446; RV32I-NEXT: slt a5, a3, a12447; RV32I-NEXT: .LBB37_2:2448; RV32I-NEXT: bnez a5, .LBB37_42449; RV32I-NEXT: # %bb.3:2450; RV32I-NEXT: sub a1, a3, a12451; RV32I-NEXT: sub a1, a1, a42452; RV32I-NEXT: sub a0, a2, a02453; RV32I-NEXT: ret2454; RV32I-NEXT: .LBB37_4:2455; RV32I-NEXT: sltu a4, a0, a22456; RV32I-NEXT: sub a1, a1, a32457; RV32I-NEXT: sub a1, a1, a42458; RV32I-NEXT: sub a0, a0, a22459; RV32I-NEXT: ret2460;2461; RV64I-LABEL: abd_select_i64:2462; RV64I: # %bb.0:2463; RV64I-NEXT: blt a1, a0, .LBB37_22464; RV64I-NEXT: # %bb.1:2465; RV64I-NEXT: sub a0, a1, a02466; RV64I-NEXT: ret2467; RV64I-NEXT: .LBB37_2:2468; RV64I-NEXT: sub a0, a0, a12469; RV64I-NEXT: ret2470;2471; RV32ZBB-LABEL: abd_select_i64:2472; RV32ZBB: # %bb.0:2473; RV32ZBB-NEXT: sltu a4, a2, a02474; RV32ZBB-NEXT: mv a5, a42475; RV32ZBB-NEXT: beq a1, a3, .LBB37_22476; RV32ZBB-NEXT: # %bb.1:2477; RV32ZBB-NEXT: slt a5, a3, a12478; RV32ZBB-NEXT: .LBB37_2:2479; RV32ZBB-NEXT: bnez a5, .LBB37_42480; RV32ZBB-NEXT: # %bb.3:2481; RV32ZBB-NEXT: sub a1, a3, a12482; RV32ZBB-NEXT: sub a1, a1, a42483; RV32ZBB-NEXT: sub a0, a2, a02484; RV32ZBB-NEXT: ret2485; RV32ZBB-NEXT: .LBB37_4:2486; RV32ZBB-NEXT: sltu a4, a0, a22487; RV32ZBB-NEXT: sub a1, a1, a32488; RV32ZBB-NEXT: sub a1, a1, a42489; RV32ZBB-NEXT: sub a0, a0, a22490; RV32ZBB-NEXT: ret2491;2492; RV64ZBB-LABEL: abd_select_i64:2493; RV64ZBB: # %bb.0:2494; RV64ZBB-NEXT: min a2, a0, a12495; RV64ZBB-NEXT: max a0, a0, a12496; RV64ZBB-NEXT: sub a0, a0, a22497; RV64ZBB-NEXT: ret2498 %cmp = icmp sge i64 %a, %b2499 %ab = select i1 %cmp, i64 %a, i64 %b2500 %ba = select i1 %cmp, i64 %b, i64 %a2501 %sub = sub i64 %ab, %ba2502 ret i64 %sub2503}2504 2505define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {2506; RV32I-LABEL: abd_select_i128:2507; RV32I: # %bb.0:2508; RV32I-NEXT: lw a3, 0(a1)2509; RV32I-NEXT: lw a4, 4(a1)2510; RV32I-NEXT: lw a5, 8(a1)2511; RV32I-NEXT: lw a7, 12(a1)2512; RV32I-NEXT: lw a1, 0(a2)2513; RV32I-NEXT: lw a6, 8(a2)2514; RV32I-NEXT: lw t1, 12(a2)2515; RV32I-NEXT: lw a2, 4(a2)2516; RV32I-NEXT: sltu t0, a6, a52517; RV32I-NEXT: mv t4, t02518; RV32I-NEXT: beq a7, t1, .LBB38_22519; RV32I-NEXT: # %bb.1:2520; RV32I-NEXT: slt t4, t1, a72521; RV32I-NEXT: .LBB38_2:2522; RV32I-NEXT: sltu t2, a1, a32523; RV32I-NEXT: sltu t5, a2, a42524; RV32I-NEXT: mv t3, t22525; RV32I-NEXT: beq a4, a2, .LBB38_42526; RV32I-NEXT: # %bb.3:2527; RV32I-NEXT: mv t3, t52528; RV32I-NEXT: .LBB38_4:2529; RV32I-NEXT: addi sp, sp, -162530; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill2531; RV32I-NEXT: xor t6, a7, t12532; RV32I-NEXT: xor s0, a5, a62533; RV32I-NEXT: or t6, s0, t62534; RV32I-NEXT: beqz t6, .LBB38_62535; RV32I-NEXT: # %bb.5:2536; RV32I-NEXT: mv t3, t42537; RV32I-NEXT: .LBB38_6:2538; RV32I-NEXT: mv t4, t22539; RV32I-NEXT: beq a2, a4, .LBB38_82540; RV32I-NEXT: # %bb.7:2541; RV32I-NEXT: mv t4, t52542; RV32I-NEXT: .LBB38_8:2543; RV32I-NEXT: sltu t5, a3, a12544; RV32I-NEXT: mv t6, t52545; RV32I-NEXT: beq a4, a2, .LBB38_102546; RV32I-NEXT: # %bb.9:2547; RV32I-NEXT: sltu t6, a4, a22548; RV32I-NEXT: .LBB38_10:2549; RV32I-NEXT: bnez t3, .LBB38_122550; RV32I-NEXT: # %bb.11:2551; RV32I-NEXT: sub a7, t1, a72552; RV32I-NEXT: sub a5, a6, a52553; RV32I-NEXT: sub a1, a1, a32554; RV32I-NEXT: sub a2, a2, a42555; RV32I-NEXT: sub a4, a7, t02556; RV32I-NEXT: sltu a6, a5, t42557; RV32I-NEXT: sub a3, a2, t22558; RV32I-NEXT: sub a2, a4, a62559; RV32I-NEXT: sub a4, a5, t42560; RV32I-NEXT: j .LBB38_132561; RV32I-NEXT: .LBB38_12:2562; RV32I-NEXT: sltu t0, a5, a62563; RV32I-NEXT: sub a7, a7, t12564; RV32I-NEXT: sub a5, a5, a62565; RV32I-NEXT: sub a1, a3, a12566; RV32I-NEXT: sub a4, a4, a22567; RV32I-NEXT: sub a2, a7, t02568; RV32I-NEXT: sltu a6, a5, t62569; RV32I-NEXT: sub a3, a4, t52570; RV32I-NEXT: sub a2, a2, a62571; RV32I-NEXT: sub a4, a5, t62572; RV32I-NEXT: .LBB38_13:2573; RV32I-NEXT: sw a1, 0(a0)2574; RV32I-NEXT: sw a3, 4(a0)2575; RV32I-NEXT: sw a4, 8(a0)2576; RV32I-NEXT: sw a2, 12(a0)2577; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload2578; RV32I-NEXT: addi sp, sp, 162579; RV32I-NEXT: ret2580;2581; RV64I-LABEL: abd_select_i128:2582; RV64I: # %bb.0:2583; RV64I-NEXT: sltu a4, a2, a02584; RV64I-NEXT: mv a5, a42585; RV64I-NEXT: beq a1, a3, .LBB38_22586; RV64I-NEXT: # %bb.1:2587; RV64I-NEXT: slt a5, a3, a12588; RV64I-NEXT: .LBB38_2:2589; RV64I-NEXT: bnez a5, .LBB38_42590; RV64I-NEXT: # %bb.3:2591; RV64I-NEXT: sub a1, a3, a12592; RV64I-NEXT: sub a1, a1, a42593; RV64I-NEXT: sub a0, a2, a02594; RV64I-NEXT: ret2595; RV64I-NEXT: .LBB38_4:2596; RV64I-NEXT: sltu a4, a0, a22597; RV64I-NEXT: sub a1, a1, a32598; RV64I-NEXT: sub a1, a1, a42599; RV64I-NEXT: sub a0, a0, a22600; RV64I-NEXT: ret2601;2602; RV32ZBB-LABEL: abd_select_i128:2603; RV32ZBB: # %bb.0:2604; RV32ZBB-NEXT: lw a3, 0(a1)2605; RV32ZBB-NEXT: lw a4, 4(a1)2606; RV32ZBB-NEXT: lw a5, 8(a1)2607; RV32ZBB-NEXT: lw a7, 12(a1)2608; RV32ZBB-NEXT: lw a1, 0(a2)2609; RV32ZBB-NEXT: lw a6, 8(a2)2610; RV32ZBB-NEXT: lw t1, 12(a2)2611; RV32ZBB-NEXT: lw a2, 4(a2)2612; RV32ZBB-NEXT: sltu t0, a6, a52613; RV32ZBB-NEXT: mv t4, t02614; RV32ZBB-NEXT: beq a7, t1, .LBB38_22615; RV32ZBB-NEXT: # %bb.1:2616; RV32ZBB-NEXT: slt t4, t1, a72617; RV32ZBB-NEXT: .LBB38_2:2618; RV32ZBB-NEXT: sltu t2, a1, a32619; RV32ZBB-NEXT: sltu t5, a2, a42620; RV32ZBB-NEXT: mv t3, t22621; RV32ZBB-NEXT: beq a4, a2, .LBB38_42622; RV32ZBB-NEXT: # %bb.3:2623; RV32ZBB-NEXT: mv t3, t52624; RV32ZBB-NEXT: .LBB38_4:2625; RV32ZBB-NEXT: addi sp, sp, -162626; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill2627; RV32ZBB-NEXT: xor t6, a7, t12628; RV32ZBB-NEXT: xor s0, a5, a62629; RV32ZBB-NEXT: or t6, s0, t62630; RV32ZBB-NEXT: beqz t6, .LBB38_62631; RV32ZBB-NEXT: # %bb.5:2632; RV32ZBB-NEXT: mv t3, t42633; RV32ZBB-NEXT: .LBB38_6:2634; RV32ZBB-NEXT: mv t4, t22635; RV32ZBB-NEXT: beq a2, a4, .LBB38_82636; RV32ZBB-NEXT: # %bb.7:2637; RV32ZBB-NEXT: mv t4, t52638; RV32ZBB-NEXT: .LBB38_8:2639; RV32ZBB-NEXT: sltu t5, a3, a12640; RV32ZBB-NEXT: mv t6, t52641; RV32ZBB-NEXT: beq a4, a2, .LBB38_102642; RV32ZBB-NEXT: # %bb.9:2643; RV32ZBB-NEXT: sltu t6, a4, a22644; RV32ZBB-NEXT: .LBB38_10:2645; RV32ZBB-NEXT: bnez t3, .LBB38_122646; RV32ZBB-NEXT: # %bb.11:2647; RV32ZBB-NEXT: sub a7, t1, a72648; RV32ZBB-NEXT: sub a5, a6, a52649; RV32ZBB-NEXT: sub a1, a1, a32650; RV32ZBB-NEXT: sub a2, a2, a42651; RV32ZBB-NEXT: sub a4, a7, t02652; RV32ZBB-NEXT: sltu a6, a5, t42653; RV32ZBB-NEXT: sub a3, a2, t22654; RV32ZBB-NEXT: sub a2, a4, a62655; RV32ZBB-NEXT: sub a4, a5, t42656; RV32ZBB-NEXT: j .LBB38_132657; RV32ZBB-NEXT: .LBB38_12:2658; RV32ZBB-NEXT: sltu t0, a5, a62659; RV32ZBB-NEXT: sub a7, a7, t12660; RV32ZBB-NEXT: sub a5, a5, a62661; RV32ZBB-NEXT: sub a1, a3, a12662; RV32ZBB-NEXT: sub a4, a4, a22663; RV32ZBB-NEXT: sub a2, a7, t02664; RV32ZBB-NEXT: sltu a6, a5, t62665; RV32ZBB-NEXT: sub a3, a4, t52666; RV32ZBB-NEXT: sub a2, a2, a62667; RV32ZBB-NEXT: sub a4, a5, t62668; RV32ZBB-NEXT: .LBB38_13:2669; RV32ZBB-NEXT: sw a1, 0(a0)2670; RV32ZBB-NEXT: sw a3, 4(a0)2671; RV32ZBB-NEXT: sw a4, 8(a0)2672; RV32ZBB-NEXT: sw a2, 12(a0)2673; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload2674; RV32ZBB-NEXT: addi sp, sp, 162675; RV32ZBB-NEXT: ret2676;2677; RV64ZBB-LABEL: abd_select_i128:2678; RV64ZBB: # %bb.0:2679; RV64ZBB-NEXT: sltu a4, a2, a02680; RV64ZBB-NEXT: mv a5, a42681; RV64ZBB-NEXT: beq a1, a3, .LBB38_22682; RV64ZBB-NEXT: # %bb.1:2683; RV64ZBB-NEXT: slt a5, a3, a12684; RV64ZBB-NEXT: .LBB38_2:2685; RV64ZBB-NEXT: bnez a5, .LBB38_42686; RV64ZBB-NEXT: # %bb.3:2687; RV64ZBB-NEXT: sub a1, a3, a12688; RV64ZBB-NEXT: sub a1, a1, a42689; RV64ZBB-NEXT: sub a0, a2, a02690; RV64ZBB-NEXT: ret2691; RV64ZBB-NEXT: .LBB38_4:2692; RV64ZBB-NEXT: sltu a4, a0, a22693; RV64ZBB-NEXT: sub a1, a1, a32694; RV64ZBB-NEXT: sub a1, a1, a42695; RV64ZBB-NEXT: sub a0, a0, a22696; RV64ZBB-NEXT: ret2697 %cmp = icmp slt i128 %a, %b2698 %ab = select i1 %cmp, i128 %a, i128 %b2699 %ba = select i1 %cmp, i128 %b, i128 %a2700 %sub = sub i128 %ba, %ab2701 ret i128 %sub2702}2703 2704