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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=NOZBB,RV32I3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=NOZBB,RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=ZBB,RV32ZBB5; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=ZBB,RV64ZBB6 7;8; trunc(nabs(sub(zext(a),zext(b)))) -> nabds(a,b)9;10 11define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {12; RV32I-LABEL: abd_ext_i8:13; RV32I: # %bb.0:14; RV32I-NEXT: zext.b a1, a115; RV32I-NEXT: zext.b a0, a016; RV32I-NEXT: sub a0, a0, a117; RV32I-NEXT: srai a1, a0, 3118; RV32I-NEXT: xor a0, a0, a119; RV32I-NEXT: sub a0, a1, a020; RV32I-NEXT: ret21;22; RV64I-LABEL: abd_ext_i8:23; RV64I: # %bb.0:24; RV64I-NEXT: zext.b a0, a025; RV64I-NEXT: zext.b a1, a126; RV64I-NEXT: sub a0, a0, a127; RV64I-NEXT: srai a1, a0, 6328; RV64I-NEXT: xor a0, a0, a129; RV64I-NEXT: sub a0, a1, a030; RV64I-NEXT: ret31;32; RV32ZBB-LABEL: abd_ext_i8:33; RV32ZBB: # %bb.0:34; RV32ZBB-NEXT: zext.b a1, a135; RV32ZBB-NEXT: zext.b a0, a036; RV32ZBB-NEXT: maxu a2, a0, a137; RV32ZBB-NEXT: minu a0, a0, a138; RV32ZBB-NEXT: sub a0, a0, a239; RV32ZBB-NEXT: ret40;41; RV64ZBB-LABEL: abd_ext_i8:42; RV64ZBB: # %bb.0:43; RV64ZBB-NEXT: zext.b a0, a044; RV64ZBB-NEXT: zext.b a1, a145; RV64ZBB-NEXT: sub a0, a0, a146; RV64ZBB-NEXT: neg a1, a047; RV64ZBB-NEXT: min a0, a0, a148; RV64ZBB-NEXT: ret49 %aext = zext i8 %a to i6450 %bext = zext i8 %b to i6451 %sub = sub i64 %aext, %bext52 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)53 %nabs = sub i64 0, %abs54 %trunc = trunc i64 %nabs to i855 ret i8 %trunc56}57 58define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {59; RV32I-LABEL: abd_ext_i8_i16:60; RV32I: # %bb.0:61; RV32I-NEXT: slli a1, a1, 1662; RV32I-NEXT: srli a1, a1, 1663; RV32I-NEXT: zext.b a0, a064; RV32I-NEXT: sub a0, a0, a165; RV32I-NEXT: srai a1, a0, 3166; RV32I-NEXT: xor a0, a0, a167; RV32I-NEXT: sub a0, a1, a068; RV32I-NEXT: ret69;70; RV64I-LABEL: abd_ext_i8_i16:71; RV64I: # %bb.0:72; RV64I-NEXT: zext.b a0, a073; RV64I-NEXT: slli a1, a1, 4874; RV64I-NEXT: srli a1, a1, 4875; RV64I-NEXT: sub a0, a0, a176; RV64I-NEXT: srai a1, a0, 6377; RV64I-NEXT: xor a0, a0, a178; RV64I-NEXT: sub a0, a1, a079; RV64I-NEXT: ret80;81; RV32ZBB-LABEL: abd_ext_i8_i16:82; RV32ZBB: # %bb.0:83; RV32ZBB-NEXT: zext.h a1, a184; RV32ZBB-NEXT: zext.b a0, a085; RV32ZBB-NEXT: maxu a2, a0, a186; RV32ZBB-NEXT: minu a0, a0, a187; RV32ZBB-NEXT: sub a0, a0, a288; RV32ZBB-NEXT: ret89;90; RV64ZBB-LABEL: abd_ext_i8_i16:91; RV64ZBB: # %bb.0:92; RV64ZBB-NEXT: zext.b a0, a093; RV64ZBB-NEXT: zext.h a1, a194; RV64ZBB-NEXT: sub a0, a0, a195; RV64ZBB-NEXT: neg a1, a096; RV64ZBB-NEXT: min a0, a0, a197; RV64ZBB-NEXT: ret98 %aext = zext i8 %a to i6499 %bext = zext i16 %b to i64100 %sub = sub i64 %aext, %bext101 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)102 %nabs = sub i64 0, %abs103 %trunc = trunc i64 %nabs to i8104 ret i8 %trunc105}106 107define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {108; RV32I-LABEL: abd_ext_i8_undef:109; RV32I: # %bb.0:110; RV32I-NEXT: zext.b a1, a1111; RV32I-NEXT: zext.b a0, a0112; RV32I-NEXT: sub a0, a0, a1113; RV32I-NEXT: srai a1, a0, 31114; RV32I-NEXT: xor a0, a0, a1115; RV32I-NEXT: sub a0, a1, a0116; RV32I-NEXT: ret117;118; RV64I-LABEL: abd_ext_i8_undef:119; RV64I: # %bb.0:120; RV64I-NEXT: zext.b a0, a0121; RV64I-NEXT: zext.b a1, a1122; RV64I-NEXT: sub a0, a0, a1123; RV64I-NEXT: srai a1, a0, 63124; RV64I-NEXT: xor a0, a0, a1125; RV64I-NEXT: sub a0, a1, a0126; RV64I-NEXT: ret127;128; RV32ZBB-LABEL: abd_ext_i8_undef:129; RV32ZBB: # %bb.0:130; RV32ZBB-NEXT: zext.b a1, a1131; RV32ZBB-NEXT: zext.b a0, a0132; RV32ZBB-NEXT: maxu a2, a0, a1133; RV32ZBB-NEXT: minu a0, a0, a1134; RV32ZBB-NEXT: sub a0, a0, a2135; RV32ZBB-NEXT: ret136;137; RV64ZBB-LABEL: abd_ext_i8_undef:138; RV64ZBB: # %bb.0:139; RV64ZBB-NEXT: zext.b a0, a0140; RV64ZBB-NEXT: zext.b a1, a1141; RV64ZBB-NEXT: sub a0, a0, a1142; RV64ZBB-NEXT: neg a1, a0143; RV64ZBB-NEXT: min a0, a0, a1144; RV64ZBB-NEXT: ret145 %aext = zext i8 %a to i64146 %bext = zext i8 %b to i64147 %sub = sub i64 %aext, %bext148 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)149 %nabs = sub i64 0, %abs150 %trunc = trunc i64 %nabs to i8151 ret i8 %trunc152}153 154define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {155; RV32I-LABEL: abd_ext_i16:156; RV32I: # %bb.0:157; RV32I-NEXT: lui a2, 16158; RV32I-NEXT: addi a2, a2, -1159; RV32I-NEXT: and a1, a1, a2160; RV32I-NEXT: and a0, a0, a2161; RV32I-NEXT: sub a0, a0, a1162; RV32I-NEXT: srai a1, a0, 31163; RV32I-NEXT: xor a0, a0, a1164; RV32I-NEXT: sub a0, a1, a0165; RV32I-NEXT: ret166;167; RV64I-LABEL: abd_ext_i16:168; RV64I: # %bb.0:169; RV64I-NEXT: lui a2, 16170; RV64I-NEXT: addi a2, a2, -1171; RV64I-NEXT: and a0, a0, a2172; RV64I-NEXT: and a1, a1, a2173; RV64I-NEXT: sub a0, a0, a1174; RV64I-NEXT: srai a1, a0, 63175; RV64I-NEXT: xor a0, a0, a1176; RV64I-NEXT: sub a0, a1, a0177; RV64I-NEXT: ret178;179; RV32ZBB-LABEL: abd_ext_i16:180; RV32ZBB: # %bb.0:181; RV32ZBB-NEXT: zext.h a1, a1182; RV32ZBB-NEXT: zext.h a0, a0183; RV32ZBB-NEXT: maxu a2, a0, a1184; RV32ZBB-NEXT: minu a0, a0, a1185; RV32ZBB-NEXT: sub a0, a0, a2186; RV32ZBB-NEXT: ret187;188; RV64ZBB-LABEL: abd_ext_i16:189; RV64ZBB: # %bb.0:190; RV64ZBB-NEXT: zext.h a0, a0191; RV64ZBB-NEXT: zext.h a1, a1192; RV64ZBB-NEXT: sub a0, a0, a1193; RV64ZBB-NEXT: neg a1, a0194; RV64ZBB-NEXT: min a0, a0, a1195; RV64ZBB-NEXT: ret196 %aext = zext i16 %a to i64197 %bext = zext i16 %b to i64198 %sub = sub i64 %aext, %bext199 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)200 %nabs = sub i64 0, %abs201 %trunc = trunc i64 %nabs to i16202 ret i16 %trunc203}204 205define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {206; RV32I-LABEL: abd_ext_i16_i32:207; RV32I: # %bb.0:208; RV32I-NEXT: slli a0, a0, 16209; RV32I-NEXT: srli a0, a0, 16210; RV32I-NEXT: bltu a1, a0, .LBB4_2211; RV32I-NEXT: # %bb.1:212; RV32I-NEXT: sub a0, a1, a0213; RV32I-NEXT: neg a0, a0214; RV32I-NEXT: ret215; RV32I-NEXT: .LBB4_2:216; RV32I-NEXT: sub a0, a0, a1217; RV32I-NEXT: neg a0, a0218; RV32I-NEXT: ret219;220; RV64I-LABEL: abd_ext_i16_i32:221; RV64I: # %bb.0:222; RV64I-NEXT: slli a0, a0, 48223; RV64I-NEXT: slli a1, a1, 32224; RV64I-NEXT: srli a0, a0, 48225; RV64I-NEXT: srli a1, a1, 32226; RV64I-NEXT: sub a0, a0, a1227; RV64I-NEXT: srai a1, a0, 63228; RV64I-NEXT: xor a0, a0, a1229; RV64I-NEXT: sub a0, a1, a0230; RV64I-NEXT: ret231;232; RV32ZBB-LABEL: abd_ext_i16_i32:233; RV32ZBB: # %bb.0:234; RV32ZBB-NEXT: zext.h a0, a0235; RV32ZBB-NEXT: maxu a2, a0, a1236; RV32ZBB-NEXT: minu a0, a0, a1237; RV32ZBB-NEXT: sub a0, a0, a2238; RV32ZBB-NEXT: ret239;240; RV64ZBB-LABEL: abd_ext_i16_i32:241; RV64ZBB: # %bb.0:242; RV64ZBB-NEXT: zext.h a0, a0243; RV64ZBB-NEXT: slli a1, a1, 32244; RV64ZBB-NEXT: srli a1, a1, 32245; RV64ZBB-NEXT: sub a0, a0, a1246; RV64ZBB-NEXT: neg a1, a0247; RV64ZBB-NEXT: min a0, a0, a1248; RV64ZBB-NEXT: ret249 %aext = zext i16 %a to i64250 %bext = zext i32 %b to i64251 %sub = sub i64 %aext, %bext252 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)253 %nabs = sub i64 0, %abs254 %trunc = trunc i64 %nabs to i16255 ret i16 %trunc256}257 258define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {259; RV32I-LABEL: abd_ext_i16_undef:260; RV32I: # %bb.0:261; RV32I-NEXT: lui a2, 16262; RV32I-NEXT: addi a2, a2, -1263; RV32I-NEXT: and a1, a1, a2264; RV32I-NEXT: and a0, a0, a2265; RV32I-NEXT: sub a0, a0, a1266; RV32I-NEXT: srai a1, a0, 31267; RV32I-NEXT: xor a0, a0, a1268; RV32I-NEXT: sub a0, a1, a0269; RV32I-NEXT: ret270;271; RV64I-LABEL: abd_ext_i16_undef:272; RV64I: # %bb.0:273; RV64I-NEXT: lui a2, 16274; RV64I-NEXT: addi a2, a2, -1275; RV64I-NEXT: and a0, a0, a2276; RV64I-NEXT: and a1, a1, a2277; RV64I-NEXT: sub a0, a0, a1278; RV64I-NEXT: srai a1, a0, 63279; RV64I-NEXT: xor a0, a0, a1280; RV64I-NEXT: sub a0, a1, a0281; RV64I-NEXT: ret282;283; RV32ZBB-LABEL: abd_ext_i16_undef:284; RV32ZBB: # %bb.0:285; RV32ZBB-NEXT: zext.h a1, a1286; RV32ZBB-NEXT: zext.h a0, a0287; RV32ZBB-NEXT: maxu a2, a0, a1288; RV32ZBB-NEXT: minu a0, a0, a1289; RV32ZBB-NEXT: sub a0, a0, a2290; RV32ZBB-NEXT: ret291;292; RV64ZBB-LABEL: abd_ext_i16_undef:293; RV64ZBB: # %bb.0:294; RV64ZBB-NEXT: zext.h a0, a0295; RV64ZBB-NEXT: zext.h a1, a1296; RV64ZBB-NEXT: sub a0, a0, a1297; RV64ZBB-NEXT: neg a1, a0298; RV64ZBB-NEXT: min a0, a0, a1299; RV64ZBB-NEXT: ret300 %aext = zext i16 %a to i64301 %bext = zext i16 %b to i64302 %sub = sub i64 %aext, %bext303 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)304 %nabs = sub i64 0, %abs305 %trunc = trunc i64 %nabs to i16306 ret i16 %trunc307}308 309define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {310; RV32I-LABEL: abd_ext_i32:311; RV32I: # %bb.0:312; RV32I-NEXT: bltu a1, a0, .LBB6_2313; RV32I-NEXT: # %bb.1:314; RV32I-NEXT: sub a0, a1, a0315; RV32I-NEXT: neg a0, a0316; RV32I-NEXT: ret317; RV32I-NEXT: .LBB6_2:318; RV32I-NEXT: sub a0, a0, a1319; RV32I-NEXT: neg a0, a0320; RV32I-NEXT: ret321;322; RV64I-LABEL: abd_ext_i32:323; RV64I: # %bb.0:324; RV64I-NEXT: slli a0, a0, 32325; RV64I-NEXT: slli a1, a1, 32326; RV64I-NEXT: srli a0, a0, 32327; RV64I-NEXT: srli a1, a1, 32328; RV64I-NEXT: sub a0, a0, a1329; RV64I-NEXT: srai a1, a0, 63330; RV64I-NEXT: xor a0, a0, a1331; RV64I-NEXT: sub a0, a1, a0332; RV64I-NEXT: ret333;334; RV32ZBB-LABEL: abd_ext_i32:335; RV32ZBB: # %bb.0:336; RV32ZBB-NEXT: maxu a2, a0, a1337; RV32ZBB-NEXT: minu a0, a0, a1338; RV32ZBB-NEXT: sub a0, a0, a2339; RV32ZBB-NEXT: ret340;341; RV64ZBB-LABEL: abd_ext_i32:342; RV64ZBB: # %bb.0:343; RV64ZBB-NEXT: slli a0, a0, 32344; RV64ZBB-NEXT: slli a1, a1, 32345; RV64ZBB-NEXT: srli a0, a0, 32346; RV64ZBB-NEXT: srli a1, a1, 32347; RV64ZBB-NEXT: sub a0, a0, a1348; RV64ZBB-NEXT: neg a1, a0349; RV64ZBB-NEXT: min a0, a0, a1350; RV64ZBB-NEXT: ret351 %aext = zext i32 %a to i64352 %bext = zext i32 %b to i64353 %sub = sub i64 %aext, %bext354 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)355 %nabs = sub i64 0, %abs356 %trunc = trunc i64 %nabs to i32357 ret i32 %trunc358}359 360define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {361; RV32I-LABEL: abd_ext_i32_i16:362; RV32I: # %bb.0:363; RV32I-NEXT: slli a1, a1, 16364; RV32I-NEXT: srli a1, a1, 16365; RV32I-NEXT: bltu a1, a0, .LBB7_2366; RV32I-NEXT: # %bb.1:367; RV32I-NEXT: sub a0, a1, a0368; RV32I-NEXT: neg a0, a0369; RV32I-NEXT: ret370; RV32I-NEXT: .LBB7_2:371; RV32I-NEXT: sub a0, a0, a1372; RV32I-NEXT: neg a0, a0373; RV32I-NEXT: ret374;375; RV64I-LABEL: abd_ext_i32_i16:376; RV64I: # %bb.0:377; RV64I-NEXT: slli a0, a0, 32378; RV64I-NEXT: slli a1, a1, 48379; RV64I-NEXT: srli a0, a0, 32380; RV64I-NEXT: srli a1, a1, 48381; RV64I-NEXT: sub a0, a0, a1382; RV64I-NEXT: srai a1, a0, 63383; RV64I-NEXT: xor a0, a0, a1384; RV64I-NEXT: sub a0, a1, a0385; RV64I-NEXT: ret386;387; RV32ZBB-LABEL: abd_ext_i32_i16:388; RV32ZBB: # %bb.0:389; RV32ZBB-NEXT: zext.h a1, a1390; RV32ZBB-NEXT: maxu a2, a0, a1391; RV32ZBB-NEXT: minu a0, a0, a1392; RV32ZBB-NEXT: sub a0, a0, a2393; RV32ZBB-NEXT: ret394;395; RV64ZBB-LABEL: abd_ext_i32_i16:396; RV64ZBB: # %bb.0:397; RV64ZBB-NEXT: slli a0, a0, 32398; RV64ZBB-NEXT: srli a0, a0, 32399; RV64ZBB-NEXT: zext.h a1, a1400; RV64ZBB-NEXT: sub a0, a0, a1401; RV64ZBB-NEXT: neg a1, a0402; RV64ZBB-NEXT: min a0, a0, a1403; RV64ZBB-NEXT: ret404 %aext = zext i32 %a to i64405 %bext = zext i16 %b to i64406 %sub = sub i64 %aext, %bext407 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)408 %nabs = sub i64 0, %abs409 %trunc = trunc i64 %nabs to i32410 ret i32 %trunc411}412 413define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {414; RV32I-LABEL: abd_ext_i32_undef:415; RV32I: # %bb.0:416; RV32I-NEXT: bltu a1, a0, .LBB8_2417; RV32I-NEXT: # %bb.1:418; RV32I-NEXT: sub a0, a1, a0419; RV32I-NEXT: neg a0, a0420; RV32I-NEXT: ret421; RV32I-NEXT: .LBB8_2:422; RV32I-NEXT: sub a0, a0, a1423; RV32I-NEXT: neg a0, a0424; RV32I-NEXT: ret425;426; RV64I-LABEL: abd_ext_i32_undef:427; RV64I: # %bb.0:428; RV64I-NEXT: slli a0, a0, 32429; RV64I-NEXT: slli a1, a1, 32430; RV64I-NEXT: srli a0, a0, 32431; RV64I-NEXT: srli a1, a1, 32432; RV64I-NEXT: sub a0, a0, a1433; RV64I-NEXT: srai a1, a0, 63434; RV64I-NEXT: xor a0, a0, a1435; RV64I-NEXT: sub a0, a1, a0436; RV64I-NEXT: ret437;438; RV32ZBB-LABEL: abd_ext_i32_undef:439; RV32ZBB: # %bb.0:440; RV32ZBB-NEXT: maxu a2, a0, a1441; RV32ZBB-NEXT: minu a0, a0, a1442; RV32ZBB-NEXT: sub a0, a0, a2443; RV32ZBB-NEXT: ret444;445; RV64ZBB-LABEL: abd_ext_i32_undef:446; RV64ZBB: # %bb.0:447; RV64ZBB-NEXT: slli a0, a0, 32448; RV64ZBB-NEXT: slli a1, a1, 32449; RV64ZBB-NEXT: srli a0, a0, 32450; RV64ZBB-NEXT: srli a1, a1, 32451; RV64ZBB-NEXT: sub a0, a0, a1452; RV64ZBB-NEXT: neg a1, a0453; RV64ZBB-NEXT: min a0, a0, a1454; RV64ZBB-NEXT: ret455 %aext = zext i32 %a to i64456 %bext = zext i32 %b to i64457 %sub = sub i64 %aext, %bext458 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)459 %nabs = sub i64 0, %abs460 %trunc = trunc i64 %nabs to i32461 ret i32 %trunc462}463 464define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {465; RV32I-LABEL: abd_ext_i64:466; RV32I: # %bb.0:467; RV32I-NEXT: sltu a4, a0, a2468; RV32I-NEXT: sub a3, a1, a3469; RV32I-NEXT: sub a3, a3, a4470; RV32I-NEXT: sub a2, a0, a2471; RV32I-NEXT: beq a3, a1, .LBB9_2472; RV32I-NEXT: # %bb.1:473; RV32I-NEXT: sltu a0, a1, a3474; RV32I-NEXT: j .LBB9_3475; RV32I-NEXT: .LBB9_2:476; RV32I-NEXT: sltu a0, a0, a2477; RV32I-NEXT: .LBB9_3:478; RV32I-NEXT: neg a1, a0479; RV32I-NEXT: xor a2, a2, a1480; RV32I-NEXT: xor a3, a3, a1481; RV32I-NEXT: sltu a1, a2, a1482; RV32I-NEXT: add a3, a3, a0483; RV32I-NEXT: add a0, a2, a0484; RV32I-NEXT: sub a3, a3, a1485; RV32I-NEXT: snez a1, a0486; RV32I-NEXT: add a1, a3, a1487; RV32I-NEXT: neg a1, a1488; RV32I-NEXT: neg a0, a0489; RV32I-NEXT: ret490;491; RV64I-LABEL: abd_ext_i64:492; RV64I: # %bb.0:493; RV64I-NEXT: bltu a1, a0, .LBB9_2494; RV64I-NEXT: # %bb.1:495; RV64I-NEXT: sub a0, a1, a0496; RV64I-NEXT: neg a0, a0497; RV64I-NEXT: ret498; RV64I-NEXT: .LBB9_2:499; RV64I-NEXT: sub a0, a0, a1500; RV64I-NEXT: neg a0, a0501; RV64I-NEXT: ret502;503; RV32ZBB-LABEL: abd_ext_i64:504; RV32ZBB: # %bb.0:505; RV32ZBB-NEXT: sltu a4, a0, a2506; RV32ZBB-NEXT: sub a3, a1, a3507; RV32ZBB-NEXT: sub a3, a3, a4508; RV32ZBB-NEXT: sub a2, a0, a2509; RV32ZBB-NEXT: beq a3, a1, .LBB9_2510; RV32ZBB-NEXT: # %bb.1:511; RV32ZBB-NEXT: sltu a0, a1, a3512; RV32ZBB-NEXT: j .LBB9_3513; RV32ZBB-NEXT: .LBB9_2:514; RV32ZBB-NEXT: sltu a0, a0, a2515; RV32ZBB-NEXT: .LBB9_3:516; RV32ZBB-NEXT: neg a1, a0517; RV32ZBB-NEXT: xor a2, a2, a1518; RV32ZBB-NEXT: xor a3, a3, a1519; RV32ZBB-NEXT: sltu a1, a2, a1520; RV32ZBB-NEXT: add a3, a3, a0521; RV32ZBB-NEXT: add a0, a2, a0522; RV32ZBB-NEXT: sub a3, a3, a1523; RV32ZBB-NEXT: snez a1, a0524; RV32ZBB-NEXT: add a1, a3, a1525; RV32ZBB-NEXT: neg a1, a1526; RV32ZBB-NEXT: neg a0, a0527; RV32ZBB-NEXT: ret528;529; RV64ZBB-LABEL: abd_ext_i64:530; RV64ZBB: # %bb.0:531; RV64ZBB-NEXT: maxu a2, a0, a1532; RV64ZBB-NEXT: minu a0, a0, a1533; RV64ZBB-NEXT: sub a0, a0, a2534; RV64ZBB-NEXT: ret535 %aext = zext i64 %a to i128536 %bext = zext i64 %b to i128537 %sub = sub i128 %aext, %bext538 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)539 %nabs = sub i128 0, %abs540 %trunc = trunc i128 %nabs to i64541 ret i64 %trunc542}543 544define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {545; RV32I-LABEL: abd_ext_i64_undef:546; RV32I: # %bb.0:547; RV32I-NEXT: sltu a4, a0, a2548; RV32I-NEXT: sub a3, a1, a3549; RV32I-NEXT: sub a3, a3, a4550; RV32I-NEXT: sub a2, a0, a2551; RV32I-NEXT: beq a3, a1, .LBB10_2552; RV32I-NEXT: # %bb.1:553; RV32I-NEXT: sltu a0, a1, a3554; RV32I-NEXT: j .LBB10_3555; RV32I-NEXT: .LBB10_2:556; RV32I-NEXT: sltu a0, a0, a2557; RV32I-NEXT: .LBB10_3:558; RV32I-NEXT: neg a1, a0559; RV32I-NEXT: xor a2, a2, a1560; RV32I-NEXT: xor a3, a3, a1561; RV32I-NEXT: sltu a1, a2, a1562; RV32I-NEXT: add a3, a3, a0563; RV32I-NEXT: add a0, a2, a0564; RV32I-NEXT: sub a3, a3, a1565; RV32I-NEXT: snez a1, a0566; RV32I-NEXT: add a1, a3, a1567; RV32I-NEXT: neg a1, a1568; RV32I-NEXT: neg a0, a0569; RV32I-NEXT: ret570;571; RV64I-LABEL: abd_ext_i64_undef:572; RV64I: # %bb.0:573; RV64I-NEXT: bltu a1, a0, .LBB10_2574; RV64I-NEXT: # %bb.1:575; RV64I-NEXT: sub a0, a1, a0576; RV64I-NEXT: neg a0, a0577; RV64I-NEXT: ret578; RV64I-NEXT: .LBB10_2:579; RV64I-NEXT: sub a0, a0, a1580; RV64I-NEXT: neg a0, a0581; RV64I-NEXT: ret582;583; RV32ZBB-LABEL: abd_ext_i64_undef:584; RV32ZBB: # %bb.0:585; RV32ZBB-NEXT: sltu a4, a0, a2586; RV32ZBB-NEXT: sub a3, a1, a3587; RV32ZBB-NEXT: sub a3, a3, a4588; RV32ZBB-NEXT: sub a2, a0, a2589; RV32ZBB-NEXT: beq a3, a1, .LBB10_2590; RV32ZBB-NEXT: # %bb.1:591; RV32ZBB-NEXT: sltu a0, a1, a3592; RV32ZBB-NEXT: j .LBB10_3593; RV32ZBB-NEXT: .LBB10_2:594; RV32ZBB-NEXT: sltu a0, a0, a2595; RV32ZBB-NEXT: .LBB10_3:596; RV32ZBB-NEXT: neg a1, a0597; RV32ZBB-NEXT: xor a2, a2, a1598; RV32ZBB-NEXT: xor a3, a3, a1599; RV32ZBB-NEXT: sltu a1, a2, a1600; RV32ZBB-NEXT: add a3, a3, a0601; RV32ZBB-NEXT: add a0, a2, a0602; RV32ZBB-NEXT: sub a3, a3, a1603; RV32ZBB-NEXT: snez a1, a0604; RV32ZBB-NEXT: add a1, a3, a1605; RV32ZBB-NEXT: neg a1, a1606; RV32ZBB-NEXT: neg a0, a0607; RV32ZBB-NEXT: ret608;609; RV64ZBB-LABEL: abd_ext_i64_undef:610; RV64ZBB: # %bb.0:611; RV64ZBB-NEXT: maxu a2, a0, a1612; RV64ZBB-NEXT: minu a0, a0, a1613; RV64ZBB-NEXT: sub a0, a0, a2614; RV64ZBB-NEXT: ret615 %aext = zext i64 %a to i128616 %bext = zext i64 %b to i128617 %sub = sub i128 %aext, %bext618 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)619 %nabs = sub i128 0, %abs620 %trunc = trunc i128 %nabs to i64621 ret i64 %trunc622}623 624define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {625; RV32I-LABEL: abd_ext_i128:626; RV32I: # %bb.0:627; RV32I-NEXT: lw a5, 0(a2)628; RV32I-NEXT: lw a7, 4(a2)629; RV32I-NEXT: lw a3, 8(a2)630; RV32I-NEXT: lw t1, 12(a2)631; RV32I-NEXT: lw a4, 8(a1)632; RV32I-NEXT: lw a6, 12(a1)633; RV32I-NEXT: lw a2, 0(a1)634; RV32I-NEXT: lw t0, 4(a1)635; RV32I-NEXT: sltu a1, a4, a3636; RV32I-NEXT: sub t1, a6, t1637; RV32I-NEXT: sltu t2, a2, a5638; RV32I-NEXT: sub a1, t1, a1639; RV32I-NEXT: mv t1, t2640; RV32I-NEXT: beq t0, a7, .LBB11_2641; RV32I-NEXT: # %bb.1:642; RV32I-NEXT: sltu t1, t0, a7643; RV32I-NEXT: .LBB11_2:644; RV32I-NEXT: sub a3, a4, a3645; RV32I-NEXT: sltu t3, a3, t1646; RV32I-NEXT: sub a1, a1, t3647; RV32I-NEXT: sub a3, a3, t1648; RV32I-NEXT: beq a1, a6, .LBB11_4649; RV32I-NEXT: # %bb.3:650; RV32I-NEXT: sltu t1, a6, a1651; RV32I-NEXT: j .LBB11_5652; RV32I-NEXT: .LBB11_4:653; RV32I-NEXT: sltu t1, a4, a3654; RV32I-NEXT: .LBB11_5:655; RV32I-NEXT: sub a7, t0, a7656; RV32I-NEXT: sub a7, a7, t2657; RV32I-NEXT: sub a5, a2, a5658; RV32I-NEXT: beq a7, t0, .LBB11_7659; RV32I-NEXT: # %bb.6:660; RV32I-NEXT: sltu a2, t0, a7661; RV32I-NEXT: j .LBB11_8662; RV32I-NEXT: .LBB11_7:663; RV32I-NEXT: sltu a2, a2, a5664; RV32I-NEXT: .LBB11_8:665; RV32I-NEXT: xor a6, a1, a6666; RV32I-NEXT: xor a4, a3, a4667; RV32I-NEXT: or a4, a4, a6668; RV32I-NEXT: beqz a4, .LBB11_10669; RV32I-NEXT: # %bb.9:670; RV32I-NEXT: mv a2, t1671; RV32I-NEXT: .LBB11_10:672; RV32I-NEXT: neg a4, a2673; RV32I-NEXT: xor t0, a5, a4674; RV32I-NEXT: xor t3, a7, a4675; RV32I-NEXT: sltu a5, t0, a4676; RV32I-NEXT: add a6, t3, a2677; RV32I-NEXT: add t0, t0, a2678; RV32I-NEXT: sub t1, a6, a5679; RV32I-NEXT: snez a6, t1680; RV32I-NEXT: snez t2, t0681; RV32I-NEXT: or a6, t2, a6682; RV32I-NEXT: beqz a7, .LBB11_12683; RV32I-NEXT: # %bb.11:684; RV32I-NEXT: sltu a5, t3, a4685; RV32I-NEXT: .LBB11_12:686; RV32I-NEXT: xor a3, a3, a4687; RV32I-NEXT: xor a1, a1, a4688; RV32I-NEXT: add t1, t1, t2689; RV32I-NEXT: neg a7, t0690; RV32I-NEXT: add t0, a3, a2691; RV32I-NEXT: sltu a3, a3, a4692; RV32I-NEXT: add a1, a1, a2693; RV32I-NEXT: neg a2, t1694; RV32I-NEXT: sub a4, t0, a5695; RV32I-NEXT: sub a1, a1, a3696; RV32I-NEXT: sltu a3, t0, a5697; RV32I-NEXT: neg a5, a4698; RV32I-NEXT: sub a1, a1, a3699; RV32I-NEXT: snez a3, a4700; RV32I-NEXT: sltu a4, a5, a6701; RV32I-NEXT: add a1, a1, a3702; RV32I-NEXT: sub a3, a5, a6703; RV32I-NEXT: neg a1, a1704; RV32I-NEXT: sub a1, a1, a4705; RV32I-NEXT: sw a7, 0(a0)706; RV32I-NEXT: sw a2, 4(a0)707; RV32I-NEXT: sw a3, 8(a0)708; RV32I-NEXT: sw a1, 12(a0)709; RV32I-NEXT: ret710;711; RV64I-LABEL: abd_ext_i128:712; RV64I: # %bb.0:713; RV64I-NEXT: sltu a4, a0, a2714; RV64I-NEXT: sub a3, a1, a3715; RV64I-NEXT: sub a3, a3, a4716; RV64I-NEXT: sub a2, a0, a2717; RV64I-NEXT: beq a3, a1, .LBB11_2718; RV64I-NEXT: # %bb.1:719; RV64I-NEXT: sltu a0, a1, a3720; RV64I-NEXT: j .LBB11_3721; RV64I-NEXT: .LBB11_2:722; RV64I-NEXT: sltu a0, a0, a2723; RV64I-NEXT: .LBB11_3:724; RV64I-NEXT: neg a1, a0725; RV64I-NEXT: xor a2, a2, a1726; RV64I-NEXT: xor a3, a3, a1727; RV64I-NEXT: sltu a1, a2, a1728; RV64I-NEXT: add a3, a3, a0729; RV64I-NEXT: add a0, a2, a0730; RV64I-NEXT: sub a3, a3, a1731; RV64I-NEXT: snez a1, a0732; RV64I-NEXT: add a1, a3, a1733; RV64I-NEXT: neg a1, a1734; RV64I-NEXT: neg a0, a0735; RV64I-NEXT: ret736;737; RV32ZBB-LABEL: abd_ext_i128:738; RV32ZBB: # %bb.0:739; RV32ZBB-NEXT: lw a5, 0(a2)740; RV32ZBB-NEXT: lw a7, 4(a2)741; RV32ZBB-NEXT: lw a3, 8(a2)742; RV32ZBB-NEXT: lw t1, 12(a2)743; RV32ZBB-NEXT: lw a4, 8(a1)744; RV32ZBB-NEXT: lw a6, 12(a1)745; RV32ZBB-NEXT: lw a2, 0(a1)746; RV32ZBB-NEXT: lw t0, 4(a1)747; RV32ZBB-NEXT: sltu a1, a4, a3748; RV32ZBB-NEXT: sub t1, a6, t1749; RV32ZBB-NEXT: sltu t2, a2, a5750; RV32ZBB-NEXT: sub a1, t1, a1751; RV32ZBB-NEXT: mv t1, t2752; RV32ZBB-NEXT: beq t0, a7, .LBB11_2753; RV32ZBB-NEXT: # %bb.1:754; RV32ZBB-NEXT: sltu t1, t0, a7755; RV32ZBB-NEXT: .LBB11_2:756; RV32ZBB-NEXT: sub a3, a4, a3757; RV32ZBB-NEXT: sltu t3, a3, t1758; RV32ZBB-NEXT: sub a1, a1, t3759; RV32ZBB-NEXT: sub a3, a3, t1760; RV32ZBB-NEXT: beq a1, a6, .LBB11_4761; RV32ZBB-NEXT: # %bb.3:762; RV32ZBB-NEXT: sltu t1, a6, a1763; RV32ZBB-NEXT: j .LBB11_5764; RV32ZBB-NEXT: .LBB11_4:765; RV32ZBB-NEXT: sltu t1, a4, a3766; RV32ZBB-NEXT: .LBB11_5:767; RV32ZBB-NEXT: sub a7, t0, a7768; RV32ZBB-NEXT: sub a7, a7, t2769; RV32ZBB-NEXT: sub a5, a2, a5770; RV32ZBB-NEXT: beq a7, t0, .LBB11_7771; RV32ZBB-NEXT: # %bb.6:772; RV32ZBB-NEXT: sltu a2, t0, a7773; RV32ZBB-NEXT: j .LBB11_8774; RV32ZBB-NEXT: .LBB11_7:775; RV32ZBB-NEXT: sltu a2, a2, a5776; RV32ZBB-NEXT: .LBB11_8:777; RV32ZBB-NEXT: xor a6, a1, a6778; RV32ZBB-NEXT: xor a4, a3, a4779; RV32ZBB-NEXT: or a4, a4, a6780; RV32ZBB-NEXT: beqz a4, .LBB11_10781; RV32ZBB-NEXT: # %bb.9:782; RV32ZBB-NEXT: mv a2, t1783; RV32ZBB-NEXT: .LBB11_10:784; RV32ZBB-NEXT: neg a4, a2785; RV32ZBB-NEXT: xor t0, a5, a4786; RV32ZBB-NEXT: xor t3, a7, a4787; RV32ZBB-NEXT: sltu a5, t0, a4788; RV32ZBB-NEXT: add a6, t3, a2789; RV32ZBB-NEXT: add t0, t0, a2790; RV32ZBB-NEXT: sub t1, a6, a5791; RV32ZBB-NEXT: snez a6, t1792; RV32ZBB-NEXT: snez t2, t0793; RV32ZBB-NEXT: or a6, t2, a6794; RV32ZBB-NEXT: beqz a7, .LBB11_12795; RV32ZBB-NEXT: # %bb.11:796; RV32ZBB-NEXT: sltu a5, t3, a4797; RV32ZBB-NEXT: .LBB11_12:798; RV32ZBB-NEXT: xor a3, a3, a4799; RV32ZBB-NEXT: xor a1, a1, a4800; RV32ZBB-NEXT: add t1, t1, t2801; RV32ZBB-NEXT: neg a7, t0802; RV32ZBB-NEXT: add t0, a3, a2803; RV32ZBB-NEXT: sltu a3, a3, a4804; RV32ZBB-NEXT: add a1, a1, a2805; RV32ZBB-NEXT: neg a2, t1806; RV32ZBB-NEXT: sub a4, t0, a5807; RV32ZBB-NEXT: sub a1, a1, a3808; RV32ZBB-NEXT: sltu a3, t0, a5809; RV32ZBB-NEXT: neg a5, a4810; RV32ZBB-NEXT: sub a1, a1, a3811; RV32ZBB-NEXT: snez a3, a4812; RV32ZBB-NEXT: sltu a4, a5, a6813; RV32ZBB-NEXT: add a1, a1, a3814; RV32ZBB-NEXT: sub a3, a5, a6815; RV32ZBB-NEXT: neg a1, a1816; RV32ZBB-NEXT: sub a1, a1, a4817; RV32ZBB-NEXT: sw a7, 0(a0)818; RV32ZBB-NEXT: sw a2, 4(a0)819; RV32ZBB-NEXT: sw a3, 8(a0)820; RV32ZBB-NEXT: sw a1, 12(a0)821; RV32ZBB-NEXT: ret822;823; RV64ZBB-LABEL: abd_ext_i128:824; RV64ZBB: # %bb.0:825; RV64ZBB-NEXT: sltu a4, a0, a2826; RV64ZBB-NEXT: sub a3, a1, a3827; RV64ZBB-NEXT: sub a3, a3, a4828; RV64ZBB-NEXT: sub a2, a0, a2829; RV64ZBB-NEXT: beq a3, a1, .LBB11_2830; RV64ZBB-NEXT: # %bb.1:831; RV64ZBB-NEXT: sltu a0, a1, a3832; RV64ZBB-NEXT: j .LBB11_3833; RV64ZBB-NEXT: .LBB11_2:834; RV64ZBB-NEXT: sltu a0, a0, a2835; RV64ZBB-NEXT: .LBB11_3:836; RV64ZBB-NEXT: neg a1, a0837; RV64ZBB-NEXT: xor a2, a2, a1838; RV64ZBB-NEXT: xor a3, a3, a1839; RV64ZBB-NEXT: sltu a1, a2, a1840; RV64ZBB-NEXT: add a3, a3, a0841; RV64ZBB-NEXT: add a0, a2, a0842; RV64ZBB-NEXT: sub a3, a3, a1843; RV64ZBB-NEXT: snez a1, a0844; RV64ZBB-NEXT: add a1, a3, a1845; RV64ZBB-NEXT: neg a1, a1846; RV64ZBB-NEXT: neg a0, a0847; RV64ZBB-NEXT: ret848 %aext = zext i128 %a to i256849 %bext = zext i128 %b to i256850 %sub = sub i256 %aext, %bext851 %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)852 %nabs = sub i256 0, %abs853 %trunc = trunc i256 %nabs to i128854 ret i128 %trunc855}856 857define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {858; RV32I-LABEL: abd_ext_i128_undef:859; RV32I: # %bb.0:860; RV32I-NEXT: lw a5, 0(a2)861; RV32I-NEXT: lw a7, 4(a2)862; RV32I-NEXT: lw a3, 8(a2)863; RV32I-NEXT: lw t1, 12(a2)864; RV32I-NEXT: lw a4, 8(a1)865; RV32I-NEXT: lw a6, 12(a1)866; RV32I-NEXT: lw a2, 0(a1)867; RV32I-NEXT: lw t0, 4(a1)868; RV32I-NEXT: sltu a1, a4, a3869; RV32I-NEXT: sub t1, a6, t1870; RV32I-NEXT: sltu t2, a2, a5871; RV32I-NEXT: sub a1, t1, a1872; RV32I-NEXT: mv t1, t2873; RV32I-NEXT: beq t0, a7, .LBB12_2874; RV32I-NEXT: # %bb.1:875; RV32I-NEXT: sltu t1, t0, a7876; RV32I-NEXT: .LBB12_2:877; RV32I-NEXT: sub a3, a4, a3878; RV32I-NEXT: sltu t3, a3, t1879; RV32I-NEXT: sub a1, a1, t3880; RV32I-NEXT: sub a3, a3, t1881; RV32I-NEXT: beq a1, a6, .LBB12_4882; RV32I-NEXT: # %bb.3:883; RV32I-NEXT: sltu t1, a6, a1884; RV32I-NEXT: j .LBB12_5885; RV32I-NEXT: .LBB12_4:886; RV32I-NEXT: sltu t1, a4, a3887; RV32I-NEXT: .LBB12_5:888; RV32I-NEXT: sub a7, t0, a7889; RV32I-NEXT: sub a7, a7, t2890; RV32I-NEXT: sub a5, a2, a5891; RV32I-NEXT: beq a7, t0, .LBB12_7892; RV32I-NEXT: # %bb.6:893; RV32I-NEXT: sltu a2, t0, a7894; RV32I-NEXT: j .LBB12_8895; RV32I-NEXT: .LBB12_7:896; RV32I-NEXT: sltu a2, a2, a5897; RV32I-NEXT: .LBB12_8:898; RV32I-NEXT: xor a6, a1, a6899; RV32I-NEXT: xor a4, a3, a4900; RV32I-NEXT: or a4, a4, a6901; RV32I-NEXT: beqz a4, .LBB12_10902; RV32I-NEXT: # %bb.9:903; RV32I-NEXT: mv a2, t1904; RV32I-NEXT: .LBB12_10:905; RV32I-NEXT: neg a4, a2906; RV32I-NEXT: xor t0, a5, a4907; RV32I-NEXT: xor t3, a7, a4908; RV32I-NEXT: sltu a5, t0, a4909; RV32I-NEXT: add a6, t3, a2910; RV32I-NEXT: add t0, t0, a2911; RV32I-NEXT: sub t1, a6, a5912; RV32I-NEXT: snez a6, t1913; RV32I-NEXT: snez t2, t0914; RV32I-NEXT: or a6, t2, a6915; RV32I-NEXT: beqz a7, .LBB12_12916; RV32I-NEXT: # %bb.11:917; RV32I-NEXT: sltu a5, t3, a4918; RV32I-NEXT: .LBB12_12:919; RV32I-NEXT: xor a3, a3, a4920; RV32I-NEXT: xor a1, a1, a4921; RV32I-NEXT: add t1, t1, t2922; RV32I-NEXT: neg a7, t0923; RV32I-NEXT: add t0, a3, a2924; RV32I-NEXT: sltu a3, a3, a4925; RV32I-NEXT: add a1, a1, a2926; RV32I-NEXT: neg a2, t1927; RV32I-NEXT: sub a4, t0, a5928; RV32I-NEXT: sub a1, a1, a3929; RV32I-NEXT: sltu a3, t0, a5930; RV32I-NEXT: neg a5, a4931; RV32I-NEXT: sub a1, a1, a3932; RV32I-NEXT: snez a3, a4933; RV32I-NEXT: sltu a4, a5, a6934; RV32I-NEXT: add a1, a1, a3935; RV32I-NEXT: sub a3, a5, a6936; RV32I-NEXT: neg a1, a1937; RV32I-NEXT: sub a1, a1, a4938; RV32I-NEXT: sw a7, 0(a0)939; RV32I-NEXT: sw a2, 4(a0)940; RV32I-NEXT: sw a3, 8(a0)941; RV32I-NEXT: sw a1, 12(a0)942; RV32I-NEXT: ret943;944; RV64I-LABEL: abd_ext_i128_undef:945; RV64I: # %bb.0:946; RV64I-NEXT: sltu a4, a0, a2947; RV64I-NEXT: sub a3, a1, a3948; RV64I-NEXT: sub a3, a3, a4949; RV64I-NEXT: sub a2, a0, a2950; RV64I-NEXT: beq a3, a1, .LBB12_2951; RV64I-NEXT: # %bb.1:952; RV64I-NEXT: sltu a0, a1, a3953; RV64I-NEXT: j .LBB12_3954; RV64I-NEXT: .LBB12_2:955; RV64I-NEXT: sltu a0, a0, a2956; RV64I-NEXT: .LBB12_3:957; RV64I-NEXT: neg a1, a0958; RV64I-NEXT: xor a2, a2, a1959; RV64I-NEXT: xor a3, a3, a1960; RV64I-NEXT: sltu a1, a2, a1961; RV64I-NEXT: add a3, a3, a0962; RV64I-NEXT: add a0, a2, a0963; RV64I-NEXT: sub a3, a3, a1964; RV64I-NEXT: snez a1, a0965; RV64I-NEXT: add a1, a3, a1966; RV64I-NEXT: neg a1, a1967; RV64I-NEXT: neg a0, a0968; RV64I-NEXT: ret969;970; RV32ZBB-LABEL: abd_ext_i128_undef:971; RV32ZBB: # %bb.0:972; RV32ZBB-NEXT: lw a5, 0(a2)973; RV32ZBB-NEXT: lw a7, 4(a2)974; RV32ZBB-NEXT: lw a3, 8(a2)975; RV32ZBB-NEXT: lw t1, 12(a2)976; RV32ZBB-NEXT: lw a4, 8(a1)977; RV32ZBB-NEXT: lw a6, 12(a1)978; RV32ZBB-NEXT: lw a2, 0(a1)979; RV32ZBB-NEXT: lw t0, 4(a1)980; RV32ZBB-NEXT: sltu a1, a4, a3981; RV32ZBB-NEXT: sub t1, a6, t1982; RV32ZBB-NEXT: sltu t2, a2, a5983; RV32ZBB-NEXT: sub a1, t1, a1984; RV32ZBB-NEXT: mv t1, t2985; RV32ZBB-NEXT: beq t0, a7, .LBB12_2986; RV32ZBB-NEXT: # %bb.1:987; RV32ZBB-NEXT: sltu t1, t0, a7988; RV32ZBB-NEXT: .LBB12_2:989; RV32ZBB-NEXT: sub a3, a4, a3990; RV32ZBB-NEXT: sltu t3, a3, t1991; RV32ZBB-NEXT: sub a1, a1, t3992; RV32ZBB-NEXT: sub a3, a3, t1993; RV32ZBB-NEXT: beq a1, a6, .LBB12_4994; RV32ZBB-NEXT: # %bb.3:995; RV32ZBB-NEXT: sltu t1, a6, a1996; RV32ZBB-NEXT: j .LBB12_5997; RV32ZBB-NEXT: .LBB12_4:998; RV32ZBB-NEXT: sltu t1, a4, a3999; RV32ZBB-NEXT: .LBB12_5:1000; RV32ZBB-NEXT: sub a7, t0, a71001; RV32ZBB-NEXT: sub a7, a7, t21002; RV32ZBB-NEXT: sub a5, a2, a51003; RV32ZBB-NEXT: beq a7, t0, .LBB12_71004; RV32ZBB-NEXT: # %bb.6:1005; RV32ZBB-NEXT: sltu a2, t0, a71006; RV32ZBB-NEXT: j .LBB12_81007; RV32ZBB-NEXT: .LBB12_7:1008; RV32ZBB-NEXT: sltu a2, a2, a51009; RV32ZBB-NEXT: .LBB12_8:1010; RV32ZBB-NEXT: xor a6, a1, a61011; RV32ZBB-NEXT: xor a4, a3, a41012; RV32ZBB-NEXT: or a4, a4, a61013; RV32ZBB-NEXT: beqz a4, .LBB12_101014; RV32ZBB-NEXT: # %bb.9:1015; RV32ZBB-NEXT: mv a2, t11016; RV32ZBB-NEXT: .LBB12_10:1017; RV32ZBB-NEXT: neg a4, a21018; RV32ZBB-NEXT: xor t0, a5, a41019; RV32ZBB-NEXT: xor t3, a7, a41020; RV32ZBB-NEXT: sltu a5, t0, a41021; RV32ZBB-NEXT: add a6, t3, a21022; RV32ZBB-NEXT: add t0, t0, a21023; RV32ZBB-NEXT: sub t1, a6, a51024; RV32ZBB-NEXT: snez a6, t11025; RV32ZBB-NEXT: snez t2, t01026; RV32ZBB-NEXT: or a6, t2, a61027; RV32ZBB-NEXT: beqz a7, .LBB12_121028; RV32ZBB-NEXT: # %bb.11:1029; RV32ZBB-NEXT: sltu a5, t3, a41030; RV32ZBB-NEXT: .LBB12_12:1031; RV32ZBB-NEXT: xor a3, a3, a41032; RV32ZBB-NEXT: xor a1, a1, a41033; RV32ZBB-NEXT: add t1, t1, t21034; RV32ZBB-NEXT: neg a7, t01035; RV32ZBB-NEXT: add t0, a3, a21036; RV32ZBB-NEXT: sltu a3, a3, a41037; RV32ZBB-NEXT: add a1, a1, a21038; RV32ZBB-NEXT: neg a2, t11039; RV32ZBB-NEXT: sub a4, t0, a51040; RV32ZBB-NEXT: sub a1, a1, a31041; RV32ZBB-NEXT: sltu a3, t0, a51042; RV32ZBB-NEXT: neg a5, a41043; RV32ZBB-NEXT: sub a1, a1, a31044; RV32ZBB-NEXT: snez a3, a41045; RV32ZBB-NEXT: sltu a4, a5, a61046; RV32ZBB-NEXT: add a1, a1, a31047; RV32ZBB-NEXT: sub a3, a5, a61048; RV32ZBB-NEXT: neg a1, a11049; RV32ZBB-NEXT: sub a1, a1, a41050; RV32ZBB-NEXT: sw a7, 0(a0)1051; RV32ZBB-NEXT: sw a2, 4(a0)1052; RV32ZBB-NEXT: sw a3, 8(a0)1053; RV32ZBB-NEXT: sw a1, 12(a0)1054; RV32ZBB-NEXT: ret1055;1056; RV64ZBB-LABEL: abd_ext_i128_undef:1057; RV64ZBB: # %bb.0:1058; RV64ZBB-NEXT: sltu a4, a0, a21059; RV64ZBB-NEXT: sub a3, a1, a31060; RV64ZBB-NEXT: sub a3, a3, a41061; RV64ZBB-NEXT: sub a2, a0, a21062; RV64ZBB-NEXT: beq a3, a1, .LBB12_21063; RV64ZBB-NEXT: # %bb.1:1064; RV64ZBB-NEXT: sltu a0, a1, a31065; RV64ZBB-NEXT: j .LBB12_31066; RV64ZBB-NEXT: .LBB12_2:1067; RV64ZBB-NEXT: sltu a0, a0, a21068; RV64ZBB-NEXT: .LBB12_3:1069; RV64ZBB-NEXT: neg a1, a01070; RV64ZBB-NEXT: xor a2, a2, a11071; RV64ZBB-NEXT: xor a3, a3, a11072; RV64ZBB-NEXT: sltu a1, a2, a11073; RV64ZBB-NEXT: add a3, a3, a01074; RV64ZBB-NEXT: add a0, a2, a01075; RV64ZBB-NEXT: sub a3, a3, a11076; RV64ZBB-NEXT: snez a1, a01077; RV64ZBB-NEXT: add a1, a3, a11078; RV64ZBB-NEXT: neg a1, a11079; RV64ZBB-NEXT: neg a0, a01080; RV64ZBB-NEXT: ret1081 %aext = zext i128 %a to i2561082 %bext = zext i128 %b to i2561083 %sub = sub i256 %aext, %bext1084 %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)1085 %nabs = sub i256 0, %abs1086 %trunc = trunc i256 %nabs to i1281087 ret i128 %trunc1088}1089 1090;1091; sub(umin(a,b),umax(a,b)) -> nabds(a,b)1092;1093 1094define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {1095; NOZBB-LABEL: abd_minmax_i8:1096; NOZBB: # %bb.0:1097; NOZBB-NEXT: zext.b a1, a11098; NOZBB-NEXT: zext.b a0, a01099; NOZBB-NEXT: mv a2, a01100; NOZBB-NEXT: bgeu a0, a1, .LBB13_31101; NOZBB-NEXT: # %bb.1:1102; NOZBB-NEXT: bgeu a1, a0, .LBB13_41103; NOZBB-NEXT: .LBB13_2:1104; NOZBB-NEXT: sub a0, a2, a01105; NOZBB-NEXT: ret1106; NOZBB-NEXT: .LBB13_3:1107; NOZBB-NEXT: mv a2, a11108; NOZBB-NEXT: bltu a1, a0, .LBB13_21109; NOZBB-NEXT: .LBB13_4:1110; NOZBB-NEXT: sub a0, a2, a11111; NOZBB-NEXT: ret1112;1113; ZBB-LABEL: abd_minmax_i8:1114; ZBB: # %bb.0:1115; ZBB-NEXT: zext.b a1, a11116; ZBB-NEXT: zext.b a0, a01117; ZBB-NEXT: minu a2, a0, a11118; ZBB-NEXT: maxu a0, a0, a11119; ZBB-NEXT: sub a0, a2, a01120; ZBB-NEXT: ret1121 %min = call i8 @llvm.umin.i8(i8 %a, i8 %b)1122 %max = call i8 @llvm.umax.i8(i8 %a, i8 %b)1123 %sub = sub i8 %min, %max1124 ret i8 %sub1125}1126 1127define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {1128; NOZBB-LABEL: abd_minmax_i16:1129; NOZBB: # %bb.0:1130; NOZBB-NEXT: lui a2, 161131; NOZBB-NEXT: addi a2, a2, -11132; NOZBB-NEXT: and a1, a1, a21133; NOZBB-NEXT: and a0, a0, a21134; NOZBB-NEXT: mv a2, a01135; NOZBB-NEXT: bgeu a0, a1, .LBB14_31136; NOZBB-NEXT: # %bb.1:1137; NOZBB-NEXT: bgeu a1, a0, .LBB14_41138; NOZBB-NEXT: .LBB14_2:1139; NOZBB-NEXT: sub a0, a2, a01140; NOZBB-NEXT: ret1141; NOZBB-NEXT: .LBB14_3:1142; NOZBB-NEXT: mv a2, a11143; NOZBB-NEXT: bltu a1, a0, .LBB14_21144; NOZBB-NEXT: .LBB14_4:1145; NOZBB-NEXT: sub a0, a2, a11146; NOZBB-NEXT: ret1147;1148; ZBB-LABEL: abd_minmax_i16:1149; ZBB: # %bb.0:1150; ZBB-NEXT: zext.h a1, a11151; ZBB-NEXT: zext.h a0, a01152; ZBB-NEXT: minu a2, a0, a11153; ZBB-NEXT: maxu a0, a0, a11154; ZBB-NEXT: sub a0, a2, a01155; ZBB-NEXT: ret1156 %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)1157 %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)1158 %sub = sub i16 %min, %max1159 ret i16 %sub1160}1161 1162define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {1163; RV32I-LABEL: abd_minmax_i32:1164; RV32I: # %bb.0:1165; RV32I-NEXT: mv a2, a01166; RV32I-NEXT: bgeu a0, a1, .LBB15_31167; RV32I-NEXT: # %bb.1:1168; RV32I-NEXT: bgeu a1, a0, .LBB15_41169; RV32I-NEXT: .LBB15_2:1170; RV32I-NEXT: sub a0, a2, a01171; RV32I-NEXT: ret1172; RV32I-NEXT: .LBB15_3:1173; RV32I-NEXT: mv a2, a11174; RV32I-NEXT: bltu a1, a0, .LBB15_21175; RV32I-NEXT: .LBB15_4:1176; RV32I-NEXT: sub a0, a2, a11177; RV32I-NEXT: ret1178;1179; RV64I-LABEL: abd_minmax_i32:1180; RV64I: # %bb.0:1181; RV64I-NEXT: sext.w a1, a11182; RV64I-NEXT: sext.w a0, a01183; RV64I-NEXT: mv a2, a01184; RV64I-NEXT: bgeu a0, a1, .LBB15_31185; RV64I-NEXT: # %bb.1:1186; RV64I-NEXT: bgeu a1, a0, .LBB15_41187; RV64I-NEXT: .LBB15_2:1188; RV64I-NEXT: subw a0, a2, a01189; RV64I-NEXT: ret1190; RV64I-NEXT: .LBB15_3:1191; RV64I-NEXT: mv a2, a11192; RV64I-NEXT: bltu a1, a0, .LBB15_21193; RV64I-NEXT: .LBB15_4:1194; RV64I-NEXT: subw a0, a2, a11195; RV64I-NEXT: ret1196;1197; RV32ZBB-LABEL: abd_minmax_i32:1198; RV32ZBB: # %bb.0:1199; RV32ZBB-NEXT: minu a2, a0, a11200; RV32ZBB-NEXT: maxu a0, a0, a11201; RV32ZBB-NEXT: sub a0, a2, a01202; RV32ZBB-NEXT: ret1203;1204; RV64ZBB-LABEL: abd_minmax_i32:1205; RV64ZBB: # %bb.0:1206; RV64ZBB-NEXT: sext.w a1, a11207; RV64ZBB-NEXT: sext.w a0, a01208; RV64ZBB-NEXT: minu a2, a0, a11209; RV64ZBB-NEXT: maxu a0, a0, a11210; RV64ZBB-NEXT: subw a0, a2, a01211; RV64ZBB-NEXT: ret1212 %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)1213 %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)1214 %sub = sub i32 %min, %max1215 ret i32 %sub1216}1217 1218define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {1219; RV32I-LABEL: abd_minmax_i64:1220; RV32I: # %bb.0:1221; RV32I-NEXT: beq a1, a3, .LBB16_21222; RV32I-NEXT: # %bb.1:1223; RV32I-NEXT: sltu a6, a1, a31224; RV32I-NEXT: j .LBB16_31225; RV32I-NEXT: .LBB16_2:1226; RV32I-NEXT: sltu a6, a0, a21227; RV32I-NEXT: .LBB16_3:1228; RV32I-NEXT: mv a4, a11229; RV32I-NEXT: mv a5, a01230; RV32I-NEXT: bnez a6, .LBB16_51231; RV32I-NEXT: # %bb.4:1232; RV32I-NEXT: mv a4, a31233; RV32I-NEXT: mv a5, a21234; RV32I-NEXT: .LBB16_5:1235; RV32I-NEXT: beq a1, a3, .LBB16_71236; RV32I-NEXT: # %bb.6:1237; RV32I-NEXT: sltu a6, a3, a11238; RV32I-NEXT: beqz a6, .LBB16_81239; RV32I-NEXT: j .LBB16_91240; RV32I-NEXT: .LBB16_7:1241; RV32I-NEXT: sltu a6, a2, a01242; RV32I-NEXT: bnez a6, .LBB16_91243; RV32I-NEXT: .LBB16_8:1244; RV32I-NEXT: mv a1, a31245; RV32I-NEXT: mv a0, a21246; RV32I-NEXT: .LBB16_9:1247; RV32I-NEXT: sltu a2, a5, a01248; RV32I-NEXT: sub a1, a4, a11249; RV32I-NEXT: sub a1, a1, a21250; RV32I-NEXT: sub a0, a5, a01251; RV32I-NEXT: ret1252;1253; RV64I-LABEL: abd_minmax_i64:1254; RV64I: # %bb.0:1255; RV64I-NEXT: mv a2, a01256; RV64I-NEXT: bgeu a0, a1, .LBB16_31257; RV64I-NEXT: # %bb.1:1258; RV64I-NEXT: bgeu a1, a0, .LBB16_41259; RV64I-NEXT: .LBB16_2:1260; RV64I-NEXT: sub a0, a2, a01261; RV64I-NEXT: ret1262; RV64I-NEXT: .LBB16_3:1263; RV64I-NEXT: mv a2, a11264; RV64I-NEXT: bltu a1, a0, .LBB16_21265; RV64I-NEXT: .LBB16_4:1266; RV64I-NEXT: sub a0, a2, a11267; RV64I-NEXT: ret1268;1269; RV32ZBB-LABEL: abd_minmax_i64:1270; RV32ZBB: # %bb.0:1271; RV32ZBB-NEXT: beq a1, a3, .LBB16_21272; RV32ZBB-NEXT: # %bb.1:1273; RV32ZBB-NEXT: sltu a6, a1, a31274; RV32ZBB-NEXT: j .LBB16_31275; RV32ZBB-NEXT: .LBB16_2:1276; RV32ZBB-NEXT: sltu a6, a0, a21277; RV32ZBB-NEXT: .LBB16_3:1278; RV32ZBB-NEXT: mv a4, a11279; RV32ZBB-NEXT: mv a5, a01280; RV32ZBB-NEXT: bnez a6, .LBB16_51281; RV32ZBB-NEXT: # %bb.4:1282; RV32ZBB-NEXT: mv a4, a31283; RV32ZBB-NEXT: mv a5, a21284; RV32ZBB-NEXT: .LBB16_5:1285; RV32ZBB-NEXT: beq a1, a3, .LBB16_71286; RV32ZBB-NEXT: # %bb.6:1287; RV32ZBB-NEXT: sltu a6, a3, a11288; RV32ZBB-NEXT: beqz a6, .LBB16_81289; RV32ZBB-NEXT: j .LBB16_91290; RV32ZBB-NEXT: .LBB16_7:1291; RV32ZBB-NEXT: sltu a6, a2, a01292; RV32ZBB-NEXT: bnez a6, .LBB16_91293; RV32ZBB-NEXT: .LBB16_8:1294; RV32ZBB-NEXT: mv a1, a31295; RV32ZBB-NEXT: mv a0, a21296; RV32ZBB-NEXT: .LBB16_9:1297; RV32ZBB-NEXT: sltu a2, a5, a01298; RV32ZBB-NEXT: sub a1, a4, a11299; RV32ZBB-NEXT: sub a1, a1, a21300; RV32ZBB-NEXT: sub a0, a5, a01301; RV32ZBB-NEXT: ret1302;1303; RV64ZBB-LABEL: abd_minmax_i64:1304; RV64ZBB: # %bb.0:1305; RV64ZBB-NEXT: minu a2, a0, a11306; RV64ZBB-NEXT: maxu a0, a0, a11307; RV64ZBB-NEXT: sub a0, a2, a01308; RV64ZBB-NEXT: ret1309 %min = call i64 @llvm.umin.i64(i64 %a, i64 %b)1310 %max = call i64 @llvm.umax.i64(i64 %a, i64 %b)1311 %sub = sub i64 %min, %max1312 ret i64 %sub1313}1314 1315define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {1316; RV32I-LABEL: abd_minmax_i128:1317; RV32I: # %bb.0:1318; RV32I-NEXT: lw a6, 4(a2)1319; RV32I-NEXT: lw a7, 8(a2)1320; RV32I-NEXT: lw t0, 12(a2)1321; RV32I-NEXT: lw a3, 4(a1)1322; RV32I-NEXT: lw a5, 12(a1)1323; RV32I-NEXT: lw a4, 8(a1)1324; RV32I-NEXT: beq a5, t0, .LBB17_21325; RV32I-NEXT: # %bb.1:1326; RV32I-NEXT: sltu t1, a5, t01327; RV32I-NEXT: j .LBB17_31328; RV32I-NEXT: .LBB17_2:1329; RV32I-NEXT: sltu t1, a4, a71330; RV32I-NEXT: .LBB17_3:1331; RV32I-NEXT: lw t2, 0(a2)1332; RV32I-NEXT: lw a1, 0(a1)1333; RV32I-NEXT: beq a3, a6, .LBB17_51334; RV32I-NEXT: # %bb.4:1335; RV32I-NEXT: sltu t6, a3, a61336; RV32I-NEXT: j .LBB17_61337; RV32I-NEXT: .LBB17_5:1338; RV32I-NEXT: sltu t6, a1, t21339; RV32I-NEXT: .LBB17_6:1340; RV32I-NEXT: xor a2, a5, t01341; RV32I-NEXT: xor t3, a4, a71342; RV32I-NEXT: or t5, t3, a21343; RV32I-NEXT: beqz t5, .LBB17_81344; RV32I-NEXT: # %bb.7:1345; RV32I-NEXT: mv t6, t11346; RV32I-NEXT: .LBB17_8:1347; RV32I-NEXT: mv a2, a11348; RV32I-NEXT: mv t1, a31349; RV32I-NEXT: mv t4, a51350; RV32I-NEXT: mv t3, a41351; RV32I-NEXT: bnez t6, .LBB17_101352; RV32I-NEXT: # %bb.9:1353; RV32I-NEXT: mv a2, t21354; RV32I-NEXT: mv t1, a61355; RV32I-NEXT: mv t4, t01356; RV32I-NEXT: mv t3, a71357; RV32I-NEXT: .LBB17_10:1358; RV32I-NEXT: beq a5, t0, .LBB17_121359; RV32I-NEXT: # %bb.11:1360; RV32I-NEXT: sltu t6, t0, a51361; RV32I-NEXT: j .LBB17_131362; RV32I-NEXT: .LBB17_12:1363; RV32I-NEXT: sltu t6, a7, a41364; RV32I-NEXT: .LBB17_13:1365; RV32I-NEXT: addi sp, sp, -161366; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1367; RV32I-NEXT: beq a3, a6, .LBB17_151368; RV32I-NEXT: # %bb.14:1369; RV32I-NEXT: sltu s0, a6, a31370; RV32I-NEXT: bnez t5, .LBB17_161371; RV32I-NEXT: j .LBB17_171372; RV32I-NEXT: .LBB17_15:1373; RV32I-NEXT: sltu s0, t2, a11374; RV32I-NEXT: beqz t5, .LBB17_171375; RV32I-NEXT: .LBB17_16:1376; RV32I-NEXT: mv s0, t61377; RV32I-NEXT: .LBB17_17:1378; RV32I-NEXT: bnez s0, .LBB17_191379; RV32I-NEXT: # %bb.18:1380; RV32I-NEXT: mv a1, t21381; RV32I-NEXT: mv a3, a61382; RV32I-NEXT: mv a5, t01383; RV32I-NEXT: mv a4, a71384; RV32I-NEXT: .LBB17_19:1385; RV32I-NEXT: sltu a7, t3, a41386; RV32I-NEXT: sub a5, t4, a51387; RV32I-NEXT: sltu a6, a2, a11388; RV32I-NEXT: sub a5, a5, a71389; RV32I-NEXT: mv a7, a61390; RV32I-NEXT: beq t1, a3, .LBB17_211391; RV32I-NEXT: # %bb.20:1392; RV32I-NEXT: sltu a7, t1, a31393; RV32I-NEXT: .LBB17_21:1394; RV32I-NEXT: sub a4, t3, a41395; RV32I-NEXT: sub a3, t1, a31396; RV32I-NEXT: sub a2, a2, a11397; RV32I-NEXT: sltu a1, a4, a71398; RV32I-NEXT: sub a4, a4, a71399; RV32I-NEXT: sub a3, a3, a61400; RV32I-NEXT: sub a5, a5, a11401; RV32I-NEXT: sw a2, 0(a0)1402; RV32I-NEXT: sw a3, 4(a0)1403; RV32I-NEXT: sw a4, 8(a0)1404; RV32I-NEXT: sw a5, 12(a0)1405; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1406; RV32I-NEXT: addi sp, sp, 161407; RV32I-NEXT: ret1408;1409; RV64I-LABEL: abd_minmax_i128:1410; RV64I: # %bb.0:1411; RV64I-NEXT: beq a1, a3, .LBB17_21412; RV64I-NEXT: # %bb.1:1413; RV64I-NEXT: sltu a6, a1, a31414; RV64I-NEXT: j .LBB17_31415; RV64I-NEXT: .LBB17_2:1416; RV64I-NEXT: sltu a6, a0, a21417; RV64I-NEXT: .LBB17_3:1418; RV64I-NEXT: mv a4, a11419; RV64I-NEXT: mv a5, a01420; RV64I-NEXT: bnez a6, .LBB17_51421; RV64I-NEXT: # %bb.4:1422; RV64I-NEXT: mv a4, a31423; RV64I-NEXT: mv a5, a21424; RV64I-NEXT: .LBB17_5:1425; RV64I-NEXT: beq a1, a3, .LBB17_71426; RV64I-NEXT: # %bb.6:1427; RV64I-NEXT: sltu a6, a3, a11428; RV64I-NEXT: beqz a6, .LBB17_81429; RV64I-NEXT: j .LBB17_91430; RV64I-NEXT: .LBB17_7:1431; RV64I-NEXT: sltu a6, a2, a01432; RV64I-NEXT: bnez a6, .LBB17_91433; RV64I-NEXT: .LBB17_8:1434; RV64I-NEXT: mv a1, a31435; RV64I-NEXT: mv a0, a21436; RV64I-NEXT: .LBB17_9:1437; RV64I-NEXT: sltu a2, a5, a01438; RV64I-NEXT: sub a1, a4, a11439; RV64I-NEXT: sub a1, a1, a21440; RV64I-NEXT: sub a0, a5, a01441; RV64I-NEXT: ret1442;1443; RV32ZBB-LABEL: abd_minmax_i128:1444; RV32ZBB: # %bb.0:1445; RV32ZBB-NEXT: lw a6, 4(a2)1446; RV32ZBB-NEXT: lw a7, 8(a2)1447; RV32ZBB-NEXT: lw t0, 12(a2)1448; RV32ZBB-NEXT: lw a3, 4(a1)1449; RV32ZBB-NEXT: lw a5, 12(a1)1450; RV32ZBB-NEXT: lw a4, 8(a1)1451; RV32ZBB-NEXT: beq a5, t0, .LBB17_21452; RV32ZBB-NEXT: # %bb.1:1453; RV32ZBB-NEXT: sltu t1, a5, t01454; RV32ZBB-NEXT: j .LBB17_31455; RV32ZBB-NEXT: .LBB17_2:1456; RV32ZBB-NEXT: sltu t1, a4, a71457; RV32ZBB-NEXT: .LBB17_3:1458; RV32ZBB-NEXT: lw t2, 0(a2)1459; RV32ZBB-NEXT: lw a1, 0(a1)1460; RV32ZBB-NEXT: beq a3, a6, .LBB17_51461; RV32ZBB-NEXT: # %bb.4:1462; RV32ZBB-NEXT: sltu t6, a3, a61463; RV32ZBB-NEXT: j .LBB17_61464; RV32ZBB-NEXT: .LBB17_5:1465; RV32ZBB-NEXT: sltu t6, a1, t21466; RV32ZBB-NEXT: .LBB17_6:1467; RV32ZBB-NEXT: xor a2, a5, t01468; RV32ZBB-NEXT: xor t3, a4, a71469; RV32ZBB-NEXT: or t5, t3, a21470; RV32ZBB-NEXT: beqz t5, .LBB17_81471; RV32ZBB-NEXT: # %bb.7:1472; RV32ZBB-NEXT: mv t6, t11473; RV32ZBB-NEXT: .LBB17_8:1474; RV32ZBB-NEXT: mv a2, a11475; RV32ZBB-NEXT: mv t1, a31476; RV32ZBB-NEXT: mv t4, a51477; RV32ZBB-NEXT: mv t3, a41478; RV32ZBB-NEXT: bnez t6, .LBB17_101479; RV32ZBB-NEXT: # %bb.9:1480; RV32ZBB-NEXT: mv a2, t21481; RV32ZBB-NEXT: mv t1, a61482; RV32ZBB-NEXT: mv t4, t01483; RV32ZBB-NEXT: mv t3, a71484; RV32ZBB-NEXT: .LBB17_10:1485; RV32ZBB-NEXT: beq a5, t0, .LBB17_121486; RV32ZBB-NEXT: # %bb.11:1487; RV32ZBB-NEXT: sltu t6, t0, a51488; RV32ZBB-NEXT: j .LBB17_131489; RV32ZBB-NEXT: .LBB17_12:1490; RV32ZBB-NEXT: sltu t6, a7, a41491; RV32ZBB-NEXT: .LBB17_13:1492; RV32ZBB-NEXT: addi sp, sp, -161493; RV32ZBB-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1494; RV32ZBB-NEXT: beq a3, a6, .LBB17_151495; RV32ZBB-NEXT: # %bb.14:1496; RV32ZBB-NEXT: sltu s0, a6, a31497; RV32ZBB-NEXT: bnez t5, .LBB17_161498; RV32ZBB-NEXT: j .LBB17_171499; RV32ZBB-NEXT: .LBB17_15:1500; RV32ZBB-NEXT: sltu s0, t2, a11501; RV32ZBB-NEXT: beqz t5, .LBB17_171502; RV32ZBB-NEXT: .LBB17_16:1503; RV32ZBB-NEXT: mv s0, t61504; RV32ZBB-NEXT: .LBB17_17:1505; RV32ZBB-NEXT: bnez s0, .LBB17_191506; RV32ZBB-NEXT: # %bb.18:1507; RV32ZBB-NEXT: mv a1, t21508; RV32ZBB-NEXT: mv a3, a61509; RV32ZBB-NEXT: mv a5, t01510; RV32ZBB-NEXT: mv a4, a71511; RV32ZBB-NEXT: .LBB17_19:1512; RV32ZBB-NEXT: sltu a7, t3, a41513; RV32ZBB-NEXT: sub a5, t4, a51514; RV32ZBB-NEXT: sltu a6, a2, a11515; RV32ZBB-NEXT: sub a5, a5, a71516; RV32ZBB-NEXT: mv a7, a61517; RV32ZBB-NEXT: beq t1, a3, .LBB17_211518; RV32ZBB-NEXT: # %bb.20:1519; RV32ZBB-NEXT: sltu a7, t1, a31520; RV32ZBB-NEXT: .LBB17_21:1521; RV32ZBB-NEXT: sub a4, t3, a41522; RV32ZBB-NEXT: sub a3, t1, a31523; RV32ZBB-NEXT: sub a2, a2, a11524; RV32ZBB-NEXT: sltu a1, a4, a71525; RV32ZBB-NEXT: sub a4, a4, a71526; RV32ZBB-NEXT: sub a3, a3, a61527; RV32ZBB-NEXT: sub a5, a5, a11528; RV32ZBB-NEXT: sw a2, 0(a0)1529; RV32ZBB-NEXT: sw a3, 4(a0)1530; RV32ZBB-NEXT: sw a4, 8(a0)1531; RV32ZBB-NEXT: sw a5, 12(a0)1532; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1533; RV32ZBB-NEXT: addi sp, sp, 161534; RV32ZBB-NEXT: ret1535;1536; RV64ZBB-LABEL: abd_minmax_i128:1537; RV64ZBB: # %bb.0:1538; RV64ZBB-NEXT: beq a1, a3, .LBB17_21539; RV64ZBB-NEXT: # %bb.1:1540; RV64ZBB-NEXT: sltu a6, a1, a31541; RV64ZBB-NEXT: j .LBB17_31542; RV64ZBB-NEXT: .LBB17_2:1543; RV64ZBB-NEXT: sltu a6, a0, a21544; RV64ZBB-NEXT: .LBB17_3:1545; RV64ZBB-NEXT: mv a4, a11546; RV64ZBB-NEXT: mv a5, a01547; RV64ZBB-NEXT: bnez a6, .LBB17_51548; RV64ZBB-NEXT: # %bb.4:1549; RV64ZBB-NEXT: mv a4, a31550; RV64ZBB-NEXT: mv a5, a21551; RV64ZBB-NEXT: .LBB17_5:1552; RV64ZBB-NEXT: beq a1, a3, .LBB17_71553; RV64ZBB-NEXT: # %bb.6:1554; RV64ZBB-NEXT: sltu a6, a3, a11555; RV64ZBB-NEXT: beqz a6, .LBB17_81556; RV64ZBB-NEXT: j .LBB17_91557; RV64ZBB-NEXT: .LBB17_7:1558; RV64ZBB-NEXT: sltu a6, a2, a01559; RV64ZBB-NEXT: bnez a6, .LBB17_91560; RV64ZBB-NEXT: .LBB17_8:1561; RV64ZBB-NEXT: mv a1, a31562; RV64ZBB-NEXT: mv a0, a21563; RV64ZBB-NEXT: .LBB17_9:1564; RV64ZBB-NEXT: sltu a2, a5, a01565; RV64ZBB-NEXT: sub a1, a4, a11566; RV64ZBB-NEXT: sub a1, a1, a21567; RV64ZBB-NEXT: sub a0, a5, a01568; RV64ZBB-NEXT: ret1569 %min = call i128 @llvm.umin.i128(i128 %a, i128 %b)1570 %max = call i128 @llvm.umax.i128(i128 %a, i128 %b)1571 %sub = sub i128 %min, %max1572 ret i128 %sub1573}1574 1575;1576; select(icmp(a,b),sub(a,b),sub(b,a)) -> nabds(a,b)1577;1578 1579define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {1580; NOZBB-LABEL: abd_cmp_i8:1581; NOZBB: # %bb.0:1582; NOZBB-NEXT: zext.b a2, a01583; NOZBB-NEXT: zext.b a3, a11584; NOZBB-NEXT: bgeu a3, a2, .LBB18_21585; NOZBB-NEXT: # %bb.1:1586; NOZBB-NEXT: sub a0, a1, a01587; NOZBB-NEXT: ret1588; NOZBB-NEXT: .LBB18_2:1589; NOZBB-NEXT: sub a0, a0, a11590; NOZBB-NEXT: ret1591;1592; ZBB-LABEL: abd_cmp_i8:1593; ZBB: # %bb.0:1594; ZBB-NEXT: zext.b a2, a01595; ZBB-NEXT: zext.b a3, a11596; ZBB-NEXT: bgeu a3, a2, .LBB18_21597; ZBB-NEXT: # %bb.1:1598; ZBB-NEXT: sub a0, a1, a01599; ZBB-NEXT: ret1600; ZBB-NEXT: .LBB18_2:1601; ZBB-NEXT: sub a0, a0, a11602; ZBB-NEXT: ret1603 %cmp = icmp ule i8 %a, %b1604 %ab = sub i8 %a, %b1605 %ba = sub i8 %b, %a1606 %sel = select i1 %cmp, i8 %ab, i8 %ba1607 ret i8 %sel1608}1609 1610define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {1611; NOZBB-LABEL: abd_cmp_i16:1612; NOZBB: # %bb.0:1613; NOZBB-NEXT: lui a2, 161614; NOZBB-NEXT: addi a2, a2, -11615; NOZBB-NEXT: and a3, a1, a21616; NOZBB-NEXT: and a2, a0, a21617; NOZBB-NEXT: bltu a2, a3, .LBB19_21618; NOZBB-NEXT: # %bb.1:1619; NOZBB-NEXT: sub a0, a1, a01620; NOZBB-NEXT: ret1621; NOZBB-NEXT: .LBB19_2:1622; NOZBB-NEXT: sub a0, a0, a11623; NOZBB-NEXT: ret1624;1625; ZBB-LABEL: abd_cmp_i16:1626; ZBB: # %bb.0:1627; ZBB-NEXT: zext.h a2, a11628; ZBB-NEXT: zext.h a3, a01629; ZBB-NEXT: bltu a3, a2, .LBB19_21630; ZBB-NEXT: # %bb.1:1631; ZBB-NEXT: sub a0, a1, a01632; ZBB-NEXT: ret1633; ZBB-NEXT: .LBB19_2:1634; ZBB-NEXT: sub a0, a0, a11635; ZBB-NEXT: ret1636 %cmp = icmp ult i16 %a, %b1637 %ab = sub i16 %a, %b1638 %ba = sub i16 %b, %a1639 %sel = select i1 %cmp, i16 %ab, i16 %ba1640 ret i16 %sel1641}1642 1643define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {1644; RV32I-LABEL: abd_cmp_i32:1645; RV32I: # %bb.0:1646; RV32I-NEXT: bgeu a0, a1, .LBB20_21647; RV32I-NEXT: # %bb.1:1648; RV32I-NEXT: sub a0, a0, a11649; RV32I-NEXT: ret1650; RV32I-NEXT: .LBB20_2:1651; RV32I-NEXT: sub a0, a1, a01652; RV32I-NEXT: ret1653;1654; RV64I-LABEL: abd_cmp_i32:1655; RV64I: # %bb.0:1656; RV64I-NEXT: sext.w a2, a11657; RV64I-NEXT: sext.w a3, a01658; RV64I-NEXT: bgeu a3, a2, .LBB20_21659; RV64I-NEXT: # %bb.1:1660; RV64I-NEXT: subw a0, a0, a11661; RV64I-NEXT: ret1662; RV64I-NEXT: .LBB20_2:1663; RV64I-NEXT: subw a0, a1, a01664; RV64I-NEXT: ret1665;1666; RV32ZBB-LABEL: abd_cmp_i32:1667; RV32ZBB: # %bb.0:1668; RV32ZBB-NEXT: bgeu a0, a1, .LBB20_21669; RV32ZBB-NEXT: # %bb.1:1670; RV32ZBB-NEXT: sub a0, a0, a11671; RV32ZBB-NEXT: ret1672; RV32ZBB-NEXT: .LBB20_2:1673; RV32ZBB-NEXT: sub a0, a1, a01674; RV32ZBB-NEXT: ret1675;1676; RV64ZBB-LABEL: abd_cmp_i32:1677; RV64ZBB: # %bb.0:1678; RV64ZBB-NEXT: sext.w a2, a11679; RV64ZBB-NEXT: sext.w a3, a01680; RV64ZBB-NEXT: bgeu a3, a2, .LBB20_21681; RV64ZBB-NEXT: # %bb.1:1682; RV64ZBB-NEXT: subw a0, a0, a11683; RV64ZBB-NEXT: ret1684; RV64ZBB-NEXT: .LBB20_2:1685; RV64ZBB-NEXT: subw a0, a1, a01686; RV64ZBB-NEXT: ret1687 %cmp = icmp uge i32 %a, %b1688 %ab = sub i32 %a, %b1689 %ba = sub i32 %b, %a1690 %sel = select i1 %cmp, i32 %ba, i32 %ab1691 ret i32 %sel1692}1693 1694define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {1695; RV32I-LABEL: abd_cmp_i64:1696; RV32I: # %bb.0:1697; RV32I-NEXT: sltu a4, a0, a21698; RV32I-NEXT: mv a5, a41699; RV32I-NEXT: beq a1, a3, .LBB21_21700; RV32I-NEXT: # %bb.1:1701; RV32I-NEXT: sltu a5, a1, a31702; RV32I-NEXT: .LBB21_2:1703; RV32I-NEXT: bnez a5, .LBB21_41704; RV32I-NEXT: # %bb.3:1705; RV32I-NEXT: sltu a4, a2, a01706; RV32I-NEXT: sub a1, a3, a11707; RV32I-NEXT: sub a1, a1, a41708; RV32I-NEXT: sub a0, a2, a01709; RV32I-NEXT: ret1710; RV32I-NEXT: .LBB21_4:1711; RV32I-NEXT: sub a1, a1, a31712; RV32I-NEXT: sub a1, a1, a41713; RV32I-NEXT: sub a0, a0, a21714; RV32I-NEXT: ret1715;1716; RV64I-LABEL: abd_cmp_i64:1717; RV64I: # %bb.0:1718; RV64I-NEXT: bltu a0, a1, .LBB21_21719; RV64I-NEXT: # %bb.1:1720; RV64I-NEXT: sub a0, a1, a01721; RV64I-NEXT: ret1722; RV64I-NEXT: .LBB21_2:1723; RV64I-NEXT: sub a0, a0, a11724; RV64I-NEXT: ret1725;1726; RV32ZBB-LABEL: abd_cmp_i64:1727; RV32ZBB: # %bb.0:1728; RV32ZBB-NEXT: sltu a4, a0, a21729; RV32ZBB-NEXT: mv a5, a41730; RV32ZBB-NEXT: beq a1, a3, .LBB21_21731; RV32ZBB-NEXT: # %bb.1:1732; RV32ZBB-NEXT: sltu a5, a1, a31733; RV32ZBB-NEXT: .LBB21_2:1734; RV32ZBB-NEXT: bnez a5, .LBB21_41735; RV32ZBB-NEXT: # %bb.3:1736; RV32ZBB-NEXT: sltu a4, a2, a01737; RV32ZBB-NEXT: sub a1, a3, a11738; RV32ZBB-NEXT: sub a1, a1, a41739; RV32ZBB-NEXT: sub a0, a2, a01740; RV32ZBB-NEXT: ret1741; RV32ZBB-NEXT: .LBB21_4:1742; RV32ZBB-NEXT: sub a1, a1, a31743; RV32ZBB-NEXT: sub a1, a1, a41744; RV32ZBB-NEXT: sub a0, a0, a21745; RV32ZBB-NEXT: ret1746;1747; RV64ZBB-LABEL: abd_cmp_i64:1748; RV64ZBB: # %bb.0:1749; RV64ZBB-NEXT: bltu a0, a1, .LBB21_21750; RV64ZBB-NEXT: # %bb.1:1751; RV64ZBB-NEXT: sub a0, a1, a01752; RV64ZBB-NEXT: ret1753; RV64ZBB-NEXT: .LBB21_2:1754; RV64ZBB-NEXT: sub a0, a0, a11755; RV64ZBB-NEXT: ret1756 %cmp = icmp ult i64 %a, %b1757 %ab = sub i64 %a, %b1758 %ba = sub i64 %b, %a1759 %sel = select i1 %cmp, i64 %ab, i64 %ba1760 ret i64 %sel1761}1762 1763define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {1764; RV32I-LABEL: abd_cmp_i128:1765; RV32I: # %bb.0:1766; RV32I-NEXT: lw a3, 0(a2)1767; RV32I-NEXT: lw a4, 4(a2)1768; RV32I-NEXT: lw a5, 8(a2)1769; RV32I-NEXT: lw a7, 12(a2)1770; RV32I-NEXT: lw a2, 0(a1)1771; RV32I-NEXT: lw a6, 8(a1)1772; RV32I-NEXT: lw t1, 12(a1)1773; RV32I-NEXT: lw a1, 4(a1)1774; RV32I-NEXT: sltu t0, a6, a51775; RV32I-NEXT: mv t4, t01776; RV32I-NEXT: beq t1, a7, .LBB22_21777; RV32I-NEXT: # %bb.1:1778; RV32I-NEXT: sltu t4, t1, a71779; RV32I-NEXT: .LBB22_2:1780; RV32I-NEXT: sltu t2, a2, a31781; RV32I-NEXT: mv t3, t21782; RV32I-NEXT: beq a1, a4, .LBB22_41783; RV32I-NEXT: # %bb.3:1784; RV32I-NEXT: sltu t3, a1, a41785; RV32I-NEXT: .LBB22_4:1786; RV32I-NEXT: xor t5, t1, a71787; RV32I-NEXT: xor t6, a6, a51788; RV32I-NEXT: or t5, t6, t51789; RV32I-NEXT: mv t6, t31790; RV32I-NEXT: beqz t5, .LBB22_61791; RV32I-NEXT: # %bb.5:1792; RV32I-NEXT: mv t6, t41793; RV32I-NEXT: .LBB22_6:1794; RV32I-NEXT: sltu t4, a3, a21795; RV32I-NEXT: mv t5, t41796; RV32I-NEXT: beq a1, a4, .LBB22_81797; RV32I-NEXT: # %bb.7:1798; RV32I-NEXT: sltu t5, a4, a11799; RV32I-NEXT: .LBB22_8:1800; RV32I-NEXT: bnez t6, .LBB22_101801; RV32I-NEXT: # %bb.9:1802; RV32I-NEXT: sltu t0, a5, a61803; RV32I-NEXT: sub a7, a7, t11804; RV32I-NEXT: sub a5, a5, a61805; RV32I-NEXT: sub a4, a4, a11806; RV32I-NEXT: sub a6, a7, t01807; RV32I-NEXT: sltu a7, a5, t51808; RV32I-NEXT: sub a1, a5, t51809; RV32I-NEXT: sub a5, a4, t41810; RV32I-NEXT: sub a4, a6, a71811; RV32I-NEXT: sub a2, a3, a21812; RV32I-NEXT: j .LBB22_111813; RV32I-NEXT: .LBB22_10:1814; RV32I-NEXT: sub a7, t1, a71815; RV32I-NEXT: sub a5, a6, a51816; RV32I-NEXT: sub a4, a1, a41817; RV32I-NEXT: sub a6, a7, t01818; RV32I-NEXT: sltu a7, a5, t31819; RV32I-NEXT: sub a1, a5, t31820; RV32I-NEXT: sub a5, a4, t21821; RV32I-NEXT: sub a4, a6, a71822; RV32I-NEXT: sub a2, a2, a31823; RV32I-NEXT: .LBB22_11:1824; RV32I-NEXT: sw a2, 0(a0)1825; RV32I-NEXT: sw a5, 4(a0)1826; RV32I-NEXT: sw a1, 8(a0)1827; RV32I-NEXT: sw a4, 12(a0)1828; RV32I-NEXT: ret1829;1830; RV64I-LABEL: abd_cmp_i128:1831; RV64I: # %bb.0:1832; RV64I-NEXT: sltu a4, a0, a21833; RV64I-NEXT: mv a5, a41834; RV64I-NEXT: beq a1, a3, .LBB22_21835; RV64I-NEXT: # %bb.1:1836; RV64I-NEXT: sltu a5, a1, a31837; RV64I-NEXT: .LBB22_2:1838; RV64I-NEXT: bnez a5, .LBB22_41839; RV64I-NEXT: # %bb.3:1840; RV64I-NEXT: sltu a4, a2, a01841; RV64I-NEXT: sub a1, a3, a11842; RV64I-NEXT: sub a1, a1, a41843; RV64I-NEXT: sub a0, a2, a01844; RV64I-NEXT: ret1845; RV64I-NEXT: .LBB22_4:1846; RV64I-NEXT: sub a1, a1, a31847; RV64I-NEXT: sub a1, a1, a41848; RV64I-NEXT: sub a0, a0, a21849; RV64I-NEXT: ret1850;1851; RV32ZBB-LABEL: abd_cmp_i128:1852; RV32ZBB: # %bb.0:1853; RV32ZBB-NEXT: lw a3, 0(a2)1854; RV32ZBB-NEXT: lw a4, 4(a2)1855; RV32ZBB-NEXT: lw a5, 8(a2)1856; RV32ZBB-NEXT: lw a7, 12(a2)1857; RV32ZBB-NEXT: lw a2, 0(a1)1858; RV32ZBB-NEXT: lw a6, 8(a1)1859; RV32ZBB-NEXT: lw t1, 12(a1)1860; RV32ZBB-NEXT: lw a1, 4(a1)1861; RV32ZBB-NEXT: sltu t0, a6, a51862; RV32ZBB-NEXT: mv t4, t01863; RV32ZBB-NEXT: beq t1, a7, .LBB22_21864; RV32ZBB-NEXT: # %bb.1:1865; RV32ZBB-NEXT: sltu t4, t1, a71866; RV32ZBB-NEXT: .LBB22_2:1867; RV32ZBB-NEXT: sltu t2, a2, a31868; RV32ZBB-NEXT: mv t3, t21869; RV32ZBB-NEXT: beq a1, a4, .LBB22_41870; RV32ZBB-NEXT: # %bb.3:1871; RV32ZBB-NEXT: sltu t3, a1, a41872; RV32ZBB-NEXT: .LBB22_4:1873; RV32ZBB-NEXT: xor t5, t1, a71874; RV32ZBB-NEXT: xor t6, a6, a51875; RV32ZBB-NEXT: or t5, t6, t51876; RV32ZBB-NEXT: mv t6, t31877; RV32ZBB-NEXT: beqz t5, .LBB22_61878; RV32ZBB-NEXT: # %bb.5:1879; RV32ZBB-NEXT: mv t6, t41880; RV32ZBB-NEXT: .LBB22_6:1881; RV32ZBB-NEXT: sltu t4, a3, a21882; RV32ZBB-NEXT: mv t5, t41883; RV32ZBB-NEXT: beq a1, a4, .LBB22_81884; RV32ZBB-NEXT: # %bb.7:1885; RV32ZBB-NEXT: sltu t5, a4, a11886; RV32ZBB-NEXT: .LBB22_8:1887; RV32ZBB-NEXT: bnez t6, .LBB22_101888; RV32ZBB-NEXT: # %bb.9:1889; RV32ZBB-NEXT: sltu t0, a5, a61890; RV32ZBB-NEXT: sub a7, a7, t11891; RV32ZBB-NEXT: sub a5, a5, a61892; RV32ZBB-NEXT: sub a4, a4, a11893; RV32ZBB-NEXT: sub a6, a7, t01894; RV32ZBB-NEXT: sltu a7, a5, t51895; RV32ZBB-NEXT: sub a1, a5, t51896; RV32ZBB-NEXT: sub a5, a4, t41897; RV32ZBB-NEXT: sub a4, a6, a71898; RV32ZBB-NEXT: sub a2, a3, a21899; RV32ZBB-NEXT: j .LBB22_111900; RV32ZBB-NEXT: .LBB22_10:1901; RV32ZBB-NEXT: sub a7, t1, a71902; RV32ZBB-NEXT: sub a5, a6, a51903; RV32ZBB-NEXT: sub a4, a1, a41904; RV32ZBB-NEXT: sub a6, a7, t01905; RV32ZBB-NEXT: sltu a7, a5, t31906; RV32ZBB-NEXT: sub a1, a5, t31907; RV32ZBB-NEXT: sub a5, a4, t21908; RV32ZBB-NEXT: sub a4, a6, a71909; RV32ZBB-NEXT: sub a2, a2, a31910; RV32ZBB-NEXT: .LBB22_11:1911; RV32ZBB-NEXT: sw a2, 0(a0)1912; RV32ZBB-NEXT: sw a5, 4(a0)1913; RV32ZBB-NEXT: sw a1, 8(a0)1914; RV32ZBB-NEXT: sw a4, 12(a0)1915; RV32ZBB-NEXT: ret1916;1917; RV64ZBB-LABEL: abd_cmp_i128:1918; RV64ZBB: # %bb.0:1919; RV64ZBB-NEXT: sltu a4, a0, a21920; RV64ZBB-NEXT: mv a5, a41921; RV64ZBB-NEXT: beq a1, a3, .LBB22_21922; RV64ZBB-NEXT: # %bb.1:1923; RV64ZBB-NEXT: sltu a5, a1, a31924; RV64ZBB-NEXT: .LBB22_2:1925; RV64ZBB-NEXT: bnez a5, .LBB22_41926; RV64ZBB-NEXT: # %bb.3:1927; RV64ZBB-NEXT: sltu a4, a2, a01928; RV64ZBB-NEXT: sub a1, a3, a11929; RV64ZBB-NEXT: sub a1, a1, a41930; RV64ZBB-NEXT: sub a0, a2, a01931; RV64ZBB-NEXT: ret1932; RV64ZBB-NEXT: .LBB22_4:1933; RV64ZBB-NEXT: sub a1, a1, a31934; RV64ZBB-NEXT: sub a1, a1, a41935; RV64ZBB-NEXT: sub a0, a0, a21936; RV64ZBB-NEXT: ret1937 %cmp = icmp ult i128 %a, %b1938 %ab = sub i128 %a, %b1939 %ba = sub i128 %b, %a1940 %sel = select i1 %cmp, i128 %ab, i128 %ba1941 ret i128 %sel1942}1943 1944