2120 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=CHECK,NOZBB,RV32I3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK,NOZBB,RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=CHECK,ZBB,RV32ZBB5; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=CHECK,ZBB,RV64ZBB6 7;8; trunc(abs(sub(zext(a),zext(b)))) -> abdu(a,b)9;10 11define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {12; RV32I-LABEL: abd_ext_i8:13; RV32I: # %bb.0:14; RV32I-NEXT: zext.b a1, a115; RV32I-NEXT: zext.b a0, a016; RV32I-NEXT: sub a0, a0, a117; RV32I-NEXT: srai a1, a0, 3118; RV32I-NEXT: xor a0, a0, a119; RV32I-NEXT: sub a0, a0, a120; RV32I-NEXT: ret21;22; RV64I-LABEL: abd_ext_i8:23; RV64I: # %bb.0:24; RV64I-NEXT: zext.b a1, a125; RV64I-NEXT: zext.b a0, a026; RV64I-NEXT: sub a0, a0, a127; RV64I-NEXT: srai a1, a0, 6328; RV64I-NEXT: xor a0, a0, a129; RV64I-NEXT: sub a0, a0, a130; RV64I-NEXT: ret31;32; ZBB-LABEL: abd_ext_i8:33; ZBB: # %bb.0:34; ZBB-NEXT: zext.b a1, a135; ZBB-NEXT: zext.b a0, a036; ZBB-NEXT: minu a2, a0, a137; ZBB-NEXT: maxu a0, a0, a138; ZBB-NEXT: sub a0, a0, a239; ZBB-NEXT: ret40 %aext = zext i8 %a to i6441 %bext = zext i8 %b to i6442 %sub = sub i64 %aext, %bext43 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)44 %trunc = trunc i64 %abs to i845 ret i8 %trunc46}47 48define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {49; RV32I-LABEL: abd_ext_i8_i16:50; RV32I: # %bb.0:51; RV32I-NEXT: slli a1, a1, 1652; RV32I-NEXT: srli a1, a1, 1653; RV32I-NEXT: zext.b a0, a054; RV32I-NEXT: sub a0, a0, a155; RV32I-NEXT: srai a1, a0, 3156; RV32I-NEXT: xor a0, a0, a157; RV32I-NEXT: sub a0, a0, a158; RV32I-NEXT: ret59;60; RV64I-LABEL: abd_ext_i8_i16:61; RV64I: # %bb.0:62; RV64I-NEXT: slli a1, a1, 4863; RV64I-NEXT: srli a1, a1, 4864; RV64I-NEXT: zext.b a0, a065; RV64I-NEXT: sub a0, a0, a166; RV64I-NEXT: srai a1, a0, 6367; RV64I-NEXT: xor a0, a0, a168; RV64I-NEXT: sub a0, a0, a169; RV64I-NEXT: ret70;71; ZBB-LABEL: abd_ext_i8_i16:72; ZBB: # %bb.0:73; ZBB-NEXT: zext.h a1, a174; ZBB-NEXT: zext.b a0, a075; ZBB-NEXT: minu a2, a0, a176; ZBB-NEXT: maxu a0, a0, a177; ZBB-NEXT: sub a0, a0, a278; ZBB-NEXT: ret79 %aext = zext i8 %a to i6480 %bext = zext i16 %b to i6481 %sub = sub i64 %aext, %bext82 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)83 %trunc = trunc i64 %abs to i884 ret i8 %trunc85}86 87define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {88; RV32I-LABEL: abd_ext_i8_undef:89; RV32I: # %bb.0:90; RV32I-NEXT: zext.b a1, a191; RV32I-NEXT: zext.b a0, a092; RV32I-NEXT: sub a0, a0, a193; RV32I-NEXT: srai a1, a0, 3194; RV32I-NEXT: xor a0, a0, a195; RV32I-NEXT: sub a0, a0, a196; RV32I-NEXT: ret97;98; RV64I-LABEL: abd_ext_i8_undef:99; RV64I: # %bb.0:100; RV64I-NEXT: zext.b a1, a1101; RV64I-NEXT: zext.b a0, a0102; RV64I-NEXT: sub a0, a0, a1103; RV64I-NEXT: srai a1, a0, 63104; RV64I-NEXT: xor a0, a0, a1105; RV64I-NEXT: sub a0, a0, a1106; RV64I-NEXT: ret107;108; ZBB-LABEL: abd_ext_i8_undef:109; ZBB: # %bb.0:110; ZBB-NEXT: zext.b a1, a1111; ZBB-NEXT: zext.b a0, a0112; ZBB-NEXT: minu a2, a0, a1113; ZBB-NEXT: maxu a0, a0, a1114; ZBB-NEXT: sub a0, a0, a2115; ZBB-NEXT: ret116 %aext = zext i8 %a to i64117 %bext = zext i8 %b to i64118 %sub = sub i64 %aext, %bext119 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)120 %trunc = trunc i64 %abs to i8121 ret i8 %trunc122}123 124define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {125; RV32I-LABEL: abd_ext_i16:126; RV32I: # %bb.0:127; RV32I-NEXT: lui a2, 16128; RV32I-NEXT: addi a2, a2, -1129; RV32I-NEXT: and a1, a1, a2130; RV32I-NEXT: and a0, a0, a2131; RV32I-NEXT: sub a0, a0, a1132; RV32I-NEXT: srai a1, a0, 31133; RV32I-NEXT: xor a0, a0, a1134; RV32I-NEXT: sub a0, a0, a1135; RV32I-NEXT: ret136;137; RV64I-LABEL: abd_ext_i16:138; RV64I: # %bb.0:139; RV64I-NEXT: lui a2, 16140; RV64I-NEXT: addi a2, a2, -1141; RV64I-NEXT: and a1, a1, a2142; RV64I-NEXT: and a0, a0, a2143; RV64I-NEXT: sub a0, a0, a1144; RV64I-NEXT: srai a1, a0, 63145; RV64I-NEXT: xor a0, a0, a1146; RV64I-NEXT: sub a0, a0, a1147; RV64I-NEXT: ret148;149; ZBB-LABEL: abd_ext_i16:150; ZBB: # %bb.0:151; ZBB-NEXT: zext.h a1, a1152; ZBB-NEXT: zext.h a0, a0153; ZBB-NEXT: minu a2, a0, a1154; ZBB-NEXT: maxu a0, a0, a1155; ZBB-NEXT: sub a0, a0, a2156; ZBB-NEXT: ret157 %aext = zext i16 %a to i64158 %bext = zext i16 %b to i64159 %sub = sub i64 %aext, %bext160 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)161 %trunc = trunc i64 %abs to i16162 ret i16 %trunc163}164 165define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {166; RV32I-LABEL: abd_ext_i16_i32:167; RV32I: # %bb.0:168; RV32I-NEXT: slli a0, a0, 16169; RV32I-NEXT: srli a0, a0, 16170; RV32I-NEXT: bltu a1, a0, .LBB4_2171; RV32I-NEXT: # %bb.1:172; RV32I-NEXT: sub a0, a1, a0173; RV32I-NEXT: ret174; RV32I-NEXT: .LBB4_2:175; RV32I-NEXT: sub a0, a0, a1176; RV32I-NEXT: ret177;178; RV64I-LABEL: abd_ext_i16_i32:179; RV64I: # %bb.0:180; RV64I-NEXT: slli a1, a1, 32181; RV64I-NEXT: slli a0, a0, 48182; RV64I-NEXT: srli a1, a1, 32183; RV64I-NEXT: srli a0, a0, 48184; RV64I-NEXT: sub a0, a0, a1185; RV64I-NEXT: srai a1, a0, 63186; RV64I-NEXT: xor a0, a0, a1187; RV64I-NEXT: sub a0, a0, a1188; RV64I-NEXT: ret189;190; RV32ZBB-LABEL: abd_ext_i16_i32:191; RV32ZBB: # %bb.0:192; RV32ZBB-NEXT: zext.h a0, a0193; RV32ZBB-NEXT: minu a2, a0, a1194; RV32ZBB-NEXT: maxu a0, a0, a1195; RV32ZBB-NEXT: sub a0, a0, a2196; RV32ZBB-NEXT: ret197;198; RV64ZBB-LABEL: abd_ext_i16_i32:199; RV64ZBB: # %bb.0:200; RV64ZBB-NEXT: slli a1, a1, 32201; RV64ZBB-NEXT: zext.h a0, a0202; RV64ZBB-NEXT: srli a1, a1, 32203; RV64ZBB-NEXT: minu a2, a0, a1204; RV64ZBB-NEXT: maxu a0, a0, a1205; RV64ZBB-NEXT: sub a0, a0, a2206; RV64ZBB-NEXT: ret207 %aext = zext i16 %a to i64208 %bext = zext i32 %b to i64209 %sub = sub i64 %aext, %bext210 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)211 %trunc = trunc i64 %abs to i16212 ret i16 %trunc213}214 215define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {216; RV32I-LABEL: abd_ext_i16_undef:217; RV32I: # %bb.0:218; RV32I-NEXT: lui a2, 16219; RV32I-NEXT: addi a2, a2, -1220; RV32I-NEXT: and a1, a1, a2221; RV32I-NEXT: and a0, a0, a2222; RV32I-NEXT: sub a0, a0, a1223; RV32I-NEXT: srai a1, a0, 31224; RV32I-NEXT: xor a0, a0, a1225; RV32I-NEXT: sub a0, a0, a1226; RV32I-NEXT: ret227;228; RV64I-LABEL: abd_ext_i16_undef:229; RV64I: # %bb.0:230; RV64I-NEXT: lui a2, 16231; RV64I-NEXT: addi a2, a2, -1232; RV64I-NEXT: and a1, a1, a2233; RV64I-NEXT: and a0, a0, a2234; RV64I-NEXT: sub a0, a0, a1235; RV64I-NEXT: srai a1, a0, 63236; RV64I-NEXT: xor a0, a0, a1237; RV64I-NEXT: sub a0, a0, a1238; RV64I-NEXT: ret239;240; ZBB-LABEL: abd_ext_i16_undef:241; ZBB: # %bb.0:242; ZBB-NEXT: zext.h a1, a1243; ZBB-NEXT: zext.h a0, a0244; ZBB-NEXT: minu a2, a0, a1245; ZBB-NEXT: maxu a0, a0, a1246; ZBB-NEXT: sub a0, a0, a2247; ZBB-NEXT: ret248 %aext = zext i16 %a to i64249 %bext = zext i16 %b to i64250 %sub = sub i64 %aext, %bext251 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)252 %trunc = trunc i64 %abs to i16253 ret i16 %trunc254}255 256define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {257; RV32I-LABEL: abd_ext_i32:258; RV32I: # %bb.0:259; RV32I-NEXT: bltu a1, a0, .LBB6_2260; RV32I-NEXT: # %bb.1:261; RV32I-NEXT: sub a0, a1, a0262; RV32I-NEXT: ret263; RV32I-NEXT: .LBB6_2:264; RV32I-NEXT: sub a0, a0, a1265; RV32I-NEXT: ret266;267; RV64I-LABEL: abd_ext_i32:268; RV64I: # %bb.0:269; RV64I-NEXT: slli a1, a1, 32270; RV64I-NEXT: slli a0, a0, 32271; RV64I-NEXT: srli a1, a1, 32272; RV64I-NEXT: srli a0, a0, 32273; RV64I-NEXT: sub a0, a0, a1274; RV64I-NEXT: srai a1, a0, 63275; RV64I-NEXT: xor a0, a0, a1276; RV64I-NEXT: sub a0, a0, a1277; RV64I-NEXT: ret278;279; RV32ZBB-LABEL: abd_ext_i32:280; RV32ZBB: # %bb.0:281; RV32ZBB-NEXT: minu a2, a0, a1282; RV32ZBB-NEXT: maxu a0, a0, a1283; RV32ZBB-NEXT: sub a0, a0, a2284; RV32ZBB-NEXT: ret285;286; RV64ZBB-LABEL: abd_ext_i32:287; RV64ZBB: # %bb.0:288; RV64ZBB-NEXT: slli a1, a1, 32289; RV64ZBB-NEXT: slli a0, a0, 32290; RV64ZBB-NEXT: srli a1, a1, 32291; RV64ZBB-NEXT: srli a0, a0, 32292; RV64ZBB-NEXT: minu a2, a0, a1293; RV64ZBB-NEXT: maxu a0, a0, a1294; RV64ZBB-NEXT: sub a0, a0, a2295; RV64ZBB-NEXT: ret296 %aext = zext i32 %a to i64297 %bext = zext i32 %b to i64298 %sub = sub i64 %aext, %bext299 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)300 %trunc = trunc i64 %abs to i32301 ret i32 %trunc302}303 304define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {305; RV32I-LABEL: abd_ext_i32_i16:306; RV32I: # %bb.0:307; RV32I-NEXT: slli a1, a1, 16308; RV32I-NEXT: srli a1, a1, 16309; RV32I-NEXT: bltu a1, a0, .LBB7_2310; RV32I-NEXT: # %bb.1:311; RV32I-NEXT: sub a0, a1, a0312; RV32I-NEXT: ret313; RV32I-NEXT: .LBB7_2:314; RV32I-NEXT: sub a0, a0, a1315; RV32I-NEXT: ret316;317; RV64I-LABEL: abd_ext_i32_i16:318; RV64I: # %bb.0:319; RV64I-NEXT: slli a0, a0, 32320; RV64I-NEXT: slli a1, a1, 48321; RV64I-NEXT: srli a0, a0, 32322; RV64I-NEXT: srli a1, a1, 48323; RV64I-NEXT: sub a0, a0, a1324; RV64I-NEXT: srai a1, a0, 63325; RV64I-NEXT: xor a0, a0, a1326; RV64I-NEXT: sub a0, a0, a1327; RV64I-NEXT: ret328;329; RV32ZBB-LABEL: abd_ext_i32_i16:330; RV32ZBB: # %bb.0:331; RV32ZBB-NEXT: zext.h a1, a1332; RV32ZBB-NEXT: minu a2, a0, a1333; RV32ZBB-NEXT: maxu a0, a0, a1334; RV32ZBB-NEXT: sub a0, a0, a2335; RV32ZBB-NEXT: ret336;337; RV64ZBB-LABEL: abd_ext_i32_i16:338; RV64ZBB: # %bb.0:339; RV64ZBB-NEXT: slli a0, a0, 32340; RV64ZBB-NEXT: zext.h a1, a1341; RV64ZBB-NEXT: srli a0, a0, 32342; RV64ZBB-NEXT: minu a2, a0, a1343; RV64ZBB-NEXT: maxu a0, a0, a1344; RV64ZBB-NEXT: sub a0, a0, a2345; RV64ZBB-NEXT: ret346 %aext = zext i32 %a to i64347 %bext = zext i16 %b to i64348 %sub = sub i64 %aext, %bext349 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)350 %trunc = trunc i64 %abs to i32351 ret i32 %trunc352}353 354define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {355; RV32I-LABEL: abd_ext_i32_undef:356; RV32I: # %bb.0:357; RV32I-NEXT: bltu a1, a0, .LBB8_2358; RV32I-NEXT: # %bb.1:359; RV32I-NEXT: sub a0, a1, a0360; RV32I-NEXT: ret361; RV32I-NEXT: .LBB8_2:362; RV32I-NEXT: sub a0, a0, a1363; RV32I-NEXT: ret364;365; RV64I-LABEL: abd_ext_i32_undef:366; RV64I: # %bb.0:367; RV64I-NEXT: slli a1, a1, 32368; RV64I-NEXT: slli a0, a0, 32369; RV64I-NEXT: srli a1, a1, 32370; RV64I-NEXT: srli a0, a0, 32371; RV64I-NEXT: sub a0, a0, a1372; RV64I-NEXT: srai a1, a0, 63373; RV64I-NEXT: xor a0, a0, a1374; RV64I-NEXT: sub a0, a0, a1375; RV64I-NEXT: ret376;377; RV32ZBB-LABEL: abd_ext_i32_undef:378; RV32ZBB: # %bb.0:379; RV32ZBB-NEXT: minu a2, a0, a1380; RV32ZBB-NEXT: maxu a0, a0, a1381; RV32ZBB-NEXT: sub a0, a0, a2382; RV32ZBB-NEXT: ret383;384; RV64ZBB-LABEL: abd_ext_i32_undef:385; RV64ZBB: # %bb.0:386; RV64ZBB-NEXT: slli a1, a1, 32387; RV64ZBB-NEXT: slli a0, a0, 32388; RV64ZBB-NEXT: srli a1, a1, 32389; RV64ZBB-NEXT: srli a0, a0, 32390; RV64ZBB-NEXT: minu a2, a0, a1391; RV64ZBB-NEXT: maxu a0, a0, a1392; RV64ZBB-NEXT: sub a0, a0, a2393; RV64ZBB-NEXT: ret394 %aext = zext i32 %a to i64395 %bext = zext i32 %b to i64396 %sub = sub i64 %aext, %bext397 %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)398 %trunc = trunc i64 %abs to i32399 ret i32 %trunc400}401 402define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {403; RV32I-LABEL: abd_ext_i64:404; RV32I: # %bb.0:405; RV32I-NEXT: sltu a4, a0, a2406; RV32I-NEXT: sub a3, a1, a3407; RV32I-NEXT: sub a3, a3, a4408; RV32I-NEXT: sub a2, a0, a2409; RV32I-NEXT: beq a3, a1, .LBB9_2410; RV32I-NEXT: # %bb.1:411; RV32I-NEXT: sltu a0, a1, a3412; RV32I-NEXT: j .LBB9_3413; RV32I-NEXT: .LBB9_2:414; RV32I-NEXT: sltu a0, a0, a2415; RV32I-NEXT: .LBB9_3:416; RV32I-NEXT: neg a1, a0417; RV32I-NEXT: xor a2, a2, a1418; RV32I-NEXT: xor a3, a3, a1419; RV32I-NEXT: sltu a1, a2, a1420; RV32I-NEXT: add a3, a3, a0421; RV32I-NEXT: sub a1, a3, a1422; RV32I-NEXT: add a0, a2, a0423; RV32I-NEXT: ret424;425; RV64I-LABEL: abd_ext_i64:426; RV64I: # %bb.0:427; RV64I-NEXT: bltu a1, a0, .LBB9_2428; RV64I-NEXT: # %bb.1:429; RV64I-NEXT: sub a0, a1, a0430; RV64I-NEXT: ret431; RV64I-NEXT: .LBB9_2:432; RV64I-NEXT: sub a0, a0, a1433; RV64I-NEXT: ret434;435; RV32ZBB-LABEL: abd_ext_i64:436; RV32ZBB: # %bb.0:437; RV32ZBB-NEXT: sltu a4, a0, a2438; RV32ZBB-NEXT: sub a3, a1, a3439; RV32ZBB-NEXT: sub a3, a3, a4440; RV32ZBB-NEXT: sub a2, a0, a2441; RV32ZBB-NEXT: beq a3, a1, .LBB9_2442; RV32ZBB-NEXT: # %bb.1:443; RV32ZBB-NEXT: sltu a0, a1, a3444; RV32ZBB-NEXT: j .LBB9_3445; RV32ZBB-NEXT: .LBB9_2:446; RV32ZBB-NEXT: sltu a0, a0, a2447; RV32ZBB-NEXT: .LBB9_3:448; RV32ZBB-NEXT: neg a1, a0449; RV32ZBB-NEXT: xor a2, a2, a1450; RV32ZBB-NEXT: xor a3, a3, a1451; RV32ZBB-NEXT: sltu a1, a2, a1452; RV32ZBB-NEXT: add a3, a3, a0453; RV32ZBB-NEXT: sub a1, a3, a1454; RV32ZBB-NEXT: add a0, a2, a0455; RV32ZBB-NEXT: ret456;457; RV64ZBB-LABEL: abd_ext_i64:458; RV64ZBB: # %bb.0:459; RV64ZBB-NEXT: minu a2, a0, a1460; RV64ZBB-NEXT: maxu a0, a0, a1461; RV64ZBB-NEXT: sub a0, a0, a2462; RV64ZBB-NEXT: ret463 %aext = zext i64 %a to i128464 %bext = zext i64 %b to i128465 %sub = sub i128 %aext, %bext466 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)467 %trunc = trunc i128 %abs to i64468 ret i64 %trunc469}470 471define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {472; RV32I-LABEL: abd_ext_i64_undef:473; RV32I: # %bb.0:474; RV32I-NEXT: sltu a4, a0, a2475; RV32I-NEXT: sub a3, a1, a3476; RV32I-NEXT: sub a3, a3, a4477; RV32I-NEXT: sub a2, a0, a2478; RV32I-NEXT: beq a3, a1, .LBB10_2479; RV32I-NEXT: # %bb.1:480; RV32I-NEXT: sltu a0, a1, a3481; RV32I-NEXT: j .LBB10_3482; RV32I-NEXT: .LBB10_2:483; RV32I-NEXT: sltu a0, a0, a2484; RV32I-NEXT: .LBB10_3:485; RV32I-NEXT: neg a1, a0486; RV32I-NEXT: xor a2, a2, a1487; RV32I-NEXT: xor a3, a3, a1488; RV32I-NEXT: sltu a1, a2, a1489; RV32I-NEXT: add a3, a3, a0490; RV32I-NEXT: sub a1, a3, a1491; RV32I-NEXT: add a0, a2, a0492; RV32I-NEXT: ret493;494; RV64I-LABEL: abd_ext_i64_undef:495; RV64I: # %bb.0:496; RV64I-NEXT: bltu a1, a0, .LBB10_2497; RV64I-NEXT: # %bb.1:498; RV64I-NEXT: sub a0, a1, a0499; RV64I-NEXT: ret500; RV64I-NEXT: .LBB10_2:501; RV64I-NEXT: sub a0, a0, a1502; RV64I-NEXT: ret503;504; RV32ZBB-LABEL: abd_ext_i64_undef:505; RV32ZBB: # %bb.0:506; RV32ZBB-NEXT: sltu a4, a0, a2507; RV32ZBB-NEXT: sub a3, a1, a3508; RV32ZBB-NEXT: sub a3, a3, a4509; RV32ZBB-NEXT: sub a2, a0, a2510; RV32ZBB-NEXT: beq a3, a1, .LBB10_2511; RV32ZBB-NEXT: # %bb.1:512; RV32ZBB-NEXT: sltu a0, a1, a3513; RV32ZBB-NEXT: j .LBB10_3514; RV32ZBB-NEXT: .LBB10_2:515; RV32ZBB-NEXT: sltu a0, a0, a2516; RV32ZBB-NEXT: .LBB10_3:517; RV32ZBB-NEXT: neg a1, a0518; RV32ZBB-NEXT: xor a2, a2, a1519; RV32ZBB-NEXT: xor a3, a3, a1520; RV32ZBB-NEXT: sltu a1, a2, a1521; RV32ZBB-NEXT: add a3, a3, a0522; RV32ZBB-NEXT: sub a1, a3, a1523; RV32ZBB-NEXT: add a0, a2, a0524; RV32ZBB-NEXT: ret525;526; RV64ZBB-LABEL: abd_ext_i64_undef:527; RV64ZBB: # %bb.0:528; RV64ZBB-NEXT: minu a2, a0, a1529; RV64ZBB-NEXT: maxu a0, a0, a1530; RV64ZBB-NEXT: sub a0, a0, a2531; RV64ZBB-NEXT: ret532 %aext = zext i64 %a to i128533 %bext = zext i64 %b to i128534 %sub = sub i128 %aext, %bext535 %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)536 %trunc = trunc i128 %abs to i64537 ret i64 %trunc538}539 540define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {541; RV32I-LABEL: abd_ext_i128:542; RV32I: # %bb.0:543; RV32I-NEXT: lw a3, 0(a2)544; RV32I-NEXT: lw a5, 4(a2)545; RV32I-NEXT: lw a6, 8(a2)546; RV32I-NEXT: lw a7, 12(a2)547; RV32I-NEXT: lw a2, 8(a1)548; RV32I-NEXT: lw a4, 12(a1)549; RV32I-NEXT: lw t0, 0(a1)550; RV32I-NEXT: lw a1, 4(a1)551; RV32I-NEXT: sltu t1, a2, a6552; RV32I-NEXT: sub a7, a4, a7553; RV32I-NEXT: sltu t2, t0, a3554; RV32I-NEXT: sub a7, a7, t1555; RV32I-NEXT: mv t1, t2556; RV32I-NEXT: beq a1, a5, .LBB11_2557; RV32I-NEXT: # %bb.1:558; RV32I-NEXT: sltu t1, a1, a5559; RV32I-NEXT: .LBB11_2:560; RV32I-NEXT: sub t3, a2, a6561; RV32I-NEXT: sltu a6, t3, t1562; RV32I-NEXT: sub a6, a7, a6563; RV32I-NEXT: sub a7, t3, t1564; RV32I-NEXT: beq a6, a4, .LBB11_4565; RV32I-NEXT: # %bb.3:566; RV32I-NEXT: sltu t1, a4, a6567; RV32I-NEXT: j .LBB11_5568; RV32I-NEXT: .LBB11_4:569; RV32I-NEXT: sltu t1, a2, a7570; RV32I-NEXT: .LBB11_5:571; RV32I-NEXT: sub a5, a1, a5572; RV32I-NEXT: sub a5, a5, t2573; RV32I-NEXT: sub a3, t0, a3574; RV32I-NEXT: beq a5, a1, .LBB11_7575; RV32I-NEXT: # %bb.6:576; RV32I-NEXT: sltu a1, a1, a5577; RV32I-NEXT: j .LBB11_8578; RV32I-NEXT: .LBB11_7:579; RV32I-NEXT: sltu a1, t0, a3580; RV32I-NEXT: .LBB11_8:581; RV32I-NEXT: xor a4, a6, a4582; RV32I-NEXT: xor a2, a7, a2583; RV32I-NEXT: or a2, a2, a4584; RV32I-NEXT: beqz a2, .LBB11_10585; RV32I-NEXT: # %bb.9:586; RV32I-NEXT: mv a1, t1587; RV32I-NEXT: .LBB11_10:588; RV32I-NEXT: neg t0, a1589; RV32I-NEXT: xor a2, a7, t0590; RV32I-NEXT: xor a6, a6, t0591; RV32I-NEXT: xor a4, a3, t0592; RV32I-NEXT: sltu a3, a2, t0593; RV32I-NEXT: add a7, a6, a1594; RV32I-NEXT: sltu a6, a4, t0595; RV32I-NEXT: sub a3, a7, a3596; RV32I-NEXT: xor t1, a5, t0597; RV32I-NEXT: mv a7, a6598; RV32I-NEXT: beqz a5, .LBB11_12599; RV32I-NEXT: # %bb.11:600; RV32I-NEXT: sltu a7, t1, t0601; RV32I-NEXT: .LBB11_12:602; RV32I-NEXT: add a2, a2, a1603; RV32I-NEXT: add t1, t1, a1604; RV32I-NEXT: add a1, a4, a1605; RV32I-NEXT: sltu a4, a2, a7606; RV32I-NEXT: sub a2, a2, a7607; RV32I-NEXT: sub a5, t1, a6608; RV32I-NEXT: sub a3, a3, a4609; RV32I-NEXT: sw a1, 0(a0)610; RV32I-NEXT: sw a5, 4(a0)611; RV32I-NEXT: sw a2, 8(a0)612; RV32I-NEXT: sw a3, 12(a0)613; RV32I-NEXT: ret614;615; RV64I-LABEL: abd_ext_i128:616; RV64I: # %bb.0:617; RV64I-NEXT: sltu a4, a0, a2618; RV64I-NEXT: sub a3, a1, a3619; RV64I-NEXT: sub a3, a3, a4620; RV64I-NEXT: sub a2, a0, a2621; RV64I-NEXT: beq a3, a1, .LBB11_2622; RV64I-NEXT: # %bb.1:623; RV64I-NEXT: sltu a0, a1, a3624; RV64I-NEXT: j .LBB11_3625; RV64I-NEXT: .LBB11_2:626; RV64I-NEXT: sltu a0, a0, a2627; RV64I-NEXT: .LBB11_3:628; RV64I-NEXT: neg a1, a0629; RV64I-NEXT: xor a2, a2, a1630; RV64I-NEXT: xor a3, a3, a1631; RV64I-NEXT: sltu a1, a2, a1632; RV64I-NEXT: add a3, a3, a0633; RV64I-NEXT: sub a1, a3, a1634; RV64I-NEXT: add a0, a2, a0635; RV64I-NEXT: ret636;637; RV32ZBB-LABEL: abd_ext_i128:638; RV32ZBB: # %bb.0:639; RV32ZBB-NEXT: lw a3, 0(a2)640; RV32ZBB-NEXT: lw a5, 4(a2)641; RV32ZBB-NEXT: lw a6, 8(a2)642; RV32ZBB-NEXT: lw a7, 12(a2)643; RV32ZBB-NEXT: lw a2, 8(a1)644; RV32ZBB-NEXT: lw a4, 12(a1)645; RV32ZBB-NEXT: lw t0, 0(a1)646; RV32ZBB-NEXT: lw a1, 4(a1)647; RV32ZBB-NEXT: sltu t1, a2, a6648; RV32ZBB-NEXT: sub a7, a4, a7649; RV32ZBB-NEXT: sltu t2, t0, a3650; RV32ZBB-NEXT: sub a7, a7, t1651; RV32ZBB-NEXT: mv t1, t2652; RV32ZBB-NEXT: beq a1, a5, .LBB11_2653; RV32ZBB-NEXT: # %bb.1:654; RV32ZBB-NEXT: sltu t1, a1, a5655; RV32ZBB-NEXT: .LBB11_2:656; RV32ZBB-NEXT: sub t3, a2, a6657; RV32ZBB-NEXT: sltu a6, t3, t1658; RV32ZBB-NEXT: sub a6, a7, a6659; RV32ZBB-NEXT: sub a7, t3, t1660; RV32ZBB-NEXT: beq a6, a4, .LBB11_4661; RV32ZBB-NEXT: # %bb.3:662; RV32ZBB-NEXT: sltu t1, a4, a6663; RV32ZBB-NEXT: j .LBB11_5664; RV32ZBB-NEXT: .LBB11_4:665; RV32ZBB-NEXT: sltu t1, a2, a7666; RV32ZBB-NEXT: .LBB11_5:667; RV32ZBB-NEXT: sub a5, a1, a5668; RV32ZBB-NEXT: sub a5, a5, t2669; RV32ZBB-NEXT: sub a3, t0, a3670; RV32ZBB-NEXT: beq a5, a1, .LBB11_7671; RV32ZBB-NEXT: # %bb.6:672; RV32ZBB-NEXT: sltu a1, a1, a5673; RV32ZBB-NEXT: j .LBB11_8674; RV32ZBB-NEXT: .LBB11_7:675; RV32ZBB-NEXT: sltu a1, t0, a3676; RV32ZBB-NEXT: .LBB11_8:677; RV32ZBB-NEXT: xor a4, a6, a4678; RV32ZBB-NEXT: xor a2, a7, a2679; RV32ZBB-NEXT: or a2, a2, a4680; RV32ZBB-NEXT: beqz a2, .LBB11_10681; RV32ZBB-NEXT: # %bb.9:682; RV32ZBB-NEXT: mv a1, t1683; RV32ZBB-NEXT: .LBB11_10:684; RV32ZBB-NEXT: neg t0, a1685; RV32ZBB-NEXT: xor a2, a7, t0686; RV32ZBB-NEXT: xor a6, a6, t0687; RV32ZBB-NEXT: xor a4, a3, t0688; RV32ZBB-NEXT: sltu a3, a2, t0689; RV32ZBB-NEXT: add a7, a6, a1690; RV32ZBB-NEXT: sltu a6, a4, t0691; RV32ZBB-NEXT: sub a3, a7, a3692; RV32ZBB-NEXT: xor t1, a5, t0693; RV32ZBB-NEXT: mv a7, a6694; RV32ZBB-NEXT: beqz a5, .LBB11_12695; RV32ZBB-NEXT: # %bb.11:696; RV32ZBB-NEXT: sltu a7, t1, t0697; RV32ZBB-NEXT: .LBB11_12:698; RV32ZBB-NEXT: add a2, a2, a1699; RV32ZBB-NEXT: add t1, t1, a1700; RV32ZBB-NEXT: add a1, a4, a1701; RV32ZBB-NEXT: sltu a4, a2, a7702; RV32ZBB-NEXT: sub a2, a2, a7703; RV32ZBB-NEXT: sub a5, t1, a6704; RV32ZBB-NEXT: sub a3, a3, a4705; RV32ZBB-NEXT: sw a1, 0(a0)706; RV32ZBB-NEXT: sw a5, 4(a0)707; RV32ZBB-NEXT: sw a2, 8(a0)708; RV32ZBB-NEXT: sw a3, 12(a0)709; RV32ZBB-NEXT: ret710;711; RV64ZBB-LABEL: abd_ext_i128:712; RV64ZBB: # %bb.0:713; RV64ZBB-NEXT: sltu a4, a0, a2714; RV64ZBB-NEXT: sub a3, a1, a3715; RV64ZBB-NEXT: sub a3, a3, a4716; RV64ZBB-NEXT: sub a2, a0, a2717; RV64ZBB-NEXT: beq a3, a1, .LBB11_2718; RV64ZBB-NEXT: # %bb.1:719; RV64ZBB-NEXT: sltu a0, a1, a3720; RV64ZBB-NEXT: j .LBB11_3721; RV64ZBB-NEXT: .LBB11_2:722; RV64ZBB-NEXT: sltu a0, a0, a2723; RV64ZBB-NEXT: .LBB11_3:724; RV64ZBB-NEXT: neg a1, a0725; RV64ZBB-NEXT: xor a2, a2, a1726; RV64ZBB-NEXT: xor a3, a3, a1727; RV64ZBB-NEXT: sltu a1, a2, a1728; RV64ZBB-NEXT: add a3, a3, a0729; RV64ZBB-NEXT: sub a1, a3, a1730; RV64ZBB-NEXT: add a0, a2, a0731; RV64ZBB-NEXT: ret732 %aext = zext i128 %a to i256733 %bext = zext i128 %b to i256734 %sub = sub i256 %aext, %bext735 %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)736 %trunc = trunc i256 %abs to i128737 ret i128 %trunc738}739 740define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {741; RV32I-LABEL: abd_ext_i128_undef:742; RV32I: # %bb.0:743; RV32I-NEXT: lw a3, 0(a2)744; RV32I-NEXT: lw a5, 4(a2)745; RV32I-NEXT: lw a6, 8(a2)746; RV32I-NEXT: lw a7, 12(a2)747; RV32I-NEXT: lw a2, 8(a1)748; RV32I-NEXT: lw a4, 12(a1)749; RV32I-NEXT: lw t0, 0(a1)750; RV32I-NEXT: lw a1, 4(a1)751; RV32I-NEXT: sltu t1, a2, a6752; RV32I-NEXT: sub a7, a4, a7753; RV32I-NEXT: sltu t2, t0, a3754; RV32I-NEXT: sub a7, a7, t1755; RV32I-NEXT: mv t1, t2756; RV32I-NEXT: beq a1, a5, .LBB12_2757; RV32I-NEXT: # %bb.1:758; RV32I-NEXT: sltu t1, a1, a5759; RV32I-NEXT: .LBB12_2:760; RV32I-NEXT: sub t3, a2, a6761; RV32I-NEXT: sltu a6, t3, t1762; RV32I-NEXT: sub a6, a7, a6763; RV32I-NEXT: sub a7, t3, t1764; RV32I-NEXT: beq a6, a4, .LBB12_4765; RV32I-NEXT: # %bb.3:766; RV32I-NEXT: sltu t1, a4, a6767; RV32I-NEXT: j .LBB12_5768; RV32I-NEXT: .LBB12_4:769; RV32I-NEXT: sltu t1, a2, a7770; RV32I-NEXT: .LBB12_5:771; RV32I-NEXT: sub a5, a1, a5772; RV32I-NEXT: sub a5, a5, t2773; RV32I-NEXT: sub a3, t0, a3774; RV32I-NEXT: beq a5, a1, .LBB12_7775; RV32I-NEXT: # %bb.6:776; RV32I-NEXT: sltu a1, a1, a5777; RV32I-NEXT: j .LBB12_8778; RV32I-NEXT: .LBB12_7:779; RV32I-NEXT: sltu a1, t0, a3780; RV32I-NEXT: .LBB12_8:781; RV32I-NEXT: xor a4, a6, a4782; RV32I-NEXT: xor a2, a7, a2783; RV32I-NEXT: or a2, a2, a4784; RV32I-NEXT: beqz a2, .LBB12_10785; RV32I-NEXT: # %bb.9:786; RV32I-NEXT: mv a1, t1787; RV32I-NEXT: .LBB12_10:788; RV32I-NEXT: neg t0, a1789; RV32I-NEXT: xor a2, a7, t0790; RV32I-NEXT: xor a6, a6, t0791; RV32I-NEXT: xor a4, a3, t0792; RV32I-NEXT: sltu a3, a2, t0793; RV32I-NEXT: add a7, a6, a1794; RV32I-NEXT: sltu a6, a4, t0795; RV32I-NEXT: sub a3, a7, a3796; RV32I-NEXT: xor t1, a5, t0797; RV32I-NEXT: mv a7, a6798; RV32I-NEXT: beqz a5, .LBB12_12799; RV32I-NEXT: # %bb.11:800; RV32I-NEXT: sltu a7, t1, t0801; RV32I-NEXT: .LBB12_12:802; RV32I-NEXT: add a2, a2, a1803; RV32I-NEXT: add t1, t1, a1804; RV32I-NEXT: add a1, a4, a1805; RV32I-NEXT: sltu a4, a2, a7806; RV32I-NEXT: sub a2, a2, a7807; RV32I-NEXT: sub a5, t1, a6808; RV32I-NEXT: sub a3, a3, a4809; RV32I-NEXT: sw a1, 0(a0)810; RV32I-NEXT: sw a5, 4(a0)811; RV32I-NEXT: sw a2, 8(a0)812; RV32I-NEXT: sw a3, 12(a0)813; RV32I-NEXT: ret814;815; RV64I-LABEL: abd_ext_i128_undef:816; RV64I: # %bb.0:817; RV64I-NEXT: sltu a4, a0, a2818; RV64I-NEXT: sub a3, a1, a3819; RV64I-NEXT: sub a3, a3, a4820; RV64I-NEXT: sub a2, a0, a2821; RV64I-NEXT: beq a3, a1, .LBB12_2822; RV64I-NEXT: # %bb.1:823; RV64I-NEXT: sltu a0, a1, a3824; RV64I-NEXT: j .LBB12_3825; RV64I-NEXT: .LBB12_2:826; RV64I-NEXT: sltu a0, a0, a2827; RV64I-NEXT: .LBB12_3:828; RV64I-NEXT: neg a1, a0829; RV64I-NEXT: xor a2, a2, a1830; RV64I-NEXT: xor a3, a3, a1831; RV64I-NEXT: sltu a1, a2, a1832; RV64I-NEXT: add a3, a3, a0833; RV64I-NEXT: sub a1, a3, a1834; RV64I-NEXT: add a0, a2, a0835; RV64I-NEXT: ret836;837; RV32ZBB-LABEL: abd_ext_i128_undef:838; RV32ZBB: # %bb.0:839; RV32ZBB-NEXT: lw a3, 0(a2)840; RV32ZBB-NEXT: lw a5, 4(a2)841; RV32ZBB-NEXT: lw a6, 8(a2)842; RV32ZBB-NEXT: lw a7, 12(a2)843; RV32ZBB-NEXT: lw a2, 8(a1)844; RV32ZBB-NEXT: lw a4, 12(a1)845; RV32ZBB-NEXT: lw t0, 0(a1)846; RV32ZBB-NEXT: lw a1, 4(a1)847; RV32ZBB-NEXT: sltu t1, a2, a6848; RV32ZBB-NEXT: sub a7, a4, a7849; RV32ZBB-NEXT: sltu t2, t0, a3850; RV32ZBB-NEXT: sub a7, a7, t1851; RV32ZBB-NEXT: mv t1, t2852; RV32ZBB-NEXT: beq a1, a5, .LBB12_2853; RV32ZBB-NEXT: # %bb.1:854; RV32ZBB-NEXT: sltu t1, a1, a5855; RV32ZBB-NEXT: .LBB12_2:856; RV32ZBB-NEXT: sub t3, a2, a6857; RV32ZBB-NEXT: sltu a6, t3, t1858; RV32ZBB-NEXT: sub a6, a7, a6859; RV32ZBB-NEXT: sub a7, t3, t1860; RV32ZBB-NEXT: beq a6, a4, .LBB12_4861; RV32ZBB-NEXT: # %bb.3:862; RV32ZBB-NEXT: sltu t1, a4, a6863; RV32ZBB-NEXT: j .LBB12_5864; RV32ZBB-NEXT: .LBB12_4:865; RV32ZBB-NEXT: sltu t1, a2, a7866; RV32ZBB-NEXT: .LBB12_5:867; RV32ZBB-NEXT: sub a5, a1, a5868; RV32ZBB-NEXT: sub a5, a5, t2869; RV32ZBB-NEXT: sub a3, t0, a3870; RV32ZBB-NEXT: beq a5, a1, .LBB12_7871; RV32ZBB-NEXT: # %bb.6:872; RV32ZBB-NEXT: sltu a1, a1, a5873; RV32ZBB-NEXT: j .LBB12_8874; RV32ZBB-NEXT: .LBB12_7:875; RV32ZBB-NEXT: sltu a1, t0, a3876; RV32ZBB-NEXT: .LBB12_8:877; RV32ZBB-NEXT: xor a4, a6, a4878; RV32ZBB-NEXT: xor a2, a7, a2879; RV32ZBB-NEXT: or a2, a2, a4880; RV32ZBB-NEXT: beqz a2, .LBB12_10881; RV32ZBB-NEXT: # %bb.9:882; RV32ZBB-NEXT: mv a1, t1883; RV32ZBB-NEXT: .LBB12_10:884; RV32ZBB-NEXT: neg t0, a1885; RV32ZBB-NEXT: xor a2, a7, t0886; RV32ZBB-NEXT: xor a6, a6, t0887; RV32ZBB-NEXT: xor a4, a3, t0888; RV32ZBB-NEXT: sltu a3, a2, t0889; RV32ZBB-NEXT: add a7, a6, a1890; RV32ZBB-NEXT: sltu a6, a4, t0891; RV32ZBB-NEXT: sub a3, a7, a3892; RV32ZBB-NEXT: xor t1, a5, t0893; RV32ZBB-NEXT: mv a7, a6894; RV32ZBB-NEXT: beqz a5, .LBB12_12895; RV32ZBB-NEXT: # %bb.11:896; RV32ZBB-NEXT: sltu a7, t1, t0897; RV32ZBB-NEXT: .LBB12_12:898; RV32ZBB-NEXT: add a2, a2, a1899; RV32ZBB-NEXT: add t1, t1, a1900; RV32ZBB-NEXT: add a1, a4, a1901; RV32ZBB-NEXT: sltu a4, a2, a7902; RV32ZBB-NEXT: sub a2, a2, a7903; RV32ZBB-NEXT: sub a5, t1, a6904; RV32ZBB-NEXT: sub a3, a3, a4905; RV32ZBB-NEXT: sw a1, 0(a0)906; RV32ZBB-NEXT: sw a5, 4(a0)907; RV32ZBB-NEXT: sw a2, 8(a0)908; RV32ZBB-NEXT: sw a3, 12(a0)909; RV32ZBB-NEXT: ret910;911; RV64ZBB-LABEL: abd_ext_i128_undef:912; RV64ZBB: # %bb.0:913; RV64ZBB-NEXT: sltu a4, a0, a2914; RV64ZBB-NEXT: sub a3, a1, a3915; RV64ZBB-NEXT: sub a3, a3, a4916; RV64ZBB-NEXT: sub a2, a0, a2917; RV64ZBB-NEXT: beq a3, a1, .LBB12_2918; RV64ZBB-NEXT: # %bb.1:919; RV64ZBB-NEXT: sltu a0, a1, a3920; RV64ZBB-NEXT: j .LBB12_3921; RV64ZBB-NEXT: .LBB12_2:922; RV64ZBB-NEXT: sltu a0, a0, a2923; RV64ZBB-NEXT: .LBB12_3:924; RV64ZBB-NEXT: neg a1, a0925; RV64ZBB-NEXT: xor a2, a2, a1926; RV64ZBB-NEXT: xor a3, a3, a1927; RV64ZBB-NEXT: sltu a1, a2, a1928; RV64ZBB-NEXT: add a3, a3, a0929; RV64ZBB-NEXT: sub a1, a3, a1930; RV64ZBB-NEXT: add a0, a2, a0931; RV64ZBB-NEXT: ret932 %aext = zext i128 %a to i256933 %bext = zext i128 %b to i256934 %sub = sub i256 %aext, %bext935 %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)936 %trunc = trunc i256 %abs to i128937 ret i128 %trunc938}939 940;941; sub(umax(a,b),umin(a,b)) -> abdu(a,b)942;943 944define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {945; RV32I-LABEL: abd_minmax_i8:946; RV32I: # %bb.0:947; RV32I-NEXT: zext.b a1, a1948; RV32I-NEXT: zext.b a0, a0949; RV32I-NEXT: sub a0, a0, a1950; RV32I-NEXT: srai a1, a0, 31951; RV32I-NEXT: xor a0, a0, a1952; RV32I-NEXT: sub a0, a0, a1953; RV32I-NEXT: ret954;955; RV64I-LABEL: abd_minmax_i8:956; RV64I: # %bb.0:957; RV64I-NEXT: zext.b a1, a1958; RV64I-NEXT: zext.b a0, a0959; RV64I-NEXT: sub a0, a0, a1960; RV64I-NEXT: srai a1, a0, 63961; RV64I-NEXT: xor a0, a0, a1962; RV64I-NEXT: sub a0, a0, a1963; RV64I-NEXT: ret964;965; ZBB-LABEL: abd_minmax_i8:966; ZBB: # %bb.0:967; ZBB-NEXT: zext.b a1, a1968; ZBB-NEXT: zext.b a0, a0969; ZBB-NEXT: minu a2, a0, a1970; ZBB-NEXT: maxu a0, a0, a1971; ZBB-NEXT: sub a0, a0, a2972; ZBB-NEXT: ret973 %min = call i8 @llvm.umin.i8(i8 %a, i8 %b)974 %max = call i8 @llvm.umax.i8(i8 %a, i8 %b)975 %sub = sub i8 %max, %min976 ret i8 %sub977}978 979define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {980; RV32I-LABEL: abd_minmax_i16:981; RV32I: # %bb.0:982; RV32I-NEXT: lui a2, 16983; RV32I-NEXT: addi a2, a2, -1984; RV32I-NEXT: and a1, a1, a2985; RV32I-NEXT: and a0, a0, a2986; RV32I-NEXT: sub a0, a0, a1987; RV32I-NEXT: srai a1, a0, 31988; RV32I-NEXT: xor a0, a0, a1989; RV32I-NEXT: sub a0, a0, a1990; RV32I-NEXT: ret991;992; RV64I-LABEL: abd_minmax_i16:993; RV64I: # %bb.0:994; RV64I-NEXT: lui a2, 16995; RV64I-NEXT: addi a2, a2, -1996; RV64I-NEXT: and a1, a1, a2997; RV64I-NEXT: and a0, a0, a2998; RV64I-NEXT: sub a0, a0, a1999; RV64I-NEXT: srai a1, a0, 631000; RV64I-NEXT: xor a0, a0, a11001; RV64I-NEXT: sub a0, a0, a11002; RV64I-NEXT: ret1003;1004; ZBB-LABEL: abd_minmax_i16:1005; ZBB: # %bb.0:1006; ZBB-NEXT: zext.h a1, a11007; ZBB-NEXT: zext.h a0, a01008; ZBB-NEXT: minu a2, a0, a11009; ZBB-NEXT: maxu a0, a0, a11010; ZBB-NEXT: sub a0, a0, a21011; ZBB-NEXT: ret1012 %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)1013 %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)1014 %sub = sub i16 %max, %min1015 ret i16 %sub1016}1017 1018define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {1019; RV32I-LABEL: abd_minmax_i32:1020; RV32I: # %bb.0:1021; RV32I-NEXT: bltu a1, a0, .LBB15_21022; RV32I-NEXT: # %bb.1:1023; RV32I-NEXT: sub a0, a1, a01024; RV32I-NEXT: ret1025; RV32I-NEXT: .LBB15_2:1026; RV32I-NEXT: sub a0, a0, a11027; RV32I-NEXT: ret1028;1029; RV64I-LABEL: abd_minmax_i32:1030; RV64I: # %bb.0:1031; RV64I-NEXT: slli a1, a1, 321032; RV64I-NEXT: slli a0, a0, 321033; RV64I-NEXT: srli a1, a1, 321034; RV64I-NEXT: srli a0, a0, 321035; RV64I-NEXT: sub a0, a0, a11036; RV64I-NEXT: srai a1, a0, 631037; RV64I-NEXT: xor a0, a0, a11038; RV64I-NEXT: sub a0, a0, a11039; RV64I-NEXT: ret1040;1041; RV32ZBB-LABEL: abd_minmax_i32:1042; RV32ZBB: # %bb.0:1043; RV32ZBB-NEXT: minu a2, a0, a11044; RV32ZBB-NEXT: maxu a0, a0, a11045; RV32ZBB-NEXT: sub a0, a0, a21046; RV32ZBB-NEXT: ret1047;1048; RV64ZBB-LABEL: abd_minmax_i32:1049; RV64ZBB: # %bb.0:1050; RV64ZBB-NEXT: slli a1, a1, 321051; RV64ZBB-NEXT: slli a0, a0, 321052; RV64ZBB-NEXT: srli a1, a1, 321053; RV64ZBB-NEXT: srli a0, a0, 321054; RV64ZBB-NEXT: minu a2, a0, a11055; RV64ZBB-NEXT: maxu a0, a0, a11056; RV64ZBB-NEXT: sub a0, a0, a21057; RV64ZBB-NEXT: ret1058 %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)1059 %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)1060 %sub = sub i32 %max, %min1061 ret i32 %sub1062}1063 1064define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {1065; RV32I-LABEL: abd_minmax_i64:1066; RV32I: # %bb.0:1067; RV32I-NEXT: sltu a4, a0, a21068; RV32I-NEXT: sub a3, a1, a31069; RV32I-NEXT: sub a3, a3, a41070; RV32I-NEXT: sub a2, a0, a21071; RV32I-NEXT: beq a3, a1, .LBB16_21072; RV32I-NEXT: # %bb.1:1073; RV32I-NEXT: sltu a0, a1, a31074; RV32I-NEXT: j .LBB16_31075; RV32I-NEXT: .LBB16_2:1076; RV32I-NEXT: sltu a0, a0, a21077; RV32I-NEXT: .LBB16_3:1078; RV32I-NEXT: neg a1, a01079; RV32I-NEXT: xor a2, a2, a11080; RV32I-NEXT: xor a3, a3, a11081; RV32I-NEXT: sltu a1, a2, a11082; RV32I-NEXT: add a3, a3, a01083; RV32I-NEXT: sub a1, a3, a11084; RV32I-NEXT: add a0, a2, a01085; RV32I-NEXT: ret1086;1087; RV64I-LABEL: abd_minmax_i64:1088; RV64I: # %bb.0:1089; RV64I-NEXT: bltu a1, a0, .LBB16_21090; RV64I-NEXT: # %bb.1:1091; RV64I-NEXT: sub a0, a1, a01092; RV64I-NEXT: ret1093; RV64I-NEXT: .LBB16_2:1094; RV64I-NEXT: sub a0, a0, a11095; RV64I-NEXT: ret1096;1097; RV32ZBB-LABEL: abd_minmax_i64:1098; RV32ZBB: # %bb.0:1099; RV32ZBB-NEXT: sltu a4, a0, a21100; RV32ZBB-NEXT: sub a3, a1, a31101; RV32ZBB-NEXT: sub a3, a3, a41102; RV32ZBB-NEXT: sub a2, a0, a21103; RV32ZBB-NEXT: beq a3, a1, .LBB16_21104; RV32ZBB-NEXT: # %bb.1:1105; RV32ZBB-NEXT: sltu a0, a1, a31106; RV32ZBB-NEXT: j .LBB16_31107; RV32ZBB-NEXT: .LBB16_2:1108; RV32ZBB-NEXT: sltu a0, a0, a21109; RV32ZBB-NEXT: .LBB16_3:1110; RV32ZBB-NEXT: neg a1, a01111; RV32ZBB-NEXT: xor a2, a2, a11112; RV32ZBB-NEXT: xor a3, a3, a11113; RV32ZBB-NEXT: sltu a1, a2, a11114; RV32ZBB-NEXT: add a3, a3, a01115; RV32ZBB-NEXT: sub a1, a3, a11116; RV32ZBB-NEXT: add a0, a2, a01117; RV32ZBB-NEXT: ret1118;1119; RV64ZBB-LABEL: abd_minmax_i64:1120; RV64ZBB: # %bb.0:1121; RV64ZBB-NEXT: minu a2, a0, a11122; RV64ZBB-NEXT: maxu a0, a0, a11123; RV64ZBB-NEXT: sub a0, a0, a21124; RV64ZBB-NEXT: ret1125 %min = call i64 @llvm.umin.i64(i64 %a, i64 %b)1126 %max = call i64 @llvm.umax.i64(i64 %a, i64 %b)1127 %sub = sub i64 %max, %min1128 ret i64 %sub1129}1130 1131define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {1132; RV32I-LABEL: abd_minmax_i128:1133; RV32I: # %bb.0:1134; RV32I-NEXT: lw a3, 0(a2)1135; RV32I-NEXT: lw a5, 4(a2)1136; RV32I-NEXT: lw a6, 8(a2)1137; RV32I-NEXT: lw a7, 12(a2)1138; RV32I-NEXT: lw a2, 8(a1)1139; RV32I-NEXT: lw a4, 12(a1)1140; RV32I-NEXT: lw t0, 0(a1)1141; RV32I-NEXT: lw a1, 4(a1)1142; RV32I-NEXT: sltu t1, a2, a61143; RV32I-NEXT: sub a7, a4, a71144; RV32I-NEXT: sltu t2, t0, a31145; RV32I-NEXT: sub a7, a7, t11146; RV32I-NEXT: mv t1, t21147; RV32I-NEXT: beq a1, a5, .LBB17_21148; RV32I-NEXT: # %bb.1:1149; RV32I-NEXT: sltu t1, a1, a51150; RV32I-NEXT: .LBB17_2:1151; RV32I-NEXT: sub t3, a2, a61152; RV32I-NEXT: sltu a6, t3, t11153; RV32I-NEXT: sub a6, a7, a61154; RV32I-NEXT: sub a7, t3, t11155; RV32I-NEXT: beq a6, a4, .LBB17_41156; RV32I-NEXT: # %bb.3:1157; RV32I-NEXT: sltu t1, a4, a61158; RV32I-NEXT: j .LBB17_51159; RV32I-NEXT: .LBB17_4:1160; RV32I-NEXT: sltu t1, a2, a71161; RV32I-NEXT: .LBB17_5:1162; RV32I-NEXT: sub a5, a1, a51163; RV32I-NEXT: sub a5, a5, t21164; RV32I-NEXT: sub a3, t0, a31165; RV32I-NEXT: beq a5, a1, .LBB17_71166; RV32I-NEXT: # %bb.6:1167; RV32I-NEXT: sltu a1, a1, a51168; RV32I-NEXT: j .LBB17_81169; RV32I-NEXT: .LBB17_7:1170; RV32I-NEXT: sltu a1, t0, a31171; RV32I-NEXT: .LBB17_8:1172; RV32I-NEXT: xor a4, a6, a41173; RV32I-NEXT: xor a2, a7, a21174; RV32I-NEXT: or a2, a2, a41175; RV32I-NEXT: beqz a2, .LBB17_101176; RV32I-NEXT: # %bb.9:1177; RV32I-NEXT: mv a1, t11178; RV32I-NEXT: .LBB17_10:1179; RV32I-NEXT: neg t0, a11180; RV32I-NEXT: xor a2, a7, t01181; RV32I-NEXT: xor a6, a6, t01182; RV32I-NEXT: xor a4, a3, t01183; RV32I-NEXT: sltu a3, a2, t01184; RV32I-NEXT: add a7, a6, a11185; RV32I-NEXT: sltu a6, a4, t01186; RV32I-NEXT: sub a3, a7, a31187; RV32I-NEXT: xor t1, a5, t01188; RV32I-NEXT: mv a7, a61189; RV32I-NEXT: beqz a5, .LBB17_121190; RV32I-NEXT: # %bb.11:1191; RV32I-NEXT: sltu a7, t1, t01192; RV32I-NEXT: .LBB17_12:1193; RV32I-NEXT: add a2, a2, a11194; RV32I-NEXT: add t1, t1, a11195; RV32I-NEXT: add a1, a4, a11196; RV32I-NEXT: sltu a4, a2, a71197; RV32I-NEXT: sub a2, a2, a71198; RV32I-NEXT: sub a5, t1, a61199; RV32I-NEXT: sub a3, a3, a41200; RV32I-NEXT: sw a1, 0(a0)1201; RV32I-NEXT: sw a5, 4(a0)1202; RV32I-NEXT: sw a2, 8(a0)1203; RV32I-NEXT: sw a3, 12(a0)1204; RV32I-NEXT: ret1205;1206; RV64I-LABEL: abd_minmax_i128:1207; RV64I: # %bb.0:1208; RV64I-NEXT: sltu a4, a0, a21209; RV64I-NEXT: sub a3, a1, a31210; RV64I-NEXT: sub a3, a3, a41211; RV64I-NEXT: sub a2, a0, a21212; RV64I-NEXT: beq a3, a1, .LBB17_21213; RV64I-NEXT: # %bb.1:1214; RV64I-NEXT: sltu a0, a1, a31215; RV64I-NEXT: j .LBB17_31216; RV64I-NEXT: .LBB17_2:1217; RV64I-NEXT: sltu a0, a0, a21218; RV64I-NEXT: .LBB17_3:1219; RV64I-NEXT: neg a1, a01220; RV64I-NEXT: xor a2, a2, a11221; RV64I-NEXT: xor a3, a3, a11222; RV64I-NEXT: sltu a1, a2, a11223; RV64I-NEXT: add a3, a3, a01224; RV64I-NEXT: sub a1, a3, a11225; RV64I-NEXT: add a0, a2, a01226; RV64I-NEXT: ret1227;1228; RV32ZBB-LABEL: abd_minmax_i128:1229; RV32ZBB: # %bb.0:1230; RV32ZBB-NEXT: lw a3, 0(a2)1231; RV32ZBB-NEXT: lw a5, 4(a2)1232; RV32ZBB-NEXT: lw a6, 8(a2)1233; RV32ZBB-NEXT: lw a7, 12(a2)1234; RV32ZBB-NEXT: lw a2, 8(a1)1235; RV32ZBB-NEXT: lw a4, 12(a1)1236; RV32ZBB-NEXT: lw t0, 0(a1)1237; RV32ZBB-NEXT: lw a1, 4(a1)1238; RV32ZBB-NEXT: sltu t1, a2, a61239; RV32ZBB-NEXT: sub a7, a4, a71240; RV32ZBB-NEXT: sltu t2, t0, a31241; RV32ZBB-NEXT: sub a7, a7, t11242; RV32ZBB-NEXT: mv t1, t21243; RV32ZBB-NEXT: beq a1, a5, .LBB17_21244; RV32ZBB-NEXT: # %bb.1:1245; RV32ZBB-NEXT: sltu t1, a1, a51246; RV32ZBB-NEXT: .LBB17_2:1247; RV32ZBB-NEXT: sub t3, a2, a61248; RV32ZBB-NEXT: sltu a6, t3, t11249; RV32ZBB-NEXT: sub a6, a7, a61250; RV32ZBB-NEXT: sub a7, t3, t11251; RV32ZBB-NEXT: beq a6, a4, .LBB17_41252; RV32ZBB-NEXT: # %bb.3:1253; RV32ZBB-NEXT: sltu t1, a4, a61254; RV32ZBB-NEXT: j .LBB17_51255; RV32ZBB-NEXT: .LBB17_4:1256; RV32ZBB-NEXT: sltu t1, a2, a71257; RV32ZBB-NEXT: .LBB17_5:1258; RV32ZBB-NEXT: sub a5, a1, a51259; RV32ZBB-NEXT: sub a5, a5, t21260; RV32ZBB-NEXT: sub a3, t0, a31261; RV32ZBB-NEXT: beq a5, a1, .LBB17_71262; RV32ZBB-NEXT: # %bb.6:1263; RV32ZBB-NEXT: sltu a1, a1, a51264; RV32ZBB-NEXT: j .LBB17_81265; RV32ZBB-NEXT: .LBB17_7:1266; RV32ZBB-NEXT: sltu a1, t0, a31267; RV32ZBB-NEXT: .LBB17_8:1268; RV32ZBB-NEXT: xor a4, a6, a41269; RV32ZBB-NEXT: xor a2, a7, a21270; RV32ZBB-NEXT: or a2, a2, a41271; RV32ZBB-NEXT: beqz a2, .LBB17_101272; RV32ZBB-NEXT: # %bb.9:1273; RV32ZBB-NEXT: mv a1, t11274; RV32ZBB-NEXT: .LBB17_10:1275; RV32ZBB-NEXT: neg t0, a11276; RV32ZBB-NEXT: xor a2, a7, t01277; RV32ZBB-NEXT: xor a6, a6, t01278; RV32ZBB-NEXT: xor a4, a3, t01279; RV32ZBB-NEXT: sltu a3, a2, t01280; RV32ZBB-NEXT: add a7, a6, a11281; RV32ZBB-NEXT: sltu a6, a4, t01282; RV32ZBB-NEXT: sub a3, a7, a31283; RV32ZBB-NEXT: xor t1, a5, t01284; RV32ZBB-NEXT: mv a7, a61285; RV32ZBB-NEXT: beqz a5, .LBB17_121286; RV32ZBB-NEXT: # %bb.11:1287; RV32ZBB-NEXT: sltu a7, t1, t01288; RV32ZBB-NEXT: .LBB17_12:1289; RV32ZBB-NEXT: add a2, a2, a11290; RV32ZBB-NEXT: add t1, t1, a11291; RV32ZBB-NEXT: add a1, a4, a11292; RV32ZBB-NEXT: sltu a4, a2, a71293; RV32ZBB-NEXT: sub a2, a2, a71294; RV32ZBB-NEXT: sub a5, t1, a61295; RV32ZBB-NEXT: sub a3, a3, a41296; RV32ZBB-NEXT: sw a1, 0(a0)1297; RV32ZBB-NEXT: sw a5, 4(a0)1298; RV32ZBB-NEXT: sw a2, 8(a0)1299; RV32ZBB-NEXT: sw a3, 12(a0)1300; RV32ZBB-NEXT: ret1301;1302; RV64ZBB-LABEL: abd_minmax_i128:1303; RV64ZBB: # %bb.0:1304; RV64ZBB-NEXT: sltu a4, a0, a21305; RV64ZBB-NEXT: sub a3, a1, a31306; RV64ZBB-NEXT: sub a3, a3, a41307; RV64ZBB-NEXT: sub a2, a0, a21308; RV64ZBB-NEXT: beq a3, a1, .LBB17_21309; RV64ZBB-NEXT: # %bb.1:1310; RV64ZBB-NEXT: sltu a0, a1, a31311; RV64ZBB-NEXT: j .LBB17_31312; RV64ZBB-NEXT: .LBB17_2:1313; RV64ZBB-NEXT: sltu a0, a0, a21314; RV64ZBB-NEXT: .LBB17_3:1315; RV64ZBB-NEXT: neg a1, a01316; RV64ZBB-NEXT: xor a2, a2, a11317; RV64ZBB-NEXT: xor a3, a3, a11318; RV64ZBB-NEXT: sltu a1, a2, a11319; RV64ZBB-NEXT: add a3, a3, a01320; RV64ZBB-NEXT: sub a1, a3, a11321; RV64ZBB-NEXT: add a0, a2, a01322; RV64ZBB-NEXT: ret1323 %min = call i128 @llvm.umin.i128(i128 %a, i128 %b)1324 %max = call i128 @llvm.umax.i128(i128 %a, i128 %b)1325 %sub = sub i128 %max, %min1326 ret i128 %sub1327}1328 1329;1330; select(icmp(a,b),sub(a,b),sub(b,a)) -> abdu(a,b)1331;1332 1333define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {1334; RV32I-LABEL: abd_cmp_i8:1335; RV32I: # %bb.0:1336; RV32I-NEXT: zext.b a1, a11337; RV32I-NEXT: zext.b a0, a01338; RV32I-NEXT: sub a0, a0, a11339; RV32I-NEXT: srai a1, a0, 311340; RV32I-NEXT: xor a0, a0, a11341; RV32I-NEXT: sub a0, a0, a11342; RV32I-NEXT: ret1343;1344; RV64I-LABEL: abd_cmp_i8:1345; RV64I: # %bb.0:1346; RV64I-NEXT: zext.b a1, a11347; RV64I-NEXT: zext.b a0, a01348; RV64I-NEXT: sub a0, a0, a11349; RV64I-NEXT: srai a1, a0, 631350; RV64I-NEXT: xor a0, a0, a11351; RV64I-NEXT: sub a0, a0, a11352; RV64I-NEXT: ret1353;1354; ZBB-LABEL: abd_cmp_i8:1355; ZBB: # %bb.0:1356; ZBB-NEXT: zext.b a1, a11357; ZBB-NEXT: zext.b a0, a01358; ZBB-NEXT: minu a2, a0, a11359; ZBB-NEXT: maxu a0, a0, a11360; ZBB-NEXT: sub a0, a0, a21361; ZBB-NEXT: ret1362 %cmp = icmp ugt i8 %a, %b1363 %ab = sub i8 %a, %b1364 %ba = sub i8 %b, %a1365 %sel = select i1 %cmp, i8 %ab, i8 %ba1366 ret i8 %sel1367}1368 1369define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {1370; RV32I-LABEL: abd_cmp_i16:1371; RV32I: # %bb.0:1372; RV32I-NEXT: lui a2, 161373; RV32I-NEXT: addi a2, a2, -11374; RV32I-NEXT: and a1, a1, a21375; RV32I-NEXT: and a0, a0, a21376; RV32I-NEXT: sub a0, a0, a11377; RV32I-NEXT: srai a1, a0, 311378; RV32I-NEXT: xor a0, a0, a11379; RV32I-NEXT: sub a0, a0, a11380; RV32I-NEXT: ret1381;1382; RV64I-LABEL: abd_cmp_i16:1383; RV64I: # %bb.0:1384; RV64I-NEXT: lui a2, 161385; RV64I-NEXT: addi a2, a2, -11386; RV64I-NEXT: and a1, a1, a21387; RV64I-NEXT: and a0, a0, a21388; RV64I-NEXT: sub a0, a0, a11389; RV64I-NEXT: srai a1, a0, 631390; RV64I-NEXT: xor a0, a0, a11391; RV64I-NEXT: sub a0, a0, a11392; RV64I-NEXT: ret1393;1394; ZBB-LABEL: abd_cmp_i16:1395; ZBB: # %bb.0:1396; ZBB-NEXT: zext.h a1, a11397; ZBB-NEXT: zext.h a0, a01398; ZBB-NEXT: minu a2, a0, a11399; ZBB-NEXT: maxu a0, a0, a11400; ZBB-NEXT: sub a0, a0, a21401; ZBB-NEXT: ret1402 %cmp = icmp uge i16 %a, %b1403 %ab = sub i16 %a, %b1404 %ba = sub i16 %b, %a1405 %sel = select i1 %cmp, i16 %ab, i16 %ba1406 ret i16 %sel1407}1408 1409define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {1410; RV32I-LABEL: abd_cmp_i32:1411; RV32I: # %bb.0:1412; RV32I-NEXT: bltu a1, a0, .LBB20_21413; RV32I-NEXT: # %bb.1:1414; RV32I-NEXT: sub a0, a1, a01415; RV32I-NEXT: ret1416; RV32I-NEXT: .LBB20_2:1417; RV32I-NEXT: sub a0, a0, a11418; RV32I-NEXT: ret1419;1420; RV64I-LABEL: abd_cmp_i32:1421; RV64I: # %bb.0:1422; RV64I-NEXT: slli a1, a1, 321423; RV64I-NEXT: slli a0, a0, 321424; RV64I-NEXT: srli a1, a1, 321425; RV64I-NEXT: srli a0, a0, 321426; RV64I-NEXT: sub a0, a0, a11427; RV64I-NEXT: srai a1, a0, 631428; RV64I-NEXT: xor a0, a0, a11429; RV64I-NEXT: sub a0, a0, a11430; RV64I-NEXT: ret1431;1432; RV32ZBB-LABEL: abd_cmp_i32:1433; RV32ZBB: # %bb.0:1434; RV32ZBB-NEXT: minu a2, a0, a11435; RV32ZBB-NEXT: maxu a0, a0, a11436; RV32ZBB-NEXT: sub a0, a0, a21437; RV32ZBB-NEXT: ret1438;1439; RV64ZBB-LABEL: abd_cmp_i32:1440; RV64ZBB: # %bb.0:1441; RV64ZBB-NEXT: slli a1, a1, 321442; RV64ZBB-NEXT: slli a0, a0, 321443; RV64ZBB-NEXT: srli a1, a1, 321444; RV64ZBB-NEXT: srli a0, a0, 321445; RV64ZBB-NEXT: minu a2, a0, a11446; RV64ZBB-NEXT: maxu a0, a0, a11447; RV64ZBB-NEXT: sub a0, a0, a21448; RV64ZBB-NEXT: ret1449 %cmp = icmp ult i32 %a, %b1450 %ab = sub i32 %a, %b1451 %ba = sub i32 %b, %a1452 %sel = select i1 %cmp, i32 %ba, i32 %ab1453 ret i32 %sel1454}1455 1456define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {1457; RV32I-LABEL: abd_cmp_i64:1458; RV32I: # %bb.0:1459; RV32I-NEXT: sltu a4, a0, a21460; RV32I-NEXT: sub a3, a1, a31461; RV32I-NEXT: sub a3, a3, a41462; RV32I-NEXT: sub a2, a0, a21463; RV32I-NEXT: beq a3, a1, .LBB21_21464; RV32I-NEXT: # %bb.1:1465; RV32I-NEXT: sltu a0, a1, a31466; RV32I-NEXT: j .LBB21_31467; RV32I-NEXT: .LBB21_2:1468; RV32I-NEXT: sltu a0, a0, a21469; RV32I-NEXT: .LBB21_3:1470; RV32I-NEXT: neg a1, a01471; RV32I-NEXT: xor a2, a2, a11472; RV32I-NEXT: xor a3, a3, a11473; RV32I-NEXT: sltu a1, a2, a11474; RV32I-NEXT: add a3, a3, a01475; RV32I-NEXT: sub a1, a3, a11476; RV32I-NEXT: add a0, a2, a01477; RV32I-NEXT: ret1478;1479; RV64I-LABEL: abd_cmp_i64:1480; RV64I: # %bb.0:1481; RV64I-NEXT: bltu a1, a0, .LBB21_21482; RV64I-NEXT: # %bb.1:1483; RV64I-NEXT: sub a0, a1, a01484; RV64I-NEXT: ret1485; RV64I-NEXT: .LBB21_2:1486; RV64I-NEXT: sub a0, a0, a11487; RV64I-NEXT: ret1488;1489; RV32ZBB-LABEL: abd_cmp_i64:1490; RV32ZBB: # %bb.0:1491; RV32ZBB-NEXT: sltu a4, a0, a21492; RV32ZBB-NEXT: sub a3, a1, a31493; RV32ZBB-NEXT: sub a3, a3, a41494; RV32ZBB-NEXT: sub a2, a0, a21495; RV32ZBB-NEXT: beq a3, a1, .LBB21_21496; RV32ZBB-NEXT: # %bb.1:1497; RV32ZBB-NEXT: sltu a0, a1, a31498; RV32ZBB-NEXT: j .LBB21_31499; RV32ZBB-NEXT: .LBB21_2:1500; RV32ZBB-NEXT: sltu a0, a0, a21501; RV32ZBB-NEXT: .LBB21_3:1502; RV32ZBB-NEXT: neg a1, a01503; RV32ZBB-NEXT: xor a2, a2, a11504; RV32ZBB-NEXT: xor a3, a3, a11505; RV32ZBB-NEXT: sltu a1, a2, a11506; RV32ZBB-NEXT: add a3, a3, a01507; RV32ZBB-NEXT: sub a1, a3, a11508; RV32ZBB-NEXT: add a0, a2, a01509; RV32ZBB-NEXT: ret1510;1511; RV64ZBB-LABEL: abd_cmp_i64:1512; RV64ZBB: # %bb.0:1513; RV64ZBB-NEXT: minu a2, a0, a11514; RV64ZBB-NEXT: maxu a0, a0, a11515; RV64ZBB-NEXT: sub a0, a0, a21516; RV64ZBB-NEXT: ret1517 %cmp = icmp uge i64 %a, %b1518 %ab = sub i64 %a, %b1519 %ba = sub i64 %b, %a1520 %sel = select i1 %cmp, i64 %ab, i64 %ba1521 ret i64 %sel1522}1523 1524define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {1525; RV32I-LABEL: abd_cmp_i128:1526; RV32I: # %bb.0:1527; RV32I-NEXT: lw a3, 0(a2)1528; RV32I-NEXT: lw a5, 4(a2)1529; RV32I-NEXT: lw a6, 8(a2)1530; RV32I-NEXT: lw a7, 12(a2)1531; RV32I-NEXT: lw a2, 8(a1)1532; RV32I-NEXT: lw a4, 12(a1)1533; RV32I-NEXT: lw t0, 0(a1)1534; RV32I-NEXT: lw a1, 4(a1)1535; RV32I-NEXT: sltu t1, a2, a61536; RV32I-NEXT: sub a7, a4, a71537; RV32I-NEXT: sltu t2, t0, a31538; RV32I-NEXT: sub a7, a7, t11539; RV32I-NEXT: mv t1, t21540; RV32I-NEXT: beq a1, a5, .LBB22_21541; RV32I-NEXT: # %bb.1:1542; RV32I-NEXT: sltu t1, a1, a51543; RV32I-NEXT: .LBB22_2:1544; RV32I-NEXT: sub t3, a2, a61545; RV32I-NEXT: sltu a6, t3, t11546; RV32I-NEXT: sub a6, a7, a61547; RV32I-NEXT: sub a7, t3, t11548; RV32I-NEXT: beq a6, a4, .LBB22_41549; RV32I-NEXT: # %bb.3:1550; RV32I-NEXT: sltu t1, a4, a61551; RV32I-NEXT: j .LBB22_51552; RV32I-NEXT: .LBB22_4:1553; RV32I-NEXT: sltu t1, a2, a71554; RV32I-NEXT: .LBB22_5:1555; RV32I-NEXT: sub a5, a1, a51556; RV32I-NEXT: sub a5, a5, t21557; RV32I-NEXT: sub a3, t0, a31558; RV32I-NEXT: beq a5, a1, .LBB22_71559; RV32I-NEXT: # %bb.6:1560; RV32I-NEXT: sltu a1, a1, a51561; RV32I-NEXT: j .LBB22_81562; RV32I-NEXT: .LBB22_7:1563; RV32I-NEXT: sltu a1, t0, a31564; RV32I-NEXT: .LBB22_8:1565; RV32I-NEXT: xor a4, a6, a41566; RV32I-NEXT: xor a2, a7, a21567; RV32I-NEXT: or a2, a2, a41568; RV32I-NEXT: beqz a2, .LBB22_101569; RV32I-NEXT: # %bb.9:1570; RV32I-NEXT: mv a1, t11571; RV32I-NEXT: .LBB22_10:1572; RV32I-NEXT: neg t0, a11573; RV32I-NEXT: xor a2, a7, t01574; RV32I-NEXT: xor a6, a6, t01575; RV32I-NEXT: xor a4, a3, t01576; RV32I-NEXT: sltu a3, a2, t01577; RV32I-NEXT: add a7, a6, a11578; RV32I-NEXT: sltu a6, a4, t01579; RV32I-NEXT: sub a3, a7, a31580; RV32I-NEXT: xor t1, a5, t01581; RV32I-NEXT: mv a7, a61582; RV32I-NEXT: beqz a5, .LBB22_121583; RV32I-NEXT: # %bb.11:1584; RV32I-NEXT: sltu a7, t1, t01585; RV32I-NEXT: .LBB22_12:1586; RV32I-NEXT: add a2, a2, a11587; RV32I-NEXT: add t1, t1, a11588; RV32I-NEXT: add a1, a4, a11589; RV32I-NEXT: sltu a4, a2, a71590; RV32I-NEXT: sub a2, a2, a71591; RV32I-NEXT: sub a5, t1, a61592; RV32I-NEXT: sub a3, a3, a41593; RV32I-NEXT: sw a1, 0(a0)1594; RV32I-NEXT: sw a5, 4(a0)1595; RV32I-NEXT: sw a2, 8(a0)1596; RV32I-NEXT: sw a3, 12(a0)1597; RV32I-NEXT: ret1598;1599; RV64I-LABEL: abd_cmp_i128:1600; RV64I: # %bb.0:1601; RV64I-NEXT: sltu a4, a0, a21602; RV64I-NEXT: sub a3, a1, a31603; RV64I-NEXT: sub a3, a3, a41604; RV64I-NEXT: sub a2, a0, a21605; RV64I-NEXT: beq a3, a1, .LBB22_21606; RV64I-NEXT: # %bb.1:1607; RV64I-NEXT: sltu a0, a1, a31608; RV64I-NEXT: j .LBB22_31609; RV64I-NEXT: .LBB22_2:1610; RV64I-NEXT: sltu a0, a0, a21611; RV64I-NEXT: .LBB22_3:1612; RV64I-NEXT: neg a1, a01613; RV64I-NEXT: xor a2, a2, a11614; RV64I-NEXT: xor a3, a3, a11615; RV64I-NEXT: sltu a1, a2, a11616; RV64I-NEXT: add a3, a3, a01617; RV64I-NEXT: sub a1, a3, a11618; RV64I-NEXT: add a0, a2, a01619; RV64I-NEXT: ret1620;1621; RV32ZBB-LABEL: abd_cmp_i128:1622; RV32ZBB: # %bb.0:1623; RV32ZBB-NEXT: lw a3, 0(a2)1624; RV32ZBB-NEXT: lw a5, 4(a2)1625; RV32ZBB-NEXT: lw a6, 8(a2)1626; RV32ZBB-NEXT: lw a7, 12(a2)1627; RV32ZBB-NEXT: lw a2, 8(a1)1628; RV32ZBB-NEXT: lw a4, 12(a1)1629; RV32ZBB-NEXT: lw t0, 0(a1)1630; RV32ZBB-NEXT: lw a1, 4(a1)1631; RV32ZBB-NEXT: sltu t1, a2, a61632; RV32ZBB-NEXT: sub a7, a4, a71633; RV32ZBB-NEXT: sltu t2, t0, a31634; RV32ZBB-NEXT: sub a7, a7, t11635; RV32ZBB-NEXT: mv t1, t21636; RV32ZBB-NEXT: beq a1, a5, .LBB22_21637; RV32ZBB-NEXT: # %bb.1:1638; RV32ZBB-NEXT: sltu t1, a1, a51639; RV32ZBB-NEXT: .LBB22_2:1640; RV32ZBB-NEXT: sub t3, a2, a61641; RV32ZBB-NEXT: sltu a6, t3, t11642; RV32ZBB-NEXT: sub a6, a7, a61643; RV32ZBB-NEXT: sub a7, t3, t11644; RV32ZBB-NEXT: beq a6, a4, .LBB22_41645; RV32ZBB-NEXT: # %bb.3:1646; RV32ZBB-NEXT: sltu t1, a4, a61647; RV32ZBB-NEXT: j .LBB22_51648; RV32ZBB-NEXT: .LBB22_4:1649; RV32ZBB-NEXT: sltu t1, a2, a71650; RV32ZBB-NEXT: .LBB22_5:1651; RV32ZBB-NEXT: sub a5, a1, a51652; RV32ZBB-NEXT: sub a5, a5, t21653; RV32ZBB-NEXT: sub a3, t0, a31654; RV32ZBB-NEXT: beq a5, a1, .LBB22_71655; RV32ZBB-NEXT: # %bb.6:1656; RV32ZBB-NEXT: sltu a1, a1, a51657; RV32ZBB-NEXT: j .LBB22_81658; RV32ZBB-NEXT: .LBB22_7:1659; RV32ZBB-NEXT: sltu a1, t0, a31660; RV32ZBB-NEXT: .LBB22_8:1661; RV32ZBB-NEXT: xor a4, a6, a41662; RV32ZBB-NEXT: xor a2, a7, a21663; RV32ZBB-NEXT: or a2, a2, a41664; RV32ZBB-NEXT: beqz a2, .LBB22_101665; RV32ZBB-NEXT: # %bb.9:1666; RV32ZBB-NEXT: mv a1, t11667; RV32ZBB-NEXT: .LBB22_10:1668; RV32ZBB-NEXT: neg t0, a11669; RV32ZBB-NEXT: xor a2, a7, t01670; RV32ZBB-NEXT: xor a6, a6, t01671; RV32ZBB-NEXT: xor a4, a3, t01672; RV32ZBB-NEXT: sltu a3, a2, t01673; RV32ZBB-NEXT: add a7, a6, a11674; RV32ZBB-NEXT: sltu a6, a4, t01675; RV32ZBB-NEXT: sub a3, a7, a31676; RV32ZBB-NEXT: xor t1, a5, t01677; RV32ZBB-NEXT: mv a7, a61678; RV32ZBB-NEXT: beqz a5, .LBB22_121679; RV32ZBB-NEXT: # %bb.11:1680; RV32ZBB-NEXT: sltu a7, t1, t01681; RV32ZBB-NEXT: .LBB22_12:1682; RV32ZBB-NEXT: add a2, a2, a11683; RV32ZBB-NEXT: add t1, t1, a11684; RV32ZBB-NEXT: add a1, a4, a11685; RV32ZBB-NEXT: sltu a4, a2, a71686; RV32ZBB-NEXT: sub a2, a2, a71687; RV32ZBB-NEXT: sub a5, t1, a61688; RV32ZBB-NEXT: sub a3, a3, a41689; RV32ZBB-NEXT: sw a1, 0(a0)1690; RV32ZBB-NEXT: sw a5, 4(a0)1691; RV32ZBB-NEXT: sw a2, 8(a0)1692; RV32ZBB-NEXT: sw a3, 12(a0)1693; RV32ZBB-NEXT: ret1694;1695; RV64ZBB-LABEL: abd_cmp_i128:1696; RV64ZBB: # %bb.0:1697; RV64ZBB-NEXT: sltu a4, a0, a21698; RV64ZBB-NEXT: sub a3, a1, a31699; RV64ZBB-NEXT: sub a3, a3, a41700; RV64ZBB-NEXT: sub a2, a0, a21701; RV64ZBB-NEXT: beq a3, a1, .LBB22_21702; RV64ZBB-NEXT: # %bb.1:1703; RV64ZBB-NEXT: sltu a0, a1, a31704; RV64ZBB-NEXT: j .LBB22_31705; RV64ZBB-NEXT: .LBB22_2:1706; RV64ZBB-NEXT: sltu a0, a0, a21707; RV64ZBB-NEXT: .LBB22_3:1708; RV64ZBB-NEXT: neg a1, a01709; RV64ZBB-NEXT: xor a2, a2, a11710; RV64ZBB-NEXT: xor a3, a3, a11711; RV64ZBB-NEXT: sltu a1, a2, a11712; RV64ZBB-NEXT: add a3, a3, a01713; RV64ZBB-NEXT: sub a1, a3, a11714; RV64ZBB-NEXT: add a0, a2, a01715; RV64ZBB-NEXT: ret1716 %cmp = icmp uge i128 %a, %b1717 %ab = sub i128 %a, %b1718 %ba = sub i128 %b, %a1719 %sel = select i1 %cmp, i128 %ab, i128 %ba1720 ret i128 %sel1721}1722 1723;1724; sub(select(icmp(a,b),a,b),select(icmp(a,b),b,a)) -> abdu(a,b)1725;1726 1727define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {1728; RV32I-LABEL: abd_select_i8:1729; RV32I: # %bb.0:1730; RV32I-NEXT: zext.b a1, a11731; RV32I-NEXT: zext.b a0, a01732; RV32I-NEXT: sub a0, a0, a11733; RV32I-NEXT: srai a1, a0, 311734; RV32I-NEXT: xor a0, a0, a11735; RV32I-NEXT: sub a0, a0, a11736; RV32I-NEXT: ret1737;1738; RV64I-LABEL: abd_select_i8:1739; RV64I: # %bb.0:1740; RV64I-NEXT: zext.b a1, a11741; RV64I-NEXT: zext.b a0, a01742; RV64I-NEXT: sub a0, a0, a11743; RV64I-NEXT: srai a1, a0, 631744; RV64I-NEXT: xor a0, a0, a11745; RV64I-NEXT: sub a0, a0, a11746; RV64I-NEXT: ret1747;1748; ZBB-LABEL: abd_select_i8:1749; ZBB: # %bb.0:1750; ZBB-NEXT: zext.b a1, a11751; ZBB-NEXT: zext.b a0, a01752; ZBB-NEXT: minu a2, a0, a11753; ZBB-NEXT: maxu a0, a0, a11754; ZBB-NEXT: sub a0, a0, a21755; ZBB-NEXT: ret1756 %cmp = icmp ult i8 %a, %b1757 %ab = select i1 %cmp, i8 %a, i8 %b1758 %ba = select i1 %cmp, i8 %b, i8 %a1759 %sub = sub i8 %ba, %ab1760 ret i8 %sub1761}1762 1763define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {1764; RV32I-LABEL: abd_select_i16:1765; RV32I: # %bb.0:1766; RV32I-NEXT: lui a2, 161767; RV32I-NEXT: addi a2, a2, -11768; RV32I-NEXT: and a1, a1, a21769; RV32I-NEXT: and a0, a0, a21770; RV32I-NEXT: sub a0, a0, a11771; RV32I-NEXT: srai a1, a0, 311772; RV32I-NEXT: xor a0, a0, a11773; RV32I-NEXT: sub a0, a0, a11774; RV32I-NEXT: ret1775;1776; RV64I-LABEL: abd_select_i16:1777; RV64I: # %bb.0:1778; RV64I-NEXT: lui a2, 161779; RV64I-NEXT: addi a2, a2, -11780; RV64I-NEXT: and a1, a1, a21781; RV64I-NEXT: and a0, a0, a21782; RV64I-NEXT: sub a0, a0, a11783; RV64I-NEXT: srai a1, a0, 631784; RV64I-NEXT: xor a0, a0, a11785; RV64I-NEXT: sub a0, a0, a11786; RV64I-NEXT: ret1787;1788; ZBB-LABEL: abd_select_i16:1789; ZBB: # %bb.0:1790; ZBB-NEXT: zext.h a1, a11791; ZBB-NEXT: zext.h a0, a01792; ZBB-NEXT: minu a2, a0, a11793; ZBB-NEXT: maxu a0, a0, a11794; ZBB-NEXT: sub a0, a0, a21795; ZBB-NEXT: ret1796 %cmp = icmp ule i16 %a, %b1797 %ab = select i1 %cmp, i16 %a, i16 %b1798 %ba = select i1 %cmp, i16 %b, i16 %a1799 %sub = sub i16 %ba, %ab1800 ret i16 %sub1801}1802 1803define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {1804; RV32I-LABEL: abd_select_i32:1805; RV32I: # %bb.0:1806; RV32I-NEXT: bltu a1, a0, .LBB25_21807; RV32I-NEXT: # %bb.1:1808; RV32I-NEXT: sub a0, a1, a01809; RV32I-NEXT: ret1810; RV32I-NEXT: .LBB25_2:1811; RV32I-NEXT: sub a0, a0, a11812; RV32I-NEXT: ret1813;1814; RV64I-LABEL: abd_select_i32:1815; RV64I: # %bb.0:1816; RV64I-NEXT: slli a1, a1, 321817; RV64I-NEXT: slli a0, a0, 321818; RV64I-NEXT: srli a1, a1, 321819; RV64I-NEXT: srli a0, a0, 321820; RV64I-NEXT: sub a0, a0, a11821; RV64I-NEXT: srai a1, a0, 631822; RV64I-NEXT: xor a0, a0, a11823; RV64I-NEXT: sub a0, a0, a11824; RV64I-NEXT: ret1825;1826; RV32ZBB-LABEL: abd_select_i32:1827; RV32ZBB: # %bb.0:1828; RV32ZBB-NEXT: minu a2, a0, a11829; RV32ZBB-NEXT: maxu a0, a0, a11830; RV32ZBB-NEXT: sub a0, a0, a21831; RV32ZBB-NEXT: ret1832;1833; RV64ZBB-LABEL: abd_select_i32:1834; RV64ZBB: # %bb.0:1835; RV64ZBB-NEXT: slli a1, a1, 321836; RV64ZBB-NEXT: slli a0, a0, 321837; RV64ZBB-NEXT: srli a1, a1, 321838; RV64ZBB-NEXT: srli a0, a0, 321839; RV64ZBB-NEXT: minu a2, a0, a11840; RV64ZBB-NEXT: maxu a0, a0, a11841; RV64ZBB-NEXT: sub a0, a0, a21842; RV64ZBB-NEXT: ret1843 %cmp = icmp ugt i32 %a, %b1844 %ab = select i1 %cmp, i32 %a, i32 %b1845 %ba = select i1 %cmp, i32 %b, i32 %a1846 %sub = sub i32 %ab, %ba1847 ret i32 %sub1848}1849 1850define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {1851; RV32I-LABEL: abd_select_i64:1852; RV32I: # %bb.0:1853; RV32I-NEXT: sltu a4, a0, a21854; RV32I-NEXT: sub a3, a1, a31855; RV32I-NEXT: sub a3, a3, a41856; RV32I-NEXT: sub a2, a0, a21857; RV32I-NEXT: beq a3, a1, .LBB26_21858; RV32I-NEXT: # %bb.1:1859; RV32I-NEXT: sltu a0, a1, a31860; RV32I-NEXT: j .LBB26_31861; RV32I-NEXT: .LBB26_2:1862; RV32I-NEXT: sltu a0, a0, a21863; RV32I-NEXT: .LBB26_3:1864; RV32I-NEXT: neg a1, a01865; RV32I-NEXT: xor a2, a2, a11866; RV32I-NEXT: xor a3, a3, a11867; RV32I-NEXT: sltu a1, a2, a11868; RV32I-NEXT: add a3, a3, a01869; RV32I-NEXT: sub a1, a3, a11870; RV32I-NEXT: add a0, a2, a01871; RV32I-NEXT: ret1872;1873; RV64I-LABEL: abd_select_i64:1874; RV64I: # %bb.0:1875; RV64I-NEXT: bltu a1, a0, .LBB26_21876; RV64I-NEXT: # %bb.1:1877; RV64I-NEXT: sub a0, a1, a01878; RV64I-NEXT: ret1879; RV64I-NEXT: .LBB26_2:1880; RV64I-NEXT: sub a0, a0, a11881; RV64I-NEXT: ret1882;1883; RV32ZBB-LABEL: abd_select_i64:1884; RV32ZBB: # %bb.0:1885; RV32ZBB-NEXT: sltu a4, a0, a21886; RV32ZBB-NEXT: sub a3, a1, a31887; RV32ZBB-NEXT: sub a3, a3, a41888; RV32ZBB-NEXT: sub a2, a0, a21889; RV32ZBB-NEXT: beq a3, a1, .LBB26_21890; RV32ZBB-NEXT: # %bb.1:1891; RV32ZBB-NEXT: sltu a0, a1, a31892; RV32ZBB-NEXT: j .LBB26_31893; RV32ZBB-NEXT: .LBB26_2:1894; RV32ZBB-NEXT: sltu a0, a0, a21895; RV32ZBB-NEXT: .LBB26_3:1896; RV32ZBB-NEXT: neg a1, a01897; RV32ZBB-NEXT: xor a2, a2, a11898; RV32ZBB-NEXT: xor a3, a3, a11899; RV32ZBB-NEXT: sltu a1, a2, a11900; RV32ZBB-NEXT: add a3, a3, a01901; RV32ZBB-NEXT: sub a1, a3, a11902; RV32ZBB-NEXT: add a0, a2, a01903; RV32ZBB-NEXT: ret1904;1905; RV64ZBB-LABEL: abd_select_i64:1906; RV64ZBB: # %bb.0:1907; RV64ZBB-NEXT: minu a2, a0, a11908; RV64ZBB-NEXT: maxu a0, a0, a11909; RV64ZBB-NEXT: sub a0, a0, a21910; RV64ZBB-NEXT: ret1911 %cmp = icmp uge i64 %a, %b1912 %ab = select i1 %cmp, i64 %a, i64 %b1913 %ba = select i1 %cmp, i64 %b, i64 %a1914 %sub = sub i64 %ab, %ba1915 ret i64 %sub1916}1917 1918define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {1919; RV32I-LABEL: abd_select_i128:1920; RV32I: # %bb.0:1921; RV32I-NEXT: lw a3, 0(a2)1922; RV32I-NEXT: lw a5, 4(a2)1923; RV32I-NEXT: lw a6, 8(a2)1924; RV32I-NEXT: lw a7, 12(a2)1925; RV32I-NEXT: lw a2, 8(a1)1926; RV32I-NEXT: lw a4, 12(a1)1927; RV32I-NEXT: lw t0, 0(a1)1928; RV32I-NEXT: lw a1, 4(a1)1929; RV32I-NEXT: sltu t1, a2, a61930; RV32I-NEXT: sub a7, a4, a71931; RV32I-NEXT: sltu t2, t0, a31932; RV32I-NEXT: sub a7, a7, t11933; RV32I-NEXT: mv t1, t21934; RV32I-NEXT: beq a1, a5, .LBB27_21935; RV32I-NEXT: # %bb.1:1936; RV32I-NEXT: sltu t1, a1, a51937; RV32I-NEXT: .LBB27_2:1938; RV32I-NEXT: sub t3, a2, a61939; RV32I-NEXT: sltu a6, t3, t11940; RV32I-NEXT: sub a6, a7, a61941; RV32I-NEXT: sub a7, t3, t11942; RV32I-NEXT: beq a6, a4, .LBB27_41943; RV32I-NEXT: # %bb.3:1944; RV32I-NEXT: sltu t1, a4, a61945; RV32I-NEXT: j .LBB27_51946; RV32I-NEXT: .LBB27_4:1947; RV32I-NEXT: sltu t1, a2, a71948; RV32I-NEXT: .LBB27_5:1949; RV32I-NEXT: sub a5, a1, a51950; RV32I-NEXT: sub a5, a5, t21951; RV32I-NEXT: sub a3, t0, a31952; RV32I-NEXT: beq a5, a1, .LBB27_71953; RV32I-NEXT: # %bb.6:1954; RV32I-NEXT: sltu a1, a1, a51955; RV32I-NEXT: j .LBB27_81956; RV32I-NEXT: .LBB27_7:1957; RV32I-NEXT: sltu a1, t0, a31958; RV32I-NEXT: .LBB27_8:1959; RV32I-NEXT: xor a4, a6, a41960; RV32I-NEXT: xor a2, a7, a21961; RV32I-NEXT: or a2, a2, a41962; RV32I-NEXT: beqz a2, .LBB27_101963; RV32I-NEXT: # %bb.9:1964; RV32I-NEXT: mv a1, t11965; RV32I-NEXT: .LBB27_10:1966; RV32I-NEXT: neg t0, a11967; RV32I-NEXT: xor a2, a7, t01968; RV32I-NEXT: xor a6, a6, t01969; RV32I-NEXT: xor a4, a3, t01970; RV32I-NEXT: sltu a3, a2, t01971; RV32I-NEXT: add a7, a6, a11972; RV32I-NEXT: sltu a6, a4, t01973; RV32I-NEXT: sub a3, a7, a31974; RV32I-NEXT: xor t1, a5, t01975; RV32I-NEXT: mv a7, a61976; RV32I-NEXT: beqz a5, .LBB27_121977; RV32I-NEXT: # %bb.11:1978; RV32I-NEXT: sltu a7, t1, t01979; RV32I-NEXT: .LBB27_12:1980; RV32I-NEXT: add a2, a2, a11981; RV32I-NEXT: add t1, t1, a11982; RV32I-NEXT: add a1, a4, a11983; RV32I-NEXT: sltu a4, a2, a71984; RV32I-NEXT: sub a2, a2, a71985; RV32I-NEXT: sub a5, t1, a61986; RV32I-NEXT: sub a3, a3, a41987; RV32I-NEXT: sw a1, 0(a0)1988; RV32I-NEXT: sw a5, 4(a0)1989; RV32I-NEXT: sw a2, 8(a0)1990; RV32I-NEXT: sw a3, 12(a0)1991; RV32I-NEXT: ret1992;1993; RV64I-LABEL: abd_select_i128:1994; RV64I: # %bb.0:1995; RV64I-NEXT: sltu a4, a0, a21996; RV64I-NEXT: sub a3, a1, a31997; RV64I-NEXT: sub a3, a3, a41998; RV64I-NEXT: sub a2, a0, a21999; RV64I-NEXT: beq a3, a1, .LBB27_22000; RV64I-NEXT: # %bb.1:2001; RV64I-NEXT: sltu a0, a1, a32002; RV64I-NEXT: j .LBB27_32003; RV64I-NEXT: .LBB27_2:2004; RV64I-NEXT: sltu a0, a0, a22005; RV64I-NEXT: .LBB27_3:2006; RV64I-NEXT: neg a1, a02007; RV64I-NEXT: xor a2, a2, a12008; RV64I-NEXT: xor a3, a3, a12009; RV64I-NEXT: sltu a1, a2, a12010; RV64I-NEXT: add a3, a3, a02011; RV64I-NEXT: sub a1, a3, a12012; RV64I-NEXT: add a0, a2, a02013; RV64I-NEXT: ret2014;2015; RV32ZBB-LABEL: abd_select_i128:2016; RV32ZBB: # %bb.0:2017; RV32ZBB-NEXT: lw a3, 0(a2)2018; RV32ZBB-NEXT: lw a5, 4(a2)2019; RV32ZBB-NEXT: lw a6, 8(a2)2020; RV32ZBB-NEXT: lw a7, 12(a2)2021; RV32ZBB-NEXT: lw a2, 8(a1)2022; RV32ZBB-NEXT: lw a4, 12(a1)2023; RV32ZBB-NEXT: lw t0, 0(a1)2024; RV32ZBB-NEXT: lw a1, 4(a1)2025; RV32ZBB-NEXT: sltu t1, a2, a62026; RV32ZBB-NEXT: sub a7, a4, a72027; RV32ZBB-NEXT: sltu t2, t0, a32028; RV32ZBB-NEXT: sub a7, a7, t12029; RV32ZBB-NEXT: mv t1, t22030; RV32ZBB-NEXT: beq a1, a5, .LBB27_22031; RV32ZBB-NEXT: # %bb.1:2032; RV32ZBB-NEXT: sltu t1, a1, a52033; RV32ZBB-NEXT: .LBB27_2:2034; RV32ZBB-NEXT: sub t3, a2, a62035; RV32ZBB-NEXT: sltu a6, t3, t12036; RV32ZBB-NEXT: sub a6, a7, a62037; RV32ZBB-NEXT: sub a7, t3, t12038; RV32ZBB-NEXT: beq a6, a4, .LBB27_42039; RV32ZBB-NEXT: # %bb.3:2040; RV32ZBB-NEXT: sltu t1, a4, a62041; RV32ZBB-NEXT: j .LBB27_52042; RV32ZBB-NEXT: .LBB27_4:2043; RV32ZBB-NEXT: sltu t1, a2, a72044; RV32ZBB-NEXT: .LBB27_5:2045; RV32ZBB-NEXT: sub a5, a1, a52046; RV32ZBB-NEXT: sub a5, a5, t22047; RV32ZBB-NEXT: sub a3, t0, a32048; RV32ZBB-NEXT: beq a5, a1, .LBB27_72049; RV32ZBB-NEXT: # %bb.6:2050; RV32ZBB-NEXT: sltu a1, a1, a52051; RV32ZBB-NEXT: j .LBB27_82052; RV32ZBB-NEXT: .LBB27_7:2053; RV32ZBB-NEXT: sltu a1, t0, a32054; RV32ZBB-NEXT: .LBB27_8:2055; RV32ZBB-NEXT: xor a4, a6, a42056; RV32ZBB-NEXT: xor a2, a7, a22057; RV32ZBB-NEXT: or a2, a2, a42058; RV32ZBB-NEXT: beqz a2, .LBB27_102059; RV32ZBB-NEXT: # %bb.9:2060; RV32ZBB-NEXT: mv a1, t12061; RV32ZBB-NEXT: .LBB27_10:2062; RV32ZBB-NEXT: neg t0, a12063; RV32ZBB-NEXT: xor a2, a7, t02064; RV32ZBB-NEXT: xor a6, a6, t02065; RV32ZBB-NEXT: xor a4, a3, t02066; RV32ZBB-NEXT: sltu a3, a2, t02067; RV32ZBB-NEXT: add a7, a6, a12068; RV32ZBB-NEXT: sltu a6, a4, t02069; RV32ZBB-NEXT: sub a3, a7, a32070; RV32ZBB-NEXT: xor t1, a5, t02071; RV32ZBB-NEXT: mv a7, a62072; RV32ZBB-NEXT: beqz a5, .LBB27_122073; RV32ZBB-NEXT: # %bb.11:2074; RV32ZBB-NEXT: sltu a7, t1, t02075; RV32ZBB-NEXT: .LBB27_12:2076; RV32ZBB-NEXT: add a2, a2, a12077; RV32ZBB-NEXT: add t1, t1, a12078; RV32ZBB-NEXT: add a1, a4, a12079; RV32ZBB-NEXT: sltu a4, a2, a72080; RV32ZBB-NEXT: sub a2, a2, a72081; RV32ZBB-NEXT: sub a5, t1, a62082; RV32ZBB-NEXT: sub a3, a3, a42083; RV32ZBB-NEXT: sw a1, 0(a0)2084; RV32ZBB-NEXT: sw a5, 4(a0)2085; RV32ZBB-NEXT: sw a2, 8(a0)2086; RV32ZBB-NEXT: sw a3, 12(a0)2087; RV32ZBB-NEXT: ret2088;2089; RV64ZBB-LABEL: abd_select_i128:2090; RV64ZBB: # %bb.0:2091; RV64ZBB-NEXT: sltu a4, a0, a22092; RV64ZBB-NEXT: sub a3, a1, a32093; RV64ZBB-NEXT: sub a3, a3, a42094; RV64ZBB-NEXT: sub a2, a0, a22095; RV64ZBB-NEXT: beq a3, a1, .LBB27_22096; RV64ZBB-NEXT: # %bb.1:2097; RV64ZBB-NEXT: sltu a0, a1, a32098; RV64ZBB-NEXT: j .LBB27_32099; RV64ZBB-NEXT: .LBB27_2:2100; RV64ZBB-NEXT: sltu a0, a0, a22101; RV64ZBB-NEXT: .LBB27_3:2102; RV64ZBB-NEXT: neg a1, a02103; RV64ZBB-NEXT: xor a2, a2, a12104; RV64ZBB-NEXT: xor a3, a3, a12105; RV64ZBB-NEXT: sltu a1, a2, a12106; RV64ZBB-NEXT: add a3, a3, a02107; RV64ZBB-NEXT: sub a1, a3, a12108; RV64ZBB-NEXT: add a0, a2, a02109; RV64ZBB-NEXT: ret2110 %cmp = icmp ult i128 %a, %b2111 %ab = select i1 %cmp, i128 %a, i128 %b2112 %ba = select i1 %cmp, i128 %b, i128 %a2113 %sub = sub i128 %ba, %ab2114 ret i128 %sub2115}2116 2117;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:2118; CHECK: {{.*}}2119; NOZBB: {{.*}}2120