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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs -M no-aliases < %s \3; RUN: | FileCheck -check-prefixes=RV32I %s4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -M no-aliases < %s \5; RUN: | FileCheck -check-prefixes=RV64I %s6; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs -M no-aliases \7; RUN: < %s | FileCheck -check-prefixes=RV32C %s8; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs -M no-aliases \9; RUN: < %s | FileCheck -check-prefixes=RV64C %s10; RUN: llc -mtriple=riscv32 -mattr=+zca -verify-machineinstrs -M no-aliases \11; RUN: < %s | FileCheck -check-prefixes=RV32C %s12; RUN: llc -mtriple=riscv64 -mattr=+zca -verify-machineinstrs -M no-aliases \13; RUN: < %s | FileCheck -check-prefixes=RV64C %s14 15; These test that constant adds are not moved after shifts by DAGCombine,16; if the constant is cheaper to materialise before it has been shifted.17 18define signext i32 @add_small_const(i32 signext %a) nounwind {19; RV32I-LABEL: add_small_const:20; RV32I: # %bb.0:21; RV32I-NEXT: addi a0, a0, 122; RV32I-NEXT: slli a0, a0, 2423; RV32I-NEXT: srai a0, a0, 2424; RV32I-NEXT: jalr zero, 0(ra)25;26; RV64I-LABEL: add_small_const:27; RV64I: # %bb.0:28; RV64I-NEXT: addi a0, a0, 129; RV64I-NEXT: slli a0, a0, 5630; RV64I-NEXT: srai a0, a0, 5631; RV64I-NEXT: jalr zero, 0(ra)32;33; RV32C-LABEL: add_small_const:34; RV32C: # %bb.0:35; RV32C-NEXT: c.addi a0, 136; RV32C-NEXT: c.slli a0, 2437; RV32C-NEXT: c.srai a0, 2438; RV32C-NEXT: c.jr ra39;40; RV64C-LABEL: add_small_const:41; RV64C: # %bb.0:42; RV64C-NEXT: c.addi a0, 143; RV64C-NEXT: c.slli a0, 5644; RV64C-NEXT: c.srai a0, 5645; RV64C-NEXT: c.jr ra46 %1 = add i32 %a, 147 %2 = shl i32 %1, 2448 %3 = ashr i32 %2, 2449 ret i32 %350}51 52define signext i32 @add_large_const(i32 signext %a) nounwind {53; RV32I-LABEL: add_large_const:54; RV32I: # %bb.0:55; RV32I-NEXT: slli a0, a0, 1656; RV32I-NEXT: lui a1, 6552057; RV32I-NEXT: add a0, a0, a158; RV32I-NEXT: srai a0, a0, 1659; RV32I-NEXT: jalr zero, 0(ra)60;61; RV64I-LABEL: add_large_const:62; RV64I: # %bb.0:63; RV64I-NEXT: slli a0, a0, 4864; RV64I-NEXT: lui a1, 409565; RV64I-NEXT: slli a1, a1, 3666; RV64I-NEXT: add a0, a0, a167; RV64I-NEXT: srai a0, a0, 4868; RV64I-NEXT: jalr zero, 0(ra)69;70; RV32C-LABEL: add_large_const:71; RV32C: # %bb.0:72; RV32C-NEXT: c.slli a0, 1673; RV32C-NEXT: lui a1, 6552074; RV32C-NEXT: c.add a0, a175; RV32C-NEXT: c.srai a0, 1676; RV32C-NEXT: c.jr ra77;78; RV64C-LABEL: add_large_const:79; RV64C: # %bb.0:80; RV64C-NEXT: c.lui a1, 181; RV64C-NEXT: c.addi a1, -182; RV64C-NEXT: c.add a0, a183; RV64C-NEXT: c.slli a0, 4884; RV64C-NEXT: c.srai a0, 4885; RV64C-NEXT: c.jr ra86 %1 = add i32 %a, 409587 %2 = shl i32 %1, 1688 %3 = ashr i32 %2, 1689 ret i32 %390}91 92define signext i32 @add_huge_const(i32 signext %a) nounwind {93; RV32I-LABEL: add_huge_const:94; RV32I: # %bb.0:95; RV32I-NEXT: slli a0, a0, 1696; RV32I-NEXT: lui a1, 52427297; RV32I-NEXT: add a0, a0, a198; RV32I-NEXT: srai a0, a0, 1699; RV32I-NEXT: jalr zero, 0(ra)100;101; RV64I-LABEL: add_huge_const:102; RV64I: # %bb.0:103; RV64I-NEXT: slli a0, a0, 48104; RV64I-NEXT: lui a1, 32767105; RV64I-NEXT: slli a1, a1, 36106; RV64I-NEXT: add a0, a0, a1107; RV64I-NEXT: srai a0, a0, 48108; RV64I-NEXT: jalr zero, 0(ra)109;110; RV32C-LABEL: add_huge_const:111; RV32C: # %bb.0:112; RV32C-NEXT: c.slli a0, 16113; RV32C-NEXT: lui a1, 524272114; RV32C-NEXT: c.add a0, a1115; RV32C-NEXT: c.srai a0, 16116; RV32C-NEXT: c.jr ra117;118; RV64C-LABEL: add_huge_const:119; RV64C: # %bb.0:120; RV64C-NEXT: c.lui a1, 8121; RV64C-NEXT: c.addi a1, -1122; RV64C-NEXT: c.add a0, a1123; RV64C-NEXT: c.slli a0, 48124; RV64C-NEXT: c.srai a0, 48125; RV64C-NEXT: c.jr ra126 %1 = add i32 %a, 32767127 %2 = shl i32 %1, 16128 %3 = ashr i32 %2, 16129 ret i32 %3130}131 132define signext i24 @add_non_machine_type(i24 signext %a) nounwind {133; RV32I-LABEL: add_non_machine_type:134; RV32I: # %bb.0:135; RV32I-NEXT: addi a0, a0, 256136; RV32I-NEXT: slli a0, a0, 20137; RV32I-NEXT: srai a0, a0, 8138; RV32I-NEXT: jalr zero, 0(ra)139;140; RV64I-LABEL: add_non_machine_type:141; RV64I: # %bb.0:142; RV64I-NEXT: addi a0, a0, 256143; RV64I-NEXT: slli a0, a0, 52144; RV64I-NEXT: srai a0, a0, 40145; RV64I-NEXT: jalr zero, 0(ra)146;147; RV32C-LABEL: add_non_machine_type:148; RV32C: # %bb.0:149; RV32C-NEXT: addi a0, a0, 256150; RV32C-NEXT: c.slli a0, 20151; RV32C-NEXT: c.srai a0, 8152; RV32C-NEXT: c.jr ra153;154; RV64C-LABEL: add_non_machine_type:155; RV64C: # %bb.0:156; RV64C-NEXT: addi a0, a0, 256157; RV64C-NEXT: c.slli a0, 52158; RV64C-NEXT: c.srai a0, 40159; RV64C-NEXT: c.jr ra160 %1 = add i24 %a, 256161 %2 = shl i24 %1, 12162 ret i24 %2163}164 165define i128 @add_wide_operand(i128 %a) nounwind {166; RV32I-LABEL: add_wide_operand:167; RV32I: # %bb.0:168; RV32I-NEXT: lw a2, 0(a1)169; RV32I-NEXT: lw a3, 4(a1)170; RV32I-NEXT: lw a4, 8(a1)171; RV32I-NEXT: lw a1, 12(a1)172; RV32I-NEXT: srli a5, a2, 29173; RV32I-NEXT: slli a6, a3, 3174; RV32I-NEXT: srli a3, a3, 29175; RV32I-NEXT: or a5, a6, a5176; RV32I-NEXT: slli a6, a4, 3177; RV32I-NEXT: or a3, a6, a3178; RV32I-NEXT: lui a6, 128179; RV32I-NEXT: srli a4, a4, 29180; RV32I-NEXT: slli a1, a1, 3181; RV32I-NEXT: slli a2, a2, 3182; RV32I-NEXT: or a1, a1, a4183; RV32I-NEXT: add a1, a1, a6184; RV32I-NEXT: sw a2, 0(a0)185; RV32I-NEXT: sw a5, 4(a0)186; RV32I-NEXT: sw a3, 8(a0)187; RV32I-NEXT: sw a1, 12(a0)188; RV32I-NEXT: jalr zero, 0(ra)189;190; RV64I-LABEL: add_wide_operand:191; RV64I: # %bb.0:192; RV64I-NEXT: srli a2, a0, 61193; RV64I-NEXT: slli a1, a1, 3194; RV64I-NEXT: slli a0, a0, 3195; RV64I-NEXT: or a1, a1, a2196; RV64I-NEXT: addi a2, zero, 1197; RV64I-NEXT: slli a2, a2, 51198; RV64I-NEXT: add a1, a1, a2199; RV64I-NEXT: jalr zero, 0(ra)200;201; RV32C-LABEL: add_wide_operand:202; RV32C: # %bb.0:203; RV32C-NEXT: c.lw a2, 0(a1)204; RV32C-NEXT: c.lw a4, 12(a1)205; RV32C-NEXT: c.lw a3, 4(a1)206; RV32C-NEXT: c.lw a1, 8(a1)207; RV32C-NEXT: c.lui a5, 16208; RV32C-NEXT: add a6, a4, a5209; RV32C-NEXT: srli a5, a2, 29210; RV32C-NEXT: slli a4, a3, 3211; RV32C-NEXT: c.or a4, a5212; RV32C-NEXT: srli a5, a1, 29213; RV32C-NEXT: c.srli a3, 29214; RV32C-NEXT: c.slli a1, 3215; RV32C-NEXT: c.slli a2, 3216; RV32C-NEXT: c.slli a6, 3217; RV32C-NEXT: c.or a1, a3218; RV32C-NEXT: or a3, a6, a5219; RV32C-NEXT: c.sw a2, 0(a0)220; RV32C-NEXT: c.sw a4, 4(a0)221; RV32C-NEXT: c.sw a1, 8(a0)222; RV32C-NEXT: c.sw a3, 12(a0)223; RV32C-NEXT: c.jr ra224;225; RV64C-LABEL: add_wide_operand:226; RV64C: # %bb.0:227; RV64C-NEXT: srli a2, a0, 61228; RV64C-NEXT: c.slli a1, 3229; RV64C-NEXT: c.slli a0, 3230; RV64C-NEXT: c.or a1, a2231; RV64C-NEXT: c.li a2, 1232; RV64C-NEXT: c.slli a2, 51233; RV64C-NEXT: c.add a1, a2234; RV64C-NEXT: c.jr ra235 %1 = add i128 %a, 5192296858534827628530496329220096236 %2 = shl i128 %1, 3237 ret i128 %2238}239