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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32I %s4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64I %s6 7; These test how the immediate in an addition is materialized.8 9define i32 @add_positive_low_bound_reject(i32 %a) nounwind {10; RV32I-LABEL: add_positive_low_bound_reject:11; RV32I: # %bb.0:12; RV32I-NEXT: addi a0, a0, 204713; RV32I-NEXT: ret14;15; RV64I-LABEL: add_positive_low_bound_reject:16; RV64I: # %bb.0:17; RV64I-NEXT: addiw a0, a0, 204718; RV64I-NEXT: ret19 %1 = add i32 %a, 204720 ret i32 %121}22 23define i32 @add_positive_low_bound_accept(i32 %a) nounwind {24; RV32I-LABEL: add_positive_low_bound_accept:25; RV32I: # %bb.0:26; RV32I-NEXT: addi a0, a0, 204727; RV32I-NEXT: addi a0, a0, 128; RV32I-NEXT: ret29;30; RV64I-LABEL: add_positive_low_bound_accept:31; RV64I: # %bb.0:32; RV64I-NEXT: addi a0, a0, 204733; RV64I-NEXT: addiw a0, a0, 134; RV64I-NEXT: ret35 %1 = add i32 %a, 204836 ret i32 %137}38 39define i32 @add_positive_high_bound_accept(i32 %a) nounwind {40; RV32I-LABEL: add_positive_high_bound_accept:41; RV32I: # %bb.0:42; RV32I-NEXT: addi a0, a0, 204743; RV32I-NEXT: addi a0, a0, 204744; RV32I-NEXT: ret45;46; RV64I-LABEL: add_positive_high_bound_accept:47; RV64I: # %bb.0:48; RV64I-NEXT: addi a0, a0, 204749; RV64I-NEXT: addiw a0, a0, 204750; RV64I-NEXT: ret51 %1 = add i32 %a, 409452 ret i32 %153}54 55define i32 @add_positive_high_bound_reject(i32 %a) nounwind {56; RV32I-LABEL: add_positive_high_bound_reject:57; RV32I: # %bb.0:58; RV32I-NEXT: lui a1, 159; RV32I-NEXT: addi a1, a1, -160; RV32I-NEXT: add a0, a0, a161; RV32I-NEXT: ret62;63; RV64I-LABEL: add_positive_high_bound_reject:64; RV64I: # %bb.0:65; RV64I-NEXT: lui a1, 166; RV64I-NEXT: addi a1, a1, -167; RV64I-NEXT: addw a0, a0, a168; RV64I-NEXT: ret69 %1 = add i32 %a, 409570 ret i32 %171}72 73define i32 @add_negative_high_bound_reject(i32 %a) nounwind {74; RV32I-LABEL: add_negative_high_bound_reject:75; RV32I: # %bb.0:76; RV32I-NEXT: addi a0, a0, -204877; RV32I-NEXT: ret78;79; RV64I-LABEL: add_negative_high_bound_reject:80; RV64I: # %bb.0:81; RV64I-NEXT: addiw a0, a0, -204882; RV64I-NEXT: ret83 %1 = add i32 %a, -204884 ret i32 %185}86 87define i32 @add_negative_high_bound_accept(i32 %a) nounwind {88; RV32I-LABEL: add_negative_high_bound_accept:89; RV32I: # %bb.0:90; RV32I-NEXT: addi a0, a0, -204891; RV32I-NEXT: addi a0, a0, -192; RV32I-NEXT: ret93;94; RV64I-LABEL: add_negative_high_bound_accept:95; RV64I: # %bb.0:96; RV64I-NEXT: addi a0, a0, -204897; RV64I-NEXT: addiw a0, a0, -198; RV64I-NEXT: ret99 %1 = add i32 %a, -2049100 ret i32 %1101}102 103define i32 @add_negative_low_bound_accept(i32 %a) nounwind {104; RV32I-LABEL: add_negative_low_bound_accept:105; RV32I: # %bb.0:106; RV32I-NEXT: addi a0, a0, -2048107; RV32I-NEXT: addi a0, a0, -2048108; RV32I-NEXT: ret109;110; RV64I-LABEL: add_negative_low_bound_accept:111; RV64I: # %bb.0:112; RV64I-NEXT: addi a0, a0, -2048113; RV64I-NEXT: addiw a0, a0, -2048114; RV64I-NEXT: ret115 %1 = add i32 %a, -4096116 ret i32 %1117}118 119define i32 @add_negative_low_bound_reject(i32 %a) nounwind {120; RV32I-LABEL: add_negative_low_bound_reject:121; RV32I: # %bb.0:122; RV32I-NEXT: lui a1, 1048575123; RV32I-NEXT: addi a1, a1, -1124; RV32I-NEXT: add a0, a0, a1125; RV32I-NEXT: ret126;127; RV64I-LABEL: add_negative_low_bound_reject:128; RV64I: # %bb.0:129; RV64I-NEXT: lui a1, 1048575130; RV64I-NEXT: addi a1, a1, -1131; RV64I-NEXT: addw a0, a0, a1132; RV64I-NEXT: ret133 %1 = add i32 %a, -4097134 ret i32 %1135}136 137define i32 @add32_accept(i32 %a) nounwind {138; RV32I-LABEL: add32_accept:139; RV32I: # %bb.0:140; RV32I-NEXT: addi a0, a0, 2047141; RV32I-NEXT: addi a0, a0, 952142; RV32I-NEXT: ret143;144; RV64I-LABEL: add32_accept:145; RV64I: # %bb.0:146; RV64I-NEXT: addi a0, a0, 2047147; RV64I-NEXT: addiw a0, a0, 952148; RV64I-NEXT: ret149 %1 = add i32 %a, 2999150 ret i32 %1151}152 153define signext i32 @add32_sext_accept(i32 signext %a) nounwind {154; RV32I-LABEL: add32_sext_accept:155; RV32I: # %bb.0:156; RV32I-NEXT: addi a0, a0, 2047157; RV32I-NEXT: addi a0, a0, 952158; RV32I-NEXT: ret159;160; RV64I-LABEL: add32_sext_accept:161; RV64I: # %bb.0:162; RV64I-NEXT: addi a0, a0, 2047163; RV64I-NEXT: addiw a0, a0, 952164; RV64I-NEXT: ret165 %1 = add i32 %a, 2999166 ret i32 %1167}168 169@gv0 = global i32 0, align 4170define signext i32 @add32_sext_reject_on_rv64(i32 signext %a) nounwind {171; RV32I-LABEL: add32_sext_reject_on_rv64:172; RV32I: # %bb.0:173; RV32I-NEXT: addi a0, a0, 2047174; RV32I-NEXT: addi a0, a0, 953175; RV32I-NEXT: lui a1, %hi(gv0)176; RV32I-NEXT: sw a0, %lo(gv0)(a1)177; RV32I-NEXT: ret178;179; RV64I-LABEL: add32_sext_reject_on_rv64:180; RV64I: # %bb.0:181; RV64I-NEXT: addi a0, a0, 2047182; RV64I-NEXT: addiw a0, a0, 953183; RV64I-NEXT: lui a1, %hi(gv0)184; RV64I-NEXT: sw a0, %lo(gv0)(a1)185; RV64I-NEXT: ret186 %b = add nsw i32 %a, 3000187 store i32 %b, ptr @gv0, align 4188 ret i32 %b189}190 191define i64 @add64_accept(i64 %a) nounwind {192; RV32I-LABEL: add64_accept:193; RV32I: # %bb.0:194; RV32I-NEXT: addi a2, a0, 2047195; RV32I-NEXT: addi a2, a2, 952196; RV32I-NEXT: sltu a0, a2, a0197; RV32I-NEXT: add a1, a1, a0198; RV32I-NEXT: mv a0, a2199; RV32I-NEXT: ret200;201; RV64I-LABEL: add64_accept:202; RV64I: # %bb.0:203; RV64I-NEXT: addi a0, a0, 2047204; RV64I-NEXT: addi a0, a0, 952205; RV64I-NEXT: ret206 %1 = add i64 %a, 2999207 ret i64 %1208}209 210@ga = global i32 0, align 4211@gb = global i32 0, align 4212define void @add32_reject() nounwind {213; RV32I-LABEL: add32_reject:214; RV32I: # %bb.0:215; RV32I-NEXT: lui a0, %hi(ga)216; RV32I-NEXT: lui a1, %hi(gb)217; RV32I-NEXT: lw a2, %lo(ga)(a0)218; RV32I-NEXT: lw a3, %lo(gb)(a1)219; RV32I-NEXT: lui a4, 1220; RV32I-NEXT: addi a4, a4, -1096221; RV32I-NEXT: add a2, a2, a4222; RV32I-NEXT: add a3, a3, a4223; RV32I-NEXT: sw a2, %lo(ga)(a0)224; RV32I-NEXT: sw a3, %lo(gb)(a1)225; RV32I-NEXT: ret226;227; RV64I-LABEL: add32_reject:228; RV64I: # %bb.0:229; RV64I-NEXT: lui a0, %hi(ga)230; RV64I-NEXT: lui a1, %hi(gb)231; RV64I-NEXT: lw a2, %lo(ga)(a0)232; RV64I-NEXT: lw a3, %lo(gb)(a1)233; RV64I-NEXT: lui a4, 1234; RV64I-NEXT: addi a4, a4, -1096235; RV64I-NEXT: add a2, a2, a4236; RV64I-NEXT: add a3, a3, a4237; RV64I-NEXT: sw a2, %lo(ga)(a0)238; RV64I-NEXT: sw a3, %lo(gb)(a1)239; RV64I-NEXT: ret240 %1 = load i32, ptr @ga, align 4241 %2 = load i32, ptr @gb, align 4242 %3 = add i32 %1, 3000243 %4 = add i32 %2, 3000244 store i32 %3, ptr @ga, align 4245 store i32 %4, ptr @gb, align 4246 ret void247}248