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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32I %s4 5; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly6 7define i64 @addc_adde(i64 %a, i64 %b) nounwind {8; RV32I-LABEL: addc_adde:9; RV32I: # %bb.0:10; RV32I-NEXT: add a1, a1, a311; RV32I-NEXT: add a2, a0, a212; RV32I-NEXT: sltu a0, a2, a013; RV32I-NEXT: add a1, a1, a014; RV32I-NEXT: mv a0, a215; RV32I-NEXT: ret16 %1 = add i64 %a, %b17 ret i64 %118}19 20define i64 @subc_sube(i64 %a, i64 %b) nounwind {21; RV32I-LABEL: subc_sube:22; RV32I: # %bb.0:23; RV32I-NEXT: sltu a4, a0, a224; RV32I-NEXT: sub a1, a1, a325; RV32I-NEXT: sub a1, a1, a426; RV32I-NEXT: sub a0, a0, a227; RV32I-NEXT: ret28 %1 = sub i64 %a, %b29 ret i64 %130}31