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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV323 4; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY.5; Signed fixed point multiplication eventually expands down to an ADDCARRY.6 7define i64 @addcarry(i64 %x, i64 %y) nounwind {8; RISCV32-LABEL: addcarry:9; RISCV32: # %bb.0:10; RISCV32-NEXT: mul a4, a0, a311; RISCV32-NEXT: mulhu a5, a0, a212; RISCV32-NEXT: mul a6, a1, a213; RISCV32-NEXT: mulhu a7, a0, a314; RISCV32-NEXT: mulhu t0, a1, a215; RISCV32-NEXT: add t1, a5, a416; RISCV32-NEXT: add a7, a7, t017; RISCV32-NEXT: add a4, t1, a618; RISCV32-NEXT: sltu a5, t1, a519; RISCV32-NEXT: sltu a6, a4, t120; RISCV32-NEXT: add a5, a7, a521; RISCV32-NEXT: add a5, a5, a622; RISCV32-NEXT: mul a6, a1, a323; RISCV32-NEXT: add a5, a5, a624; RISCV32-NEXT: bgez a1, .LBB0_225; RISCV32-NEXT: # %bb.1:26; RISCV32-NEXT: sub a5, a5, a227; RISCV32-NEXT: .LBB0_2:28; RISCV32-NEXT: bgez a3, .LBB0_429; RISCV32-NEXT: # %bb.3:30; RISCV32-NEXT: sub a5, a5, a031; RISCV32-NEXT: .LBB0_4:32; RISCV32-NEXT: slli a5, a5, 3033; RISCV32-NEXT: srli a1, a4, 234; RISCV32-NEXT: slli a4, a4, 3035; RISCV32-NEXT: mul a0, a0, a236; RISCV32-NEXT: or a1, a5, a137; RISCV32-NEXT: srli a0, a0, 238; RISCV32-NEXT: or a0, a4, a039; RISCV32-NEXT: ret40 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2);41 ret i64 %tmp;42}43 44; negative test for combineCarryDiamond(): ADDCARRY not legal45define { i32, i32, i1 } @addcarry_2x32(i32 %x0, i32 %x1, i32 %y0, i32 %y1) nounwind {46; RISCV32-LABEL: addcarry_2x32:47; RISCV32: # %bb.0:48; RISCV32-NEXT: add a3, a1, a349; RISCV32-NEXT: add a4, a2, a450; RISCV32-NEXT: sltu a1, a3, a151; RISCV32-NEXT: sltu a2, a4, a252; RISCV32-NEXT: add a1, a4, a153; RISCV32-NEXT: sltu a4, a1, a454; RISCV32-NEXT: or a2, a2, a455; RISCV32-NEXT: sw a3, 0(a0)56; RISCV32-NEXT: sw a1, 4(a0)57; RISCV32-NEXT: sb a2, 8(a0)58; RISCV32-NEXT: ret59 %t0 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x0, i32 %y0)60 %s0 = extractvalue { i32, i1 } %t0, 061 %k0 = extractvalue { i32, i1 } %t0, 162 63 %t1 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x1, i32 %y1)64 %s1 = extractvalue { i32, i1 } %t1, 065 %k1 = extractvalue { i32, i1 } %t1, 166 67 %zk0 = zext i1 %k0 to i3268 %t2 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %s1, i32 %zk0)69 %s2 = extractvalue { i32, i1 } %t2, 070 %k2 = extractvalue { i32, i1 } %t2, 171 %k = or i1 %k1, %k272 73 %r0 = insertvalue { i32, i32, i1 } poison, i32 %s0, 074 %r1 = insertvalue { i32, i32, i1 } %r0, i32 %s2, 175 %r = insertvalue { i32, i32, i1 } %r1, i1 %k, 276 ret { i32, i32, i1 } %r77}78