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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64I4 5; Make sure we don't generate an addi in the loop in6; addition to the addiw. Previously we type legalize the7; setcc use using signext and the phi use using anyext.8; We now detect when it would be beneficial to replace9; anyext with signext.10 11define void @quux(i32 signext %arg, i32 signext %arg1) nounwind {12; RV64I-LABEL: quux:13; RV64I: # %bb.0: # %bb14; RV64I-NEXT: beq a1, a0, .LBB0_415; RV64I-NEXT: # %bb.1: # %bb2.preheader16; RV64I-NEXT: addi sp, sp, -1617; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill18; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill19; RV64I-NEXT: sub s0, a1, a020; RV64I-NEXT: .LBB0_2: # %bb221; RV64I-NEXT: # =>This Inner Loop Header: Depth=122; RV64I-NEXT: call hoge23; RV64I-NEXT: addiw s0, s0, -124; RV64I-NEXT: bnez s0, .LBB0_225; RV64I-NEXT: # %bb.3:26; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload27; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload28; RV64I-NEXT: addi sp, sp, 1629; RV64I-NEXT: .LBB0_4: # %bb630; RV64I-NEXT: ret31bb:32 %tmp = icmp eq i32 %arg, %arg133 br i1 %tmp, label %bb6, label %bb234 35bb2: ; preds = %bb2, %bb36 %tmp3 = phi i32 [ %tmp4, %bb2 ], [ %arg, %bb ]37 tail call void @hoge()38 %tmp4 = add nsw i32 %tmp3, 139 %tmp5 = icmp eq i32 %tmp4, %arg140 br i1 %tmp5, label %bb6, label %bb241 42bb6: ; preds = %bb2, %bb43 ret void44}45 46declare void @hoge()47 48; This ends up creating a shl with a i64 result type, but an i32 shift amount.49; Because custom type legalization for i32 is enabled, this resulted in50; LowerOperation being called for the amount. This was not expected and51; triggered an assert.52define i32 @crash(i32 signext %x, i32 signext %y, i32 signext %z) {53; RV64I-LABEL: crash:54; RV64I: # %bb.0:55; RV64I-NEXT: seqz a3, a056; RV64I-NEXT: addw a0, a1, a257; RV64I-NEXT: slli a1, a3, 358; RV64I-NEXT: .LBB1_1: # %bb59; RV64I-NEXT: # =>This Inner Loop Header: Depth=160; RV64I-NEXT: beq a0, a1, .LBB1_161; RV64I-NEXT: # %bb.2: # %bar62; RV64I-NEXT: ret63 br label %bb64 65bb:66 %a = icmp eq i32 %x, 067 %b = add i32 %y, %z68 %c = select i1 %a, i32 8, i32 069 %d = icmp eq i32 %b, %c70 br i1 %d, label %bb, label %bar71 72bar:73 ret i32 %b74}75 76; We prefer to sign extend i32 constants for phis. The default behavior in77; SelectionDAGBuilder is zero extend. We have a target hook to override it.78define i64 @sext_phi_constants(i32 signext %c) {79; RV64I-LABEL: sext_phi_constants:80; RV64I: # %bb.0:81; RV64I-NEXT: beqz a0, .LBB2_282; RV64I-NEXT: # %bb.1:83; RV64I-NEXT: li a0, -184; RV64I-NEXT: j .LBB2_385; RV64I-NEXT: .LBB2_2: # %iffalse86; RV64I-NEXT: li a0, -287; RV64I-NEXT: .LBB2_3: # %merge88; RV64I-NEXT: slli a0, a0, 3289; RV64I-NEXT: srli a0, a0, 3290; RV64I-NEXT: ret91 %a = icmp ne i32 %c, 092 br i1 %a, label %iftrue, label %iffalse93 94iftrue:95 br label %merge96 97iffalse:98 br label %merge99 100merge:101 %b = phi i32 [-1, %iftrue], [-2, %iffalse]102 %d = zext i32 %b to i64103 ret i64 %d104}105 106; We prefer to sign extend i32 non-negative values. The default behavior in107; DAGCombiner is zero extend. We have a target hook to override it.108define signext i32 @square(i32 signext %num) {109; RV64I-LABEL: square:110; RV64I: # %bb.0:111; RV64I-NEXT: mulw a0, a0, a0112; RV64I-NEXT: ret113 %mul = mul nsw i32 %num, %num114 ret i32 %mul115}116