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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7; These tests are identical to those in alu32.ll but operate on i16. They check8; that legalisation of these non-native types doesn't introduce unnecessary9; inefficiencies.10 11define i16 @addi(i16 %a) nounwind {12; RV32I-LABEL: addi:13; RV32I: # %bb.0:14; RV32I-NEXT: addi a0, a0, 115; RV32I-NEXT: ret16;17; RV64I-LABEL: addi:18; RV64I: # %bb.0:19; RV64I-NEXT: addi a0, a0, 120; RV64I-NEXT: ret21 %1 = add i16 %a, 122 ret i16 %123}24 25define i16 @slti(i16 %a) nounwind {26; RV32I-LABEL: slti:27; RV32I: # %bb.0:28; RV32I-NEXT: slli a0, a0, 1629; RV32I-NEXT: srai a0, a0, 1630; RV32I-NEXT: slti a0, a0, 231; RV32I-NEXT: ret32;33; RV64I-LABEL: slti:34; RV64I: # %bb.0:35; RV64I-NEXT: slli a0, a0, 4836; RV64I-NEXT: srai a0, a0, 4837; RV64I-NEXT: slti a0, a0, 238; RV64I-NEXT: ret39 %1 = icmp slt i16 %a, 240 %2 = zext i1 %1 to i1641 ret i16 %242}43 44define i16 @sltiu(i16 %a) nounwind {45; RV32I-LABEL: sltiu:46; RV32I: # %bb.0:47; RV32I-NEXT: slli a0, a0, 1648; RV32I-NEXT: srli a0, a0, 1649; RV32I-NEXT: sltiu a0, a0, 350; RV32I-NEXT: ret51;52; RV64I-LABEL: sltiu:53; RV64I: # %bb.0:54; RV64I-NEXT: slli a0, a0, 4855; RV64I-NEXT: srli a0, a0, 4856; RV64I-NEXT: sltiu a0, a0, 357; RV64I-NEXT: ret58 %1 = icmp ult i16 %a, 359 %2 = zext i1 %1 to i1660 ret i16 %261}62 63; Make sure we avoid an AND, if the input of an unsigned compare is known64; to be sign extended. This can occur due to InstCombine canonicalizing65; x s>= 0 && x s< 10 to x u< 10.66define i16 @sltiu_signext(i16 signext %a) nounwind {67; RV32I-LABEL: sltiu_signext:68; RV32I: # %bb.0:69; RV32I-NEXT: sltiu a0, a0, 1070; RV32I-NEXT: ret71;72; RV64I-LABEL: sltiu_signext:73; RV64I: # %bb.0:74; RV64I-NEXT: sltiu a0, a0, 1075; RV64I-NEXT: ret76 %1 = icmp ult i16 %a, 1077 %2 = zext i1 %1 to i1678 ret i16 %279}80 81define i16 @xori(i16 %a) nounwind {82; RV32I-LABEL: xori:83; RV32I: # %bb.0:84; RV32I-NEXT: xori a0, a0, 485; RV32I-NEXT: ret86;87; RV64I-LABEL: xori:88; RV64I: # %bb.0:89; RV64I-NEXT: xori a0, a0, 490; RV64I-NEXT: ret91 %1 = xor i16 %a, 492 ret i16 %193}94 95define i16 @ori(i16 %a) nounwind {96; RV32I-LABEL: ori:97; RV32I: # %bb.0:98; RV32I-NEXT: ori a0, a0, 599; RV32I-NEXT: ret100;101; RV64I-LABEL: ori:102; RV64I: # %bb.0:103; RV64I-NEXT: ori a0, a0, 5104; RV64I-NEXT: ret105 %1 = or i16 %a, 5106 ret i16 %1107}108 109define i16 @andi(i16 %a) nounwind {110; RV32I-LABEL: andi:111; RV32I: # %bb.0:112; RV32I-NEXT: andi a0, a0, 6113; RV32I-NEXT: ret114;115; RV64I-LABEL: andi:116; RV64I: # %bb.0:117; RV64I-NEXT: andi a0, a0, 6118; RV64I-NEXT: ret119 %1 = and i16 %a, 6120 ret i16 %1121}122 123define i16 @slli(i16 %a) nounwind {124; RV32I-LABEL: slli:125; RV32I: # %bb.0:126; RV32I-NEXT: slli a0, a0, 7127; RV32I-NEXT: ret128;129; RV64I-LABEL: slli:130; RV64I: # %bb.0:131; RV64I-NEXT: slli a0, a0, 7132; RV64I-NEXT: ret133 %1 = shl i16 %a, 7134 ret i16 %1135}136 137define i16 @srli(i16 %a) nounwind {138; RV32I-LABEL: srli:139; RV32I: # %bb.0:140; RV32I-NEXT: slli a0, a0, 16141; RV32I-NEXT: srli a0, a0, 22142; RV32I-NEXT: ret143;144; RV64I-LABEL: srli:145; RV64I: # %bb.0:146; RV64I-NEXT: slli a0, a0, 48147; RV64I-NEXT: srli a0, a0, 54148; RV64I-NEXT: ret149 %1 = lshr i16 %a, 6150 ret i16 %1151}152 153define i16 @srai(i16 %a) nounwind {154; RV32I-LABEL: srai:155; RV32I: # %bb.0:156; RV32I-NEXT: slli a0, a0, 16157; RV32I-NEXT: srai a0, a0, 25158; RV32I-NEXT: ret159;160; RV64I-LABEL: srai:161; RV64I: # %bb.0:162; RV64I-NEXT: slli a0, a0, 48163; RV64I-NEXT: srai a0, a0, 57164; RV64I-NEXT: ret165 %1 = ashr i16 %a, 9166 ret i16 %1167}168 169 170define i16 @add(i16 %a, i16 %b) nounwind {171; RV32I-LABEL: add:172; RV32I: # %bb.0:173; RV32I-NEXT: add a0, a0, a1174; RV32I-NEXT: ret175;176; RV64I-LABEL: add:177; RV64I: # %bb.0:178; RV64I-NEXT: add a0, a0, a1179; RV64I-NEXT: ret180 %1 = add i16 %a, %b181 ret i16 %1182}183 184define i16 @sub(i16 %a, i16 %b) nounwind {185; RV32I-LABEL: sub:186; RV32I: # %bb.0:187; RV32I-NEXT: sub a0, a0, a1188; RV32I-NEXT: ret189;190; RV64I-LABEL: sub:191; RV64I: # %bb.0:192; RV64I-NEXT: sub a0, a0, a1193; RV64I-NEXT: ret194 %1 = sub i16 %a, %b195 ret i16 %1196}197 198define i16 @sll(i16 %a, i16 %b) nounwind {199; RV32I-LABEL: sll:200; RV32I: # %bb.0:201; RV32I-NEXT: sll a0, a0, a1202; RV32I-NEXT: ret203;204; RV64I-LABEL: sll:205; RV64I: # %bb.0:206; RV64I-NEXT: sll a0, a0, a1207; RV64I-NEXT: ret208 %1 = shl i16 %a, %b209 ret i16 %1210}211 212; Test the pattern we get from C integer promotion.213define void @sll_ext(i16 %a, i32 signext %b, ptr %p) nounwind {214; RV32I-LABEL: sll_ext:215; RV32I: # %bb.0:216; RV32I-NEXT: sll a0, a0, a1217; RV32I-NEXT: sh a0, 0(a2)218; RV32I-NEXT: ret219;220; RV64I-LABEL: sll_ext:221; RV64I: # %bb.0:222; RV64I-NEXT: sllw a0, a0, a1223; RV64I-NEXT: sh a0, 0(a2)224; RV64I-NEXT: ret225 %1 = zext i16 %a to i32226 %2 = shl i32 %1, %b227 %3 = trunc i32 %2 to i16228 store i16 %3, ptr %p229 ret void230}231 232; Test the pattern we get from C integer promotion. This time with poison233; generating flags.234define void @sll_ext_drop_poison(i16 %a, i32 signext %b, ptr %p) nounwind {235; RV32I-LABEL: sll_ext_drop_poison:236; RV32I: # %bb.0:237; RV32I-NEXT: sll a0, a0, a1238; RV32I-NEXT: sh a0, 0(a2)239; RV32I-NEXT: ret240;241; RV64I-LABEL: sll_ext_drop_poison:242; RV64I: # %bb.0:243; RV64I-NEXT: sllw a0, a0, a1244; RV64I-NEXT: sh a0, 0(a2)245; RV64I-NEXT: ret246 %1 = zext i16 %a to i32247 %2 = shl nuw nsw i32 %1, %b248 %3 = trunc i32 %2 to i16249 store i16 %3, ptr %p250 ret void251}252 253define i16 @slt(i16 %a, i16 %b) nounwind {254; RV32I-LABEL: slt:255; RV32I: # %bb.0:256; RV32I-NEXT: slli a1, a1, 16257; RV32I-NEXT: slli a0, a0, 16258; RV32I-NEXT: srai a1, a1, 16259; RV32I-NEXT: srai a0, a0, 16260; RV32I-NEXT: slt a0, a0, a1261; RV32I-NEXT: ret262;263; RV64I-LABEL: slt:264; RV64I: # %bb.0:265; RV64I-NEXT: slli a1, a1, 48266; RV64I-NEXT: slli a0, a0, 48267; RV64I-NEXT: srai a1, a1, 48268; RV64I-NEXT: srai a0, a0, 48269; RV64I-NEXT: slt a0, a0, a1270; RV64I-NEXT: ret271 %1 = icmp slt i16 %a, %b272 %2 = zext i1 %1 to i16273 ret i16 %2274}275 276define i16 @sltu(i16 %a, i16 %b) nounwind {277; RV32I-LABEL: sltu:278; RV32I: # %bb.0:279; RV32I-NEXT: lui a2, 16280; RV32I-NEXT: addi a2, a2, -1281; RV32I-NEXT: and a1, a1, a2282; RV32I-NEXT: and a0, a0, a2283; RV32I-NEXT: sltu a0, a0, a1284; RV32I-NEXT: ret285;286; RV64I-LABEL: sltu:287; RV64I: # %bb.0:288; RV64I-NEXT: lui a2, 16289; RV64I-NEXT: addi a2, a2, -1290; RV64I-NEXT: and a1, a1, a2291; RV64I-NEXT: and a0, a0, a2292; RV64I-NEXT: sltu a0, a0, a1293; RV64I-NEXT: ret294 %1 = icmp ult i16 %a, %b295 %2 = zext i1 %1 to i16296 ret i16 %2297}298 299define i16 @xor(i16 %a, i16 %b) nounwind {300; RV32I-LABEL: xor:301; RV32I: # %bb.0:302; RV32I-NEXT: xor a0, a0, a1303; RV32I-NEXT: ret304;305; RV64I-LABEL: xor:306; RV64I: # %bb.0:307; RV64I-NEXT: xor a0, a0, a1308; RV64I-NEXT: ret309 %1 = xor i16 %a, %b310 ret i16 %1311}312 313define i16 @srl(i16 %a, i16 %b) nounwind {314; RV32I-LABEL: srl:315; RV32I: # %bb.0:316; RV32I-NEXT: slli a0, a0, 16317; RV32I-NEXT: srli a0, a0, 16318; RV32I-NEXT: srl a0, a0, a1319; RV32I-NEXT: ret320;321; RV64I-LABEL: srl:322; RV64I: # %bb.0:323; RV64I-NEXT: slli a0, a0, 48324; RV64I-NEXT: srli a0, a0, 48325; RV64I-NEXT: srl a0, a0, a1326; RV64I-NEXT: ret327 %1 = lshr i16 %a, %b328 ret i16 %1329}330 331define i16 @sra(i16 %a, i16 %b) nounwind {332; RV32I-LABEL: sra:333; RV32I: # %bb.0:334; RV32I-NEXT: slli a0, a0, 16335; RV32I-NEXT: srai a0, a0, 16336; RV32I-NEXT: sra a0, a0, a1337; RV32I-NEXT: ret338;339; RV64I-LABEL: sra:340; RV64I: # %bb.0:341; RV64I-NEXT: slli a0, a0, 48342; RV64I-NEXT: srai a0, a0, 48343; RV64I-NEXT: sra a0, a0, a1344; RV64I-NEXT: ret345 %1 = ashr i16 %a, %b346 ret i16 %1347}348 349define i16 @or(i16 %a, i16 %b) nounwind {350; RV32I-LABEL: or:351; RV32I: # %bb.0:352; RV32I-NEXT: or a0, a0, a1353; RV32I-NEXT: ret354;355; RV64I-LABEL: or:356; RV64I: # %bb.0:357; RV64I-NEXT: or a0, a0, a1358; RV64I-NEXT: ret359 %1 = or i16 %a, %b360 ret i16 %1361}362 363define i16 @and(i16 %a, i16 %b) nounwind {364; RV32I-LABEL: and:365; RV32I: # %bb.0:366; RV32I-NEXT: and a0, a0, a1367; RV32I-NEXT: ret368;369; RV64I-LABEL: and:370; RV64I: # %bb.0:371; RV64I-NEXT: and a0, a0, a1372; RV64I-NEXT: ret373 %1 = and i16 %a, %b374 ret i16 %1375}376