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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7; These tests are each targeted at a particular RISC-V ALU instruction. Most8; other files in this folder exercise LLVM IR instructions that don't directly9; match a RISC-V instruction.10 11; Register-immediate instructions.12 13define i32 @addi(i32 %a) nounwind {14; RV32I-LABEL: addi:15; RV32I: # %bb.0:16; RV32I-NEXT: addi a0, a0, 117; RV32I-NEXT: ret18;19; RV64I-LABEL: addi:20; RV64I: # %bb.0:21; RV64I-NEXT: addiw a0, a0, 122; RV64I-NEXT: ret23 %1 = add i32 %a, 124 ret i32 %125}26 27define i32 @slti(i32 %a) nounwind {28; RV32I-LABEL: slti:29; RV32I: # %bb.0:30; RV32I-NEXT: slti a0, a0, 231; RV32I-NEXT: ret32;33; RV64I-LABEL: slti:34; RV64I: # %bb.0:35; RV64I-NEXT: sext.w a0, a036; RV64I-NEXT: slti a0, a0, 237; RV64I-NEXT: ret38 %1 = icmp slt i32 %a, 239 %2 = zext i1 %1 to i3240 ret i32 %241}42 43define i32 @sltiu(i32 %a) nounwind {44; RV32I-LABEL: sltiu:45; RV32I: # %bb.0:46; RV32I-NEXT: sltiu a0, a0, 347; RV32I-NEXT: ret48;49; RV64I-LABEL: sltiu:50; RV64I: # %bb.0:51; RV64I-NEXT: sext.w a0, a052; RV64I-NEXT: sltiu a0, a0, 353; RV64I-NEXT: ret54 %1 = icmp ult i32 %a, 355 %2 = zext i1 %1 to i3256 ret i32 %257}58 59define i32 @xori(i32 %a) nounwind {60; RV32I-LABEL: xori:61; RV32I: # %bb.0:62; RV32I-NEXT: xori a0, a0, 463; RV32I-NEXT: ret64;65; RV64I-LABEL: xori:66; RV64I: # %bb.0:67; RV64I-NEXT: xori a0, a0, 468; RV64I-NEXT: ret69 %1 = xor i32 %a, 470 ret i32 %171}72 73define i32 @ori(i32 %a) nounwind {74; RV32I-LABEL: ori:75; RV32I: # %bb.0:76; RV32I-NEXT: ori a0, a0, 577; RV32I-NEXT: ret78;79; RV64I-LABEL: ori:80; RV64I: # %bb.0:81; RV64I-NEXT: ori a0, a0, 582; RV64I-NEXT: ret83 %1 = or i32 %a, 584 ret i32 %185}86 87define i32 @andi(i32 %a) nounwind {88; RV32I-LABEL: andi:89; RV32I: # %bb.0:90; RV32I-NEXT: andi a0, a0, 691; RV32I-NEXT: ret92;93; RV64I-LABEL: andi:94; RV64I: # %bb.0:95; RV64I-NEXT: andi a0, a0, 696; RV64I-NEXT: ret97 %1 = and i32 %a, 698 ret i32 %199}100 101define i32 @slli(i32 %a) nounwind {102; RV32I-LABEL: slli:103; RV32I: # %bb.0:104; RV32I-NEXT: slli a0, a0, 7105; RV32I-NEXT: ret106;107; RV64I-LABEL: slli:108; RV64I: # %bb.0:109; RV64I-NEXT: slliw a0, a0, 7110; RV64I-NEXT: ret111 %1 = shl i32 %a, 7112 ret i32 %1113}114 115define i32 @srli(i32 %a) nounwind {116; RV32I-LABEL: srli:117; RV32I: # %bb.0:118; RV32I-NEXT: srli a0, a0, 8119; RV32I-NEXT: ret120;121; RV64I-LABEL: srli:122; RV64I: # %bb.0:123; RV64I-NEXT: srliw a0, a0, 8124; RV64I-NEXT: ret125 %1 = lshr i32 %a, 8126 ret i32 %1127}128 129; This makes sure SimplifyDemandedBits doesn't prevent us from matching SRLIW130; on RV64.131define i32 @srli_demandedbits(i32 %0) {132; RV32I-LABEL: srli_demandedbits:133; RV32I: # %bb.0:134; RV32I-NEXT: srli a0, a0, 3135; RV32I-NEXT: ori a0, a0, 1136; RV32I-NEXT: ret137;138; RV64I-LABEL: srli_demandedbits:139; RV64I: # %bb.0:140; RV64I-NEXT: srliw a0, a0, 3141; RV64I-NEXT: ori a0, a0, 1142; RV64I-NEXT: ret143 %2 = lshr i32 %0, 3144 %3 = or i32 %2, 1145 ret i32 %3146}147 148define i32 @srai(i32 %a) nounwind {149; RV32I-LABEL: srai:150; RV32I: # %bb.0:151; RV32I-NEXT: srai a0, a0, 9152; RV32I-NEXT: ret153;154; RV64I-LABEL: srai:155; RV64I: # %bb.0:156; RV64I-NEXT: sraiw a0, a0, 9157; RV64I-NEXT: ret158 %1 = ashr i32 %a, 9159 ret i32 %1160}161 162; Register-register instructions163 164define i32 @add(i32 %a, i32 %b) nounwind {165; RV32I-LABEL: add:166; RV32I: # %bb.0:167; RV32I-NEXT: add a0, a0, a1168; RV32I-NEXT: ret169;170; RV64I-LABEL: add:171; RV64I: # %bb.0:172; RV64I-NEXT: addw a0, a0, a1173; RV64I-NEXT: ret174 %1 = add i32 %a, %b175 ret i32 %1176}177 178define i32 @sub(i32 %a, i32 %b) nounwind {179; RV32I-LABEL: sub:180; RV32I: # %bb.0:181; RV32I-NEXT: sub a0, a0, a1182; RV32I-NEXT: ret183;184; RV64I-LABEL: sub:185; RV64I: # %bb.0:186; RV64I-NEXT: subw a0, a0, a1187; RV64I-NEXT: ret188 %1 = sub i32 %a, %b189 ret i32 %1190}191 192define i32 @sub_negative_constant_lhs(i32 %a) nounwind {193; RV32I-LABEL: sub_negative_constant_lhs:194; RV32I: # %bb.0:195; RV32I-NEXT: li a1, -2196; RV32I-NEXT: sub a0, a1, a0197; RV32I-NEXT: ret198;199; RV64I-LABEL: sub_negative_constant_lhs:200; RV64I: # %bb.0:201; RV64I-NEXT: li a1, -2202; RV64I-NEXT: subw a0, a1, a0203; RV64I-NEXT: ret204 %1 = sub i32 -2, %a205 ret i32 %1206}207 208define i32 @sll(i32 %a, i32 %b) nounwind {209; RV32I-LABEL: sll:210; RV32I: # %bb.0:211; RV32I-NEXT: sll a0, a0, a1212; RV32I-NEXT: ret213;214; RV64I-LABEL: sll:215; RV64I: # %bb.0:216; RV64I-NEXT: sllw a0, a0, a1217; RV64I-NEXT: ret218 %1 = shl i32 %a, %b219 ret i32 %1220}221 222define i32 @sll_negative_constant_lhs(i32 %a) nounwind {223; RV32I-LABEL: sll_negative_constant_lhs:224; RV32I: # %bb.0:225; RV32I-NEXT: li a1, -1226; RV32I-NEXT: sll a0, a1, a0227; RV32I-NEXT: ret228;229; RV64I-LABEL: sll_negative_constant_lhs:230; RV64I: # %bb.0:231; RV64I-NEXT: li a1, -1232; RV64I-NEXT: sllw a0, a1, a0233; RV64I-NEXT: ret234 %1 = shl i32 -1, %a235 ret i32 %1236}237 238define i32 @slt(i32 %a, i32 %b) nounwind {239; RV32I-LABEL: slt:240; RV32I: # %bb.0:241; RV32I-NEXT: slt a0, a0, a1242; RV32I-NEXT: ret243;244; RV64I-LABEL: slt:245; RV64I: # %bb.0:246; RV64I-NEXT: sext.w a1, a1247; RV64I-NEXT: sext.w a0, a0248; RV64I-NEXT: slt a0, a0, a1249; RV64I-NEXT: ret250 %1 = icmp slt i32 %a, %b251 %2 = zext i1 %1 to i32252 ret i32 %2253}254 255define i32 @sltu(i32 %a, i32 %b) nounwind {256; RV32I-LABEL: sltu:257; RV32I: # %bb.0:258; RV32I-NEXT: sltu a0, a0, a1259; RV32I-NEXT: ret260;261; RV64I-LABEL: sltu:262; RV64I: # %bb.0:263; RV64I-NEXT: sext.w a1, a1264; RV64I-NEXT: sext.w a0, a0265; RV64I-NEXT: sltu a0, a0, a1266; RV64I-NEXT: ret267 %1 = icmp ult i32 %a, %b268 %2 = zext i1 %1 to i32269 ret i32 %2270}271 272define i32 @xor(i32 %a, i32 %b) nounwind {273; RV32I-LABEL: xor:274; RV32I: # %bb.0:275; RV32I-NEXT: xor a0, a0, a1276; RV32I-NEXT: ret277;278; RV64I-LABEL: xor:279; RV64I: # %bb.0:280; RV64I-NEXT: xor a0, a0, a1281; RV64I-NEXT: ret282 %1 = xor i32 %a, %b283 ret i32 %1284}285 286define i32 @srl(i32 %a, i32 %b) nounwind {287; RV32I-LABEL: srl:288; RV32I: # %bb.0:289; RV32I-NEXT: srl a0, a0, a1290; RV32I-NEXT: ret291;292; RV64I-LABEL: srl:293; RV64I: # %bb.0:294; RV64I-NEXT: srlw a0, a0, a1295; RV64I-NEXT: ret296 %1 = lshr i32 %a, %b297 ret i32 %1298}299 300define i32 @srl_negative_constant_lhs(i32 %a) nounwind {301; RV32I-LABEL: srl_negative_constant_lhs:302; RV32I: # %bb.0:303; RV32I-NEXT: li a1, -1304; RV32I-NEXT: srl a0, a1, a0305; RV32I-NEXT: ret306;307; RV64I-LABEL: srl_negative_constant_lhs:308; RV64I: # %bb.0:309; RV64I-NEXT: li a1, -1310; RV64I-NEXT: srlw a0, a1, a0311; RV64I-NEXT: ret312 %1 = lshr i32 -1, %a313 ret i32 %1314}315 316define i32 @sra(i32 %a, i32 %b) nounwind {317; RV32I-LABEL: sra:318; RV32I: # %bb.0:319; RV32I-NEXT: sra a0, a0, a1320; RV32I-NEXT: ret321;322; RV64I-LABEL: sra:323; RV64I: # %bb.0:324; RV64I-NEXT: sraw a0, a0, a1325; RV64I-NEXT: ret326 %1 = ashr i32 %a, %b327 ret i32 %1328}329 330define i32 @sra_negative_constant_lhs(i32 %a) nounwind {331; RV32I-LABEL: sra_negative_constant_lhs:332; RV32I: # %bb.0:333; RV32I-NEXT: lui a1, 524288334; RV32I-NEXT: sra a0, a1, a0335; RV32I-NEXT: ret336;337; RV64I-LABEL: sra_negative_constant_lhs:338; RV64I: # %bb.0:339; RV64I-NEXT: lui a1, 524288340; RV64I-NEXT: sraw a0, a1, a0341; RV64I-NEXT: ret342 %1 = ashr i32 2147483648, %a343 ret i32 %1344}345 346define i32 @or(i32 %a, i32 %b) nounwind {347; RV32I-LABEL: or:348; RV32I: # %bb.0:349; RV32I-NEXT: or a0, a0, a1350; RV32I-NEXT: ret351;352; RV64I-LABEL: or:353; RV64I: # %bb.0:354; RV64I-NEXT: or a0, a0, a1355; RV64I-NEXT: ret356 %1 = or i32 %a, %b357 ret i32 %1358}359 360define i32 @and(i32 %a, i32 %b) nounwind {361; RV32I-LABEL: and:362; RV32I: # %bb.0:363; RV32I-NEXT: and a0, a0, a1364; RV32I-NEXT: ret365;366; RV64I-LABEL: and:367; RV64I: # %bb.0:368; RV64I-NEXT: and a0, a0, a1369; RV64I-NEXT: ret370 %1 = and i32 %a, %b371 ret i32 %1372}373