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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7; These tests are identical to those in alu32.ll but operate on i8. They check8; that legalisation of these non-native types doesn't introduce unnecessary9; inefficiencies.10 11define i8 @addi(i8 %a) nounwind {12; RV32I-LABEL: addi:13; RV32I: # %bb.0:14; RV32I-NEXT: addi a0, a0, 115; RV32I-NEXT: ret16;17; RV64I-LABEL: addi:18; RV64I: # %bb.0:19; RV64I-NEXT: addi a0, a0, 120; RV64I-NEXT: ret21 %1 = add i8 %a, 122 ret i8 %123}24 25define i8 @slti(i8 %a) nounwind {26; RV32I-LABEL: slti:27; RV32I: # %bb.0:28; RV32I-NEXT: slli a0, a0, 2429; RV32I-NEXT: srai a0, a0, 2430; RV32I-NEXT: slti a0, a0, 231; RV32I-NEXT: ret32;33; RV64I-LABEL: slti:34; RV64I: # %bb.0:35; RV64I-NEXT: slli a0, a0, 5636; RV64I-NEXT: srai a0, a0, 5637; RV64I-NEXT: slti a0, a0, 238; RV64I-NEXT: ret39 %1 = icmp slt i8 %a, 240 %2 = zext i1 %1 to i841 ret i8 %242}43 44define i8 @sltiu(i8 %a) nounwind {45; RV32I-LABEL: sltiu:46; RV32I: # %bb.0:47; RV32I-NEXT: zext.b a0, a048; RV32I-NEXT: sltiu a0, a0, 349; RV32I-NEXT: ret50;51; RV64I-LABEL: sltiu:52; RV64I: # %bb.0:53; RV64I-NEXT: zext.b a0, a054; RV64I-NEXT: sltiu a0, a0, 355; RV64I-NEXT: ret56 %1 = icmp ult i8 %a, 357 %2 = zext i1 %1 to i858 ret i8 %259}60 61; Make sure we avoid an AND, if the input of an unsigned compare is known62; to be sign extended. This can occur due to InstCombine canonicalizing63; x s>= 0 && x s< 10 to x u< 10.64define i8 @sltiu_signext(i8 signext %a) nounwind {65; RV32I-LABEL: sltiu_signext:66; RV32I: # %bb.0:67; RV32I-NEXT: sltiu a0, a0, 1068; RV32I-NEXT: ret69;70; RV64I-LABEL: sltiu_signext:71; RV64I: # %bb.0:72; RV64I-NEXT: sltiu a0, a0, 1073; RV64I-NEXT: ret74 %1 = icmp ult i8 %a, 1075 %2 = zext i1 %1 to i876 ret i8 %277}78 79define i8 @xori(i8 %a) nounwind {80; RV32I-LABEL: xori:81; RV32I: # %bb.0:82; RV32I-NEXT: xori a0, a0, 483; RV32I-NEXT: ret84;85; RV64I-LABEL: xori:86; RV64I: # %bb.0:87; RV64I-NEXT: xori a0, a0, 488; RV64I-NEXT: ret89 %1 = xor i8 %a, 490 ret i8 %191}92 93define i8 @ori(i8 %a) nounwind {94; RV32I-LABEL: ori:95; RV32I: # %bb.0:96; RV32I-NEXT: ori a0, a0, 597; RV32I-NEXT: ret98;99; RV64I-LABEL: ori:100; RV64I: # %bb.0:101; RV64I-NEXT: ori a0, a0, 5102; RV64I-NEXT: ret103 %1 = or i8 %a, 5104 ret i8 %1105}106 107define i8 @andi(i8 %a) nounwind {108; RV32I-LABEL: andi:109; RV32I: # %bb.0:110; RV32I-NEXT: andi a0, a0, 6111; RV32I-NEXT: ret112;113; RV64I-LABEL: andi:114; RV64I: # %bb.0:115; RV64I-NEXT: andi a0, a0, 6116; RV64I-NEXT: ret117 %1 = and i8 %a, 6118 ret i8 %1119}120 121define i8 @slli(i8 %a) nounwind {122; RV32I-LABEL: slli:123; RV32I: # %bb.0:124; RV32I-NEXT: slli a0, a0, 7125; RV32I-NEXT: ret126;127; RV64I-LABEL: slli:128; RV64I: # %bb.0:129; RV64I-NEXT: slli a0, a0, 7130; RV64I-NEXT: ret131 %1 = shl i8 %a, 7132 ret i8 %1133}134 135define i8 @srli(i8 %a) nounwind {136; RV32I-LABEL: srli:137; RV32I: # %bb.0:138; RV32I-NEXT: slli a0, a0, 24139; RV32I-NEXT: srli a0, a0, 30140; RV32I-NEXT: ret141;142; RV64I-LABEL: srli:143; RV64I: # %bb.0:144; RV64I-NEXT: slli a0, a0, 56145; RV64I-NEXT: srli a0, a0, 62146; RV64I-NEXT: ret147 %1 = lshr i8 %a, 6148 ret i8 %1149}150 151define i8 @srai(i8 %a) nounwind {152; RV32I-LABEL: srai:153; RV32I: # %bb.0:154; RV32I-NEXT: slli a0, a0, 24155; RV32I-NEXT: srai a0, a0, 29156; RV32I-NEXT: ret157;158; RV64I-LABEL: srai:159; RV64I: # %bb.0:160; RV64I-NEXT: slli a0, a0, 56161; RV64I-NEXT: srai a0, a0, 61162; RV64I-NEXT: ret163 %1 = ashr i8 %a, 5164 ret i8 %1165}166 167 168define i8 @add(i8 %a, i8 %b) nounwind {169; RV32I-LABEL: add:170; RV32I: # %bb.0:171; RV32I-NEXT: add a0, a0, a1172; RV32I-NEXT: ret173;174; RV64I-LABEL: add:175; RV64I: # %bb.0:176; RV64I-NEXT: add a0, a0, a1177; RV64I-NEXT: ret178 %1 = add i8 %a, %b179 ret i8 %1180}181 182define i8 @sub(i8 %a, i8 %b) nounwind {183; RV32I-LABEL: sub:184; RV32I: # %bb.0:185; RV32I-NEXT: sub a0, a0, a1186; RV32I-NEXT: ret187;188; RV64I-LABEL: sub:189; RV64I: # %bb.0:190; RV64I-NEXT: sub a0, a0, a1191; RV64I-NEXT: ret192 %1 = sub i8 %a, %b193 ret i8 %1194}195 196define i8 @sll(i8 %a, i8 %b) nounwind {197; RV32I-LABEL: sll:198; RV32I: # %bb.0:199; RV32I-NEXT: sll a0, a0, a1200; RV32I-NEXT: ret201;202; RV64I-LABEL: sll:203; RV64I: # %bb.0:204; RV64I-NEXT: sll a0, a0, a1205; RV64I-NEXT: ret206 %1 = shl i8 %a, %b207 ret i8 %1208}209 210; Test the pattern we get from C integer promotion.211define void @sll_ext(i8 %a, i32 signext %b, ptr %p) nounwind {212; RV32I-LABEL: sll_ext:213; RV32I: # %bb.0:214; RV32I-NEXT: sll a0, a0, a1215; RV32I-NEXT: sb a0, 0(a2)216; RV32I-NEXT: ret217;218; RV64I-LABEL: sll_ext:219; RV64I: # %bb.0:220; RV64I-NEXT: sllw a0, a0, a1221; RV64I-NEXT: sb a0, 0(a2)222; RV64I-NEXT: ret223 %1 = zext i8 %a to i32224 %2 = shl i32 %1, %b225 %3 = trunc i32 %2 to i8226 store i8 %3, ptr %p227 ret void228}229 230; Test the pattern we get from C integer promotion. This time with poison231; generating flags.232define void @sll_ext_drop_poison(i8 %a, i32 signext %b, ptr %p) nounwind {233; RV32I-LABEL: sll_ext_drop_poison:234; RV32I: # %bb.0:235; RV32I-NEXT: sll a0, a0, a1236; RV32I-NEXT: sb a0, 0(a2)237; RV32I-NEXT: ret238;239; RV64I-LABEL: sll_ext_drop_poison:240; RV64I: # %bb.0:241; RV64I-NEXT: sllw a0, a0, a1242; RV64I-NEXT: sb a0, 0(a2)243; RV64I-NEXT: ret244 %1 = zext i8 %a to i32245 %2 = shl nuw nsw i32 %1, %b246 %3 = trunc i32 %2 to i8247 store i8 %3, ptr %p248 ret void249}250 251define i8 @slt(i8 %a, i8 %b) nounwind {252; RV32I-LABEL: slt:253; RV32I: # %bb.0:254; RV32I-NEXT: slli a1, a1, 24255; RV32I-NEXT: slli a0, a0, 24256; RV32I-NEXT: srai a1, a1, 24257; RV32I-NEXT: srai a0, a0, 24258; RV32I-NEXT: slt a0, a0, a1259; RV32I-NEXT: ret260;261; RV64I-LABEL: slt:262; RV64I: # %bb.0:263; RV64I-NEXT: slli a1, a1, 56264; RV64I-NEXT: slli a0, a0, 56265; RV64I-NEXT: srai a1, a1, 56266; RV64I-NEXT: srai a0, a0, 56267; RV64I-NEXT: slt a0, a0, a1268; RV64I-NEXT: ret269 %1 = icmp slt i8 %a, %b270 %2 = zext i1 %1 to i8271 ret i8 %2272}273 274define i8 @sltu(i8 %a, i8 %b) nounwind {275; RV32I-LABEL: sltu:276; RV32I: # %bb.0:277; RV32I-NEXT: zext.b a1, a1278; RV32I-NEXT: zext.b a0, a0279; RV32I-NEXT: sltu a0, a0, a1280; RV32I-NEXT: ret281;282; RV64I-LABEL: sltu:283; RV64I: # %bb.0:284; RV64I-NEXT: zext.b a1, a1285; RV64I-NEXT: zext.b a0, a0286; RV64I-NEXT: sltu a0, a0, a1287; RV64I-NEXT: ret288 %1 = icmp ult i8 %a, %b289 %2 = zext i1 %1 to i8290 ret i8 %2291}292 293define i8 @xor(i8 %a, i8 %b) nounwind {294; RV32I-LABEL: xor:295; RV32I: # %bb.0:296; RV32I-NEXT: xor a0, a0, a1297; RV32I-NEXT: ret298;299; RV64I-LABEL: xor:300; RV64I: # %bb.0:301; RV64I-NEXT: xor a0, a0, a1302; RV64I-NEXT: ret303 %1 = xor i8 %a, %b304 ret i8 %1305}306 307define i8 @srl(i8 %a, i8 %b) nounwind {308; RV32I-LABEL: srl:309; RV32I: # %bb.0:310; RV32I-NEXT: zext.b a0, a0311; RV32I-NEXT: srl a0, a0, a1312; RV32I-NEXT: ret313;314; RV64I-LABEL: srl:315; RV64I: # %bb.0:316; RV64I-NEXT: zext.b a0, a0317; RV64I-NEXT: srl a0, a0, a1318; RV64I-NEXT: ret319 %1 = lshr i8 %a, %b320 ret i8 %1321}322 323define i8 @sra(i8 %a, i8 %b) nounwind {324; RV32I-LABEL: sra:325; RV32I: # %bb.0:326; RV32I-NEXT: slli a0, a0, 24327; RV32I-NEXT: srai a0, a0, 24328; RV32I-NEXT: sra a0, a0, a1329; RV32I-NEXT: ret330;331; RV64I-LABEL: sra:332; RV64I: # %bb.0:333; RV64I-NEXT: slli a0, a0, 56334; RV64I-NEXT: srai a0, a0, 56335; RV64I-NEXT: sra a0, a0, a1336; RV64I-NEXT: ret337 %1 = ashr i8 %a, %b338 ret i8 %1339}340 341define i8 @or(i8 %a, i8 %b) nounwind {342; RV32I-LABEL: or:343; RV32I: # %bb.0:344; RV32I-NEXT: or a0, a0, a1345; RV32I-NEXT: ret346;347; RV64I-LABEL: or:348; RV64I: # %bb.0:349; RV64I-NEXT: or a0, a0, a1350; RV64I-NEXT: ret351 %1 = or i8 %a, %b352 ret i8 %1353}354 355define i8 @and(i8 %a, i8 %b) nounwind {356; RV32I-LABEL: and:357; RV32I: # %bb.0:358; RV32I-NEXT: and a0, a0, a1359; RV32I-NEXT: ret360;361; RV64I-LABEL: and:362; RV64I: # %bb.0:363; RV64I-NEXT: and a0, a0, a1364; RV64I-NEXT: ret365 %1 = and i8 %a, %b366 ret i8 %1367}368