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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7define i32 @and_add_lsr(i32 %x, i32 %y) {8; RV32I-LABEL: and_add_lsr:9; RV32I: # %bb.0:10; RV32I-NEXT: addi a0, a0, -111; RV32I-NEXT: srli a1, a1, 2012; RV32I-NEXT: and a0, a1, a013; RV32I-NEXT: ret14;15; RV64I-LABEL: and_add_lsr:16; RV64I: # %bb.0:17; RV64I-NEXT: addiw a0, a0, -118; RV64I-NEXT: srliw a1, a1, 2019; RV64I-NEXT: and a0, a1, a020; RV64I-NEXT: ret21 %1 = add i32 %x, 409522 %2 = lshr i32 %y, 2023 %r = and i32 %2, %124 ret i32 %r25}26 27; Make sure we don't crash on fixed length vectors28define <2 x i32> @and_add_lsr_vec(<2 x i32> %x, <2 x i32> %y) {29; RV32I-LABEL: and_add_lsr_vec:30; RV32I: # %bb.0:31; RV32I-NEXT: lui a0, 132; RV32I-NEXT: addi a0, a0, -133; RV32I-NEXT: vsetivli zero, 2, e32, mf2, ta, ma34; RV32I-NEXT: vadd.vx v8, v8, a035; RV32I-NEXT: vsrl.vi v9, v9, 2036; RV32I-NEXT: vand.vv v8, v9, v837; RV32I-NEXT: ret38;39; RV64I-LABEL: and_add_lsr_vec:40; RV64I: # %bb.0:41; RV64I-NEXT: lui a0, 142; RV64I-NEXT: addi a0, a0, -143; RV64I-NEXT: vsetivli zero, 2, e32, mf2, ta, ma44; RV64I-NEXT: vadd.vx v8, v8, a045; RV64I-NEXT: vsrl.vi v9, v9, 2046; RV64I-NEXT: vand.vv v8, v9, v847; RV64I-NEXT: ret48 %1 = add <2 x i32> %x, splat (i32 4095)49 %2 = lshr <2 x i32> %y, splat (i32 20)50 %r = and <2 x i32> %2, %151 ret <2 x i32> %r52}53 54; Make sure we don't crash on scalable vectors55define <vscale x 2 x i32> @and_add_lsr_vec2(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {56; RV32I-LABEL: and_add_lsr_vec2:57; RV32I: # %bb.0:58; RV32I-NEXT: lui a0, 159; RV32I-NEXT: addi a0, a0, -160; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma61; RV32I-NEXT: vadd.vx v8, v8, a062; RV32I-NEXT: vsrl.vi v9, v9, 2063; RV32I-NEXT: vand.vv v8, v9, v864; RV32I-NEXT: ret65;66; RV64I-LABEL: and_add_lsr_vec2:67; RV64I: # %bb.0:68; RV64I-NEXT: lui a0, 169; RV64I-NEXT: addi a0, a0, -170; RV64I-NEXT: vsetvli a1, zero, e32, m1, ta, ma71; RV64I-NEXT: vadd.vx v8, v8, a072; RV64I-NEXT: vsrl.vi v9, v9, 2073; RV64I-NEXT: vand.vv v8, v9, v874; RV64I-NEXT: ret75 %1 = add <vscale x 2 x i32> %x, splat (i32 4095)76 %2 = lshr <vscale x 2 x i32> %y, splat (i32 20)77 %r = and <vscale x 2 x i32> %2, %178 ret <vscale x 2 x i32> %r79}80