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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK,RV644 5define i1 @test1(i64 %x) {6; RV32-LABEL: test1:7; RV32: # %bb.0:8; RV32-NEXT: slli a2, a1, 29; RV32-NEXT: srli a0, a0, 3010; RV32-NEXT: srai a1, a1, 3011; RV32-NEXT: or a0, a0, a212; RV32-NEXT: xori a0, a0, -213; RV32-NEXT: not a1, a114; RV32-NEXT: or a0, a0, a115; RV32-NEXT: seqz a0, a016; RV32-NEXT: ret17;18; RV64-LABEL: test1:19; RV64: # %bb.0:20; RV64-NEXT: srai a0, a0, 3021; RV64-NEXT: addi a0, a0, 222; RV64-NEXT: seqz a0, a023; RV64-NEXT: ret24 %a = and i64 %x, -107374182425 %b = icmp eq i64 %a, -214748364826 ret i1 %b27}28 29define i1 @test2(i32 signext %x) {30; CHECK-LABEL: test2:31; CHECK: # %bb.0:32; CHECK-NEXT: srli a0, a0, 3033; CHECK-NEXT: seqz a0, a034; CHECK-NEXT: ret35 %a = and i32 %x, -107374182436 %b = icmp eq i32 %a, 037 ret i1 %b38}39 40define i1 @test3(i32 signext %x) {41; CHECK-LABEL: test3:42; CHECK: # %bb.0:43; CHECK-NEXT: srli a0, a0, 2944; CHECK-NEXT: snez a0, a045; CHECK-NEXT: ret46 %a = and i32 %x, -53687091247 %b = icmp ne i32 %a, 048 ret i1 %b49}50 51define i1 @test4(i64 %x) {52; RV32-LABEL: test4:53; RV32: # %bb.0:54; RV32-NEXT: srli a1, a1, 1455; RV32-NEXT: seqz a0, a156; RV32-NEXT: ret57;58; RV64-LABEL: test4:59; RV64: # %bb.0:60; RV64-NEXT: srli a0, a0, 4661; RV64-NEXT: seqz a0, a062; RV64-NEXT: ret63 %a = and i64 %x, -7036874417766464 %b = icmp eq i64 %a, 065 ret i1 %b66}67 68define i1 @test5(i64 %x) {69; RV32-LABEL: test5:70; RV32: # %bb.0:71; RV32-NEXT: srli a0, a0, 2972; RV32-NEXT: seqz a0, a073; RV32-NEXT: ret74;75; RV64-LABEL: test5:76; RV64: # %bb.0:77; RV64-NEXT: sraiw a0, a0, 2978; RV64-NEXT: seqz a0, a079; RV64-NEXT: ret80 %a = and i64 %x, u0xE000000081 %b = icmp eq i64 %a, 082 ret i1 %b83}84 85define i1 @test6(i64 %x) {86; RV32-LABEL: test6:87; RV32: # %bb.0:88; RV32-NEXT: srli a0, a0, 2989; RV32-NEXT: snez a0, a090; RV32-NEXT: ret91;92; RV64-LABEL: test6:93; RV64: # %bb.0:94; RV64-NEXT: sraiw a0, a0, 2995; RV64-NEXT: snez a0, a096; RV64-NEXT: ret97 %a = and i64 %x, u0xE000000098 %b = icmp ne i64 %a, 099 ret i1 %b100}101 102define i1 @test7(i64 %x) {103; RV32-LABEL: test7:104; RV32: # %bb.0:105; RV32-NEXT: srli a0, a0, 29106; RV32-NEXT: addi a0, a0, -6107; RV32-NEXT: seqz a0, a0108; RV32-NEXT: ret109;110; RV64-LABEL: test7:111; RV64: # %bb.0:112; RV64-NEXT: sraiw a0, a0, 29113; RV64-NEXT: addi a0, a0, 2114; RV64-NEXT: seqz a0, a0115; RV64-NEXT: ret116 %a = and i64 %x, u0xE0000000117 %b = icmp eq i64 %a, u0xC0000000118 ret i1 %b119}120 121define i1 @test8(i64 %x) {122; RV32-LABEL: test8:123; RV32: # %bb.0:124; RV32-NEXT: srai a0, a0, 20125; RV32-NEXT: xori a0, a0, -2048126; RV32-NEXT: snez a0, a0127; RV32-NEXT: ret128;129; RV64-LABEL: test8:130; RV64: # %bb.0:131; RV64-NEXT: sraiw a0, a0, 20132; RV64-NEXT: xori a0, a0, -2048133; RV64-NEXT: snez a0, a0134; RV64-NEXT: ret135 %a = and i64 %x, u0xFFF00000136 %b = icmp ne i64 %a, u0x80000000137 ret i1 %b138}139 140define i1 @test9(i64 %x) {141; RV32-LABEL: test9:142; RV32: # %bb.0:143; RV32-NEXT: srli a0, a0, 16144; RV32-NEXT: addi a0, a0, -2048145; RV32-NEXT: seqz a0, a0146; RV32-NEXT: ret147;148; RV64-LABEL: test9:149; RV64: # %bb.0:150; RV64-NEXT: sraiw a0, a0, 16151; RV64-NEXT: addi a0, a0, -2048152; RV64-NEXT: seqz a0, a0153; RV64-NEXT: ret154 %a = and i64 %x, u0xFFFF0000155 %b = icmp eq i64 %a, u0x08000000156 ret i1 %b157}158 159; Make sure the and constant doesn't get converted to an opaque constant by160; ConstantHoisting. If it's an opaque constant, we'll have addi -16 and addi 15.161define i64 @test10(i64 %0) #0 {162; RV32-LABEL: test10:163; RV32: # %bb.0: # %entry164; RV32-NEXT: addi a0, a0, -1165; RV32-NEXT: andi a0, a0, -16166; RV32-NEXT: snez a0, a0167; RV32-NEXT: li a1, 0168; RV32-NEXT: ret169;170; RV64-LABEL: test10:171; RV64: # %bb.0: # %entry172; RV64-NEXT: addi a0, a0, -1173; RV64-NEXT: sraiw a0, a0, 4174; RV64-NEXT: snez a0, a0175; RV64-NEXT: ret176entry:177 %1 = add nuw nsw i64 %0, u0xffffffff178 %2 = and i64 %1, u0xfffffff0179 %3 = icmp ne i64 %2, 0180 %4 = zext i1 %3 to i64181 ret i64 %4182}183 184; Make sure the and constant doesn't get converted to an opaque constant by185; ConstantHoisting. If it's an opaque constant, we'll have addi -16 and addi 15.186define i64 @test11(i64 %0) #0 {187; RV32-LABEL: test11:188; RV32: # %bb.0: # %entry189; RV32-NEXT: addi a0, a0, -1190; RV32-NEXT: srai a0, a0, 4191; RV32-NEXT: addi a0, a0, 1621192; RV32-NEXT: seqz a0, a0193; RV32-NEXT: li a1, 0194; RV32-NEXT: ret195;196; RV64-LABEL: test11:197; RV64: # %bb.0: # %entry198; RV64-NEXT: addi a0, a0, -1199; RV64-NEXT: sraiw a0, a0, 4200; RV64-NEXT: addi a0, a0, 1621201; RV64-NEXT: seqz a0, a0202; RV64-NEXT: ret203entry:204 %1 = add nuw nsw i64 %0, u0xffffffff205 %2 = and i64 %1, u0xfffffff0206 %3 = icmp eq i64 %2, u0xffff9ab0207 %4 = zext i1 %3 to i64208 ret i64 %4209}210 211; Make sure the and constant doesn't get converted to an opaque constant by212; ConstantHoisting. If it's an opaque constant we'll end up with constant213; materialization sequences on RV64.214define i64 @test12(i64 %0) #0 {215; RV32-LABEL: test12:216; RV32: # %bb.0: # %entry217; RV32-NEXT: addi a0, a0, -3218; RV32-NEXT: seqz a0, a0219; RV32-NEXT: li a1, 0220; RV32-NEXT: ret221;222; RV64-LABEL: test12:223; RV64: # %bb.0: # %entry224; RV64-NEXT: addi a0, a0, -16225; RV64-NEXT: addiw a0, a0, 13226; RV64-NEXT: seqz a0, a0227; RV64-NEXT: ret228entry:229 %1 = add nuw nsw i64 %0, u0xfffffff0230 %2 = and i64 %1, u0xffffffff231 %3 = icmp eq i64 %2, u0xfffffff3232 %4 = zext i1 %3 to i64233 ret i64 %4234}235 236; Make sure the and constant doesn't get converted to an opaque constant by237; ConstantHoisting.238define i64 @test13(i64 %0) #0 {239; RV32-LABEL: test13:240; RV32: # %bb.0: # %entry241; RV32-NEXT: lui a1, 524288242; RV32-NEXT: addi a1, a1, 15243; RV32-NEXT: add a0, a0, a1244; RV32-NEXT: srli a0, a0, 31245; RV32-NEXT: seqz a0, a0246; RV32-NEXT: li a1, 0247; RV32-NEXT: ret248;249; RV64-LABEL: test13:250; RV64: # %bb.0: # %entry251; RV64-NEXT: lui a1, 524288252; RV64-NEXT: addi a1, a1, -15253; RV64-NEXT: sub a0, a0, a1254; RV64-NEXT: sraiw a0, a0, 31255; RV64-NEXT: seqz a0, a0256; RV64-NEXT: ret257entry:258 %1 = add nuw nsw i64 %0, u0x8000000f259 %2 = and i64 %1, u0x80000000260 %3 = icmp eq i64 %2, 0261 %4 = zext i1 %3 to i64262 ret i64 %4263}264