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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7define i32 @and_0xfff_shl_2(i32 %x) {8; RV32I-LABEL: and_0xfff_shl_2:9; RV32I: # %bb.0:10; RV32I-NEXT: slli a0, a0, 2011; RV32I-NEXT: srli a0, a0, 1812; RV32I-NEXT: ret13;14; RV64I-LABEL: and_0xfff_shl_2:15; RV64I: # %bb.0:16; RV64I-NEXT: slli a0, a0, 5217; RV64I-NEXT: srli a0, a0, 5018; RV64I-NEXT: ret19 %a = and i32 %x, 409520 %s = shl i32 %a, 221 ret i32 %s22}23 24define i32 @and_0x7ff_shl_2(i32 %x) {25; RV32I-LABEL: and_0x7ff_shl_2:26; RV32I: # %bb.0:27; RV32I-NEXT: andi a0, a0, 204728; RV32I-NEXT: slli a0, a0, 229; RV32I-NEXT: ret30;31; RV64I-LABEL: and_0x7ff_shl_2:32; RV64I: # %bb.0:33; RV64I-NEXT: andi a0, a0, 204734; RV64I-NEXT: slli a0, a0, 235; RV64I-NEXT: ret36 %a = and i32 %x, 204737 %s = shl i32 %a, 238 ret i32 %s39}40 41define i64 @and_0xffffffff_shl_2(i64 %x) {42; RV32I-LABEL: and_0xffffffff_shl_2:43; RV32I: # %bb.0:44; RV32I-NEXT: slli a2, a0, 245; RV32I-NEXT: srli a1, a0, 3046; RV32I-NEXT: mv a0, a247; RV32I-NEXT: ret48;49; RV64I-LABEL: and_0xffffffff_shl_2:50; RV64I: # %bb.0:51; RV64I-NEXT: slli a0, a0, 3252; RV64I-NEXT: srli a0, a0, 3053; RV64I-NEXT: ret54 %a = and i64 %x, 429496729555 %s = shl i64 %a, 256 ret i64 %s57}58 59define i32 @and_0xfff_shl_2_multi_use(i32 %x) {60; RV32I-LABEL: and_0xfff_shl_2_multi_use:61; RV32I: # %bb.0:62; RV32I-NEXT: slli a0, a0, 2063; RV32I-NEXT: srli a0, a0, 2064; RV32I-NEXT: slli a1, a0, 265; RV32I-NEXT: add a0, a0, a166; RV32I-NEXT: ret67;68; RV64I-LABEL: and_0xfff_shl_2_multi_use:69; RV64I: # %bb.0:70; RV64I-NEXT: slli a0, a0, 5271; RV64I-NEXT: srli a0, a0, 5272; RV64I-NEXT: slli a1, a0, 273; RV64I-NEXT: add a0, a0, a174; RV64I-NEXT: ret75 %a = and i32 %x, 409576 %s = shl i32 %a, 277 %r = add i32 %a, %s78 ret i32 %r79}80 81define i64 @and_0xfff_shl_33(i64 %x) {82; RV32I-LABEL: and_0xfff_shl_33:83; RV32I: # %bb.0:84; RV32I-NEXT: slli a0, a0, 2085; RV32I-NEXT: srli a1, a0, 1986; RV32I-NEXT: li a0, 087; RV32I-NEXT: ret88;89; RV64I-LABEL: and_0xfff_shl_33:90; RV64I: # %bb.0:91; RV64I-NEXT: slli a0, a0, 5292; RV64I-NEXT: srli a0, a0, 1993; RV64I-NEXT: ret94 %a = and i64 %x, 409595 %s = shl i64 %a, 3396 ret i64 %s97}98