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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7; Test for handling of AND with constant. If this constant exceeds simm12 and8; also is a non-empty sequence of ones starting at the least significant bit9; with the remainder zero, we can replace it with SLLI + SLRI10 11define i32 @and32_0x7ff(i32 %x) {12; RV32I-LABEL: and32_0x7ff:13; RV32I: # %bb.0:14; RV32I-NEXT: andi a0, a0, 204715; RV32I-NEXT: ret16;17; RV64I-LABEL: and32_0x7ff:18; RV64I: # %bb.0:19; RV64I-NEXT: andi a0, a0, 204720; RV64I-NEXT: ret21 %a = and i32 %x, 204722 ret i32 %a23}24 25define i32 @and32_0xfff(i32 %x) {26; RV32I-LABEL: and32_0xfff:27; RV32I: # %bb.0:28; RV32I-NEXT: slli a0, a0, 2029; RV32I-NEXT: srli a0, a0, 2030; RV32I-NEXT: ret31;32; RV64I-LABEL: and32_0xfff:33; RV64I: # %bb.0:34; RV64I-NEXT: slli a0, a0, 5235; RV64I-NEXT: srli a0, a0, 5236; RV64I-NEXT: ret37 %a = and i32 %x, 409538 ret i32 %a39}40 41define i64 @and64_0x7ff(i64 %x) {42; RV32I-LABEL: and64_0x7ff:43; RV32I: # %bb.0:44; RV32I-NEXT: andi a0, a0, 204745; RV32I-NEXT: li a1, 046; RV32I-NEXT: ret47;48; RV64I-LABEL: and64_0x7ff:49; RV64I: # %bb.0:50; RV64I-NEXT: andi a0, a0, 204751; RV64I-NEXT: ret52 %a = and i64 %x, 204753 ret i64 %a54}55 56define i64 @and64_0xfff(i64 %x) {57; RV32I-LABEL: and64_0xfff:58; RV32I: # %bb.0:59; RV32I-NEXT: slli a0, a0, 2060; RV32I-NEXT: srli a0, a0, 2061; RV32I-NEXT: li a1, 062; RV32I-NEXT: ret63;64; RV64I-LABEL: and64_0xfff:65; RV64I: # %bb.0:66; RV64I-NEXT: slli a0, a0, 5267; RV64I-NEXT: srli a0, a0, 5268; RV64I-NEXT: ret69 %a = and i64 %x, 409570 ret i64 %a71}72 73; Test for handling of AND with constant. If this constant exceeds simm32 and74; also is a non-empty sequence of ones starting at the most significant bit75; with the remainder zero, we can replace it with SRLI + SLLI.76 77define i32 @and32_0x7ffff000(i32 %x) {78; RV32I-LABEL: and32_0x7ffff000:79; RV32I: # %bb.0:80; RV32I-NEXT: lui a1, 52428781; RV32I-NEXT: and a0, a0, a182; RV32I-NEXT: ret83;84; RV64I-LABEL: and32_0x7ffff000:85; RV64I: # %bb.0:86; RV64I-NEXT: lui a1, 52428787; RV64I-NEXT: and a0, a0, a188; RV64I-NEXT: ret89 %a = and i32 %x, 214747955290 ret i32 %a91}92 93define i32 @and32_0xfffff000(i32 %x) {94; RV32I-LABEL: and32_0xfffff000:95; RV32I: # %bb.0:96; RV32I-NEXT: lui a1, 104857597; RV32I-NEXT: and a0, a0, a198; RV32I-NEXT: ret99;100; RV64I-LABEL: and32_0xfffff000:101; RV64I: # %bb.0:102; RV64I-NEXT: lui a1, 1048575103; RV64I-NEXT: and a0, a0, a1104; RV64I-NEXT: ret105 %a = and i32 %x, -4096106 ret i32 %a107}108 109define i32 @and32_0xfffffa00(i32 %x) {110; RV32I-LABEL: and32_0xfffffa00:111; RV32I: # %bb.0:112; RV32I-NEXT: andi a0, a0, -1536113; RV32I-NEXT: ret114;115; RV64I-LABEL: and32_0xfffffa00:116; RV64I: # %bb.0:117; RV64I-NEXT: andi a0, a0, -1536118; RV64I-NEXT: ret119 %a = and i32 %x, -1536120 ret i32 %a121}122 123define i64 @and64_0x7ffffffffffff000(i64 %x) {124; RV32I-LABEL: and64_0x7ffffffffffff000:125; RV32I: # %bb.0:126; RV32I-NEXT: lui a2, 1048575127; RV32I-NEXT: slli a1, a1, 1128; RV32I-NEXT: and a0, a0, a2129; RV32I-NEXT: srli a1, a1, 1130; RV32I-NEXT: ret131;132; RV64I-LABEL: and64_0x7ffffffffffff000:133; RV64I: # %bb.0:134; RV64I-NEXT: lui a1, 1048574135; RV64I-NEXT: srli a1, a1, 1136; RV64I-NEXT: and a0, a0, a1137; RV64I-NEXT: ret138 %a = and i64 %x, 9223372036854771712139 ret i64 %a140}141 142define i64 @and64_0xfffffffffffff000(i64 %x) {143; RV32I-LABEL: and64_0xfffffffffffff000:144; RV32I: # %bb.0:145; RV32I-NEXT: lui a2, 1048575146; RV32I-NEXT: and a0, a0, a2147; RV32I-NEXT: ret148;149; RV64I-LABEL: and64_0xfffffffffffff000:150; RV64I: # %bb.0:151; RV64I-NEXT: lui a1, 1048575152; RV64I-NEXT: and a0, a0, a1153; RV64I-NEXT: ret154 %a = and i64 %x, -4096155 ret i64 %a156}157 158define i64 @and64_0xfffffffffffffa00(i64 %x) {159; RV32I-LABEL: and64_0xfffffffffffffa00:160; RV32I: # %bb.0:161; RV32I-NEXT: andi a0, a0, -1536162; RV32I-NEXT: ret163;164; RV64I-LABEL: and64_0xfffffffffffffa00:165; RV64I: # %bb.0:166; RV64I-NEXT: andi a0, a0, -1536167; RV64I-NEXT: ret168 %a = and i64 %x, -1536169 ret i64 %a170}171 172define i64 @and64_0xffffffff00000000(i64 %x) {173; RV32I-LABEL: and64_0xffffffff00000000:174; RV32I: # %bb.0:175; RV32I-NEXT: li a0, 0176; RV32I-NEXT: ret177;178; RV64I-LABEL: and64_0xffffffff00000000:179; RV64I: # %bb.0:180; RV64I-NEXT: srli a0, a0, 32181; RV64I-NEXT: slli a0, a0, 32182; RV64I-NEXT: ret183 %a = and i64 %x, -4294967296184 ret i64 %a185}186 187define i64 @and64_0x7fffffff00000000(i64 %x) {188; RV32I-LABEL: and64_0x7fffffff00000000:189; RV32I: # %bb.0:190; RV32I-NEXT: slli a1, a1, 1191; RV32I-NEXT: srli a1, a1, 1192; RV32I-NEXT: li a0, 0193; RV32I-NEXT: ret194;195; RV64I-LABEL: and64_0x7fffffff00000000:196; RV64I: # %bb.0:197; RV64I-NEXT: lui a1, 524288198; RV64I-NEXT: addi a1, a1, -1199; RV64I-NEXT: slli a1, a1, 32200; RV64I-NEXT: and a0, a0, a1201; RV64I-NEXT: ret202 %a = and i64 %x, 9223372032559808512203 ret i64 %a204}205 206define i64 @and64_0xffffffff80000000(i64 %x) {207; RV32I-LABEL: and64_0xffffffff80000000:208; RV32I: # %bb.0:209; RV32I-NEXT: lui a2, 524288210; RV32I-NEXT: and a0, a0, a2211; RV32I-NEXT: ret212;213; RV64I-LABEL: and64_0xffffffff80000000:214; RV64I: # %bb.0:215; RV64I-NEXT: lui a1, 524288216; RV64I-NEXT: and a0, a0, a1217; RV64I-NEXT: ret218 %a = and i64 %x, -2147483648219 ret i64 %a220}221 222define i64 @and64_0x00000000fffffff8(i64 %x) {223; RV32I-LABEL: and64_0x00000000fffffff8:224; RV32I: # %bb.0:225; RV32I-NEXT: andi a0, a0, -8226; RV32I-NEXT: li a1, 0227; RV32I-NEXT: ret228;229; RV64I-LABEL: and64_0x00000000fffffff8:230; RV64I: # %bb.0:231; RV64I-NEXT: srliw a0, a0, 3232; RV64I-NEXT: slli a0, a0, 3233; RV64I-NEXT: ret234 %a = and i64 %x, 4294967288235 ret i64 %a236}237