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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV64IA %s4 5; This test ensures that the output of the 'lr.w' instruction is sign-extended.6; Previously, the default zero-extension was being used and 'cmp' parameter7; higher bits were masked to zero for the comparison.8 9define i1 @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 signext %cmp,10; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:11; RV64IA: # %bb.0: # %entry12; RV64IA-NEXT: .LBB0_1: # %entry13; RV64IA-NEXT: # =>This Inner Loop Header: Depth=114; RV64IA-NEXT: lr.w.aqrl a3, (a0)15; RV64IA-NEXT: bne a3, a1, .LBB0_316; RV64IA-NEXT: # %bb.2: # %entry17; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=118; RV64IA-NEXT: sc.w.rl a4, a2, (a0)19; RV64IA-NEXT: bnez a4, .LBB0_120; RV64IA-NEXT: .LBB0_3: # %entry21; RV64IA-NEXT: xor a1, a3, a122; RV64IA-NEXT: seqz a0, a123; RV64IA-NEXT: ret24 i32 signext %val) nounwind {25entry:26 %0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst27 %1 = extractvalue { i32, i1 } %0, 128 ret i1 %129}30