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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s4 5;6; fixed avg(x,y) = sub(or(x,y),ashr(xor(x,y),1))7;8; ext avg(x,y) = trunc(ashr(add(sext(x),sext(y),1),1))9;10 11define i8 @test_fixed_i8(i8 %a0, i8 %a1) nounwind {12; RV32I-LABEL: test_fixed_i8:13; RV32I: # %bb.0:14; RV32I-NEXT: slli a1, a1, 2415; RV32I-NEXT: slli a0, a0, 2416; RV32I-NEXT: srai a1, a1, 2417; RV32I-NEXT: srai a0, a0, 2418; RV32I-NEXT: add a0, a0, a119; RV32I-NEXT: addi a0, a0, 120; RV32I-NEXT: srai a0, a0, 121; RV32I-NEXT: ret22;23; RV64I-LABEL: test_fixed_i8:24; RV64I: # %bb.0:25; RV64I-NEXT: slli a1, a1, 5626; RV64I-NEXT: slli a0, a0, 5627; RV64I-NEXT: srai a1, a1, 5628; RV64I-NEXT: srai a0, a0, 5629; RV64I-NEXT: add a0, a0, a130; RV64I-NEXT: addi a0, a0, 131; RV64I-NEXT: srai a0, a0, 132; RV64I-NEXT: ret33 %or = or i8 %a0, %a134 %xor = xor i8 %a0, %a135 %shift = ashr i8 %xor, 136 %res = sub i8 %or, %shift37 ret i8 %res38}39 40define i8 @test_ext_i8(i8 %a0, i8 %a1) nounwind {41; RV32I-LABEL: test_ext_i8:42; RV32I: # %bb.0:43; RV32I-NEXT: slli a1, a1, 2444; RV32I-NEXT: slli a0, a0, 2445; RV32I-NEXT: srai a1, a1, 2446; RV32I-NEXT: srai a0, a0, 2447; RV32I-NEXT: add a0, a0, a148; RV32I-NEXT: addi a0, a0, 149; RV32I-NEXT: srai a0, a0, 150; RV32I-NEXT: ret51;52; RV64I-LABEL: test_ext_i8:53; RV64I: # %bb.0:54; RV64I-NEXT: slli a1, a1, 5655; RV64I-NEXT: slli a0, a0, 5656; RV64I-NEXT: srai a1, a1, 5657; RV64I-NEXT: srai a0, a0, 5658; RV64I-NEXT: add a0, a0, a159; RV64I-NEXT: addi a0, a0, 160; RV64I-NEXT: srai a0, a0, 161; RV64I-NEXT: ret62 %x0 = sext i8 %a0 to i1663 %x1 = sext i8 %a1 to i1664 %sum = add i16 %x0, %x165 %sum1 = add i16 %sum, 166 %shift = ashr i16 %sum1, 167 %res = trunc i16 %shift to i868 ret i8 %res69}70 71define i16 @test_fixed_i16(i16 %a0, i16 %a1) nounwind {72; RV32I-LABEL: test_fixed_i16:73; RV32I: # %bb.0:74; RV32I-NEXT: slli a1, a1, 1675; RV32I-NEXT: slli a0, a0, 1676; RV32I-NEXT: srai a1, a1, 1677; RV32I-NEXT: srai a0, a0, 1678; RV32I-NEXT: add a0, a0, a179; RV32I-NEXT: addi a0, a0, 180; RV32I-NEXT: srai a0, a0, 181; RV32I-NEXT: ret82;83; RV64I-LABEL: test_fixed_i16:84; RV64I: # %bb.0:85; RV64I-NEXT: slli a1, a1, 4886; RV64I-NEXT: slli a0, a0, 4887; RV64I-NEXT: srai a1, a1, 4888; RV64I-NEXT: srai a0, a0, 4889; RV64I-NEXT: add a0, a0, a190; RV64I-NEXT: addi a0, a0, 191; RV64I-NEXT: srai a0, a0, 192; RV64I-NEXT: ret93 %or = or i16 %a0, %a194 %xor = xor i16 %a0, %a195 %shift = ashr i16 %xor, 196 %res = sub i16 %or, %shift97 ret i16 %res98}99 100define i16 @test_ext_i16(i16 %a0, i16 %a1) nounwind {101; RV32I-LABEL: test_ext_i16:102; RV32I: # %bb.0:103; RV32I-NEXT: slli a1, a1, 16104; RV32I-NEXT: slli a0, a0, 16105; RV32I-NEXT: srai a1, a1, 16106; RV32I-NEXT: srai a0, a0, 16107; RV32I-NEXT: add a0, a0, a1108; RV32I-NEXT: addi a0, a0, 1109; RV32I-NEXT: srai a0, a0, 1110; RV32I-NEXT: ret111;112; RV64I-LABEL: test_ext_i16:113; RV64I: # %bb.0:114; RV64I-NEXT: slli a1, a1, 48115; RV64I-NEXT: slli a0, a0, 48116; RV64I-NEXT: srai a1, a1, 48117; RV64I-NEXT: srai a0, a0, 48118; RV64I-NEXT: add a0, a0, a1119; RV64I-NEXT: addi a0, a0, 1120; RV64I-NEXT: srai a0, a0, 1121; RV64I-NEXT: ret122 %x0 = sext i16 %a0 to i32123 %x1 = sext i16 %a1 to i32124 %sum = add i32 %x0, %x1125 %sum1 = add i32 %sum, 1126 %shift = ashr i32 %sum1, 1127 %res = trunc i32 %shift to i16128 ret i16 %res129}130 131define i32 @test_fixed_i32(i32 %a0, i32 %a1) nounwind {132; RV32I-LABEL: test_fixed_i32:133; RV32I: # %bb.0:134; RV32I-NEXT: or a2, a0, a1135; RV32I-NEXT: xor a0, a0, a1136; RV32I-NEXT: srai a0, a0, 1137; RV32I-NEXT: sub a0, a2, a0138; RV32I-NEXT: ret139;140; RV64I-LABEL: test_fixed_i32:141; RV64I: # %bb.0:142; RV64I-NEXT: sext.w a1, a1143; RV64I-NEXT: sext.w a0, a0144; RV64I-NEXT: add a0, a0, a1145; RV64I-NEXT: addi a0, a0, 1146; RV64I-NEXT: srai a0, a0, 1147; RV64I-NEXT: ret148 %or = or i32 %a0, %a1149 %xor = xor i32 %a1, %a0150 %shift = ashr i32 %xor, 1151 %res = sub i32 %or, %shift152 ret i32 %res153}154 155define i32 @test_ext_i32(i32 %a0, i32 %a1) nounwind {156; RV32I-LABEL: test_ext_i32:157; RV32I: # %bb.0:158; RV32I-NEXT: or a2, a0, a1159; RV32I-NEXT: xor a0, a0, a1160; RV32I-NEXT: srai a0, a0, 1161; RV32I-NEXT: sub a0, a2, a0162; RV32I-NEXT: ret163;164; RV64I-LABEL: test_ext_i32:165; RV64I: # %bb.0:166; RV64I-NEXT: sext.w a1, a1167; RV64I-NEXT: sext.w a0, a0168; RV64I-NEXT: add a0, a0, a1169; RV64I-NEXT: addi a0, a0, 1170; RV64I-NEXT: srai a0, a0, 1171; RV64I-NEXT: ret172 %x0 = sext i32 %a0 to i64173 %x1 = sext i32 %a1 to i64174 %sum = add i64 %x0, %x1175 %sum1 = add i64 %sum, 1176 %shift = ashr i64 %sum1, 1177 %res = trunc i64 %shift to i32178 ret i32 %res179}180 181define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {182; RV32I-LABEL: test_fixed_i64:183; RV32I: # %bb.0:184; RV32I-NEXT: or a4, a1, a3185; RV32I-NEXT: xor a1, a1, a3186; RV32I-NEXT: xor a3, a0, a2187; RV32I-NEXT: or a0, a0, a2188; RV32I-NEXT: srai a2, a1, 1189; RV32I-NEXT: slli a1, a1, 31190; RV32I-NEXT: srli a3, a3, 1191; RV32I-NEXT: sub a4, a4, a2192; RV32I-NEXT: or a3, a3, a1193; RV32I-NEXT: sltu a1, a0, a3194; RV32I-NEXT: sub a1, a4, a1195; RV32I-NEXT: sub a0, a0, a3196; RV32I-NEXT: ret197;198; RV64I-LABEL: test_fixed_i64:199; RV64I: # %bb.0:200; RV64I-NEXT: or a2, a0, a1201; RV64I-NEXT: xor a0, a0, a1202; RV64I-NEXT: srai a0, a0, 1203; RV64I-NEXT: sub a0, a2, a0204; RV64I-NEXT: ret205 %or = or i64 %a0, %a1206 %xor = xor i64 %a1, %a0207 %shift = ashr i64 %xor, 1208 %res = sub i64 %or, %shift209 ret i64 %res210}211 212define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {213; RV32I-LABEL: test_ext_i64:214; RV32I: # %bb.0:215; RV32I-NEXT: or a4, a1, a3216; RV32I-NEXT: xor a1, a1, a3217; RV32I-NEXT: xor a3, a0, a2218; RV32I-NEXT: or a0, a0, a2219; RV32I-NEXT: srai a2, a1, 1220; RV32I-NEXT: slli a1, a1, 31221; RV32I-NEXT: srli a3, a3, 1222; RV32I-NEXT: sub a4, a4, a2223; RV32I-NEXT: or a3, a3, a1224; RV32I-NEXT: sltu a1, a0, a3225; RV32I-NEXT: sub a1, a4, a1226; RV32I-NEXT: sub a0, a0, a3227; RV32I-NEXT: ret228;229; RV64I-LABEL: test_ext_i64:230; RV64I: # %bb.0:231; RV64I-NEXT: or a2, a0, a1232; RV64I-NEXT: xor a0, a0, a1233; RV64I-NEXT: srai a0, a0, 1234; RV64I-NEXT: sub a0, a2, a0235; RV64I-NEXT: ret236 %x0 = sext i64 %a0 to i128237 %x1 = sext i64 %a1 to i128238 %sum = add i128 %x0, %x1239 %sum1 = add i128 %sum, 1240 %shift = ashr i128 %sum1, 1241 %res = trunc i128 %shift to i64242 ret i64 %res243}244