240 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s4 5;6; fixed avg(x,y) = sub(or(x,y),lshr(xor(x,y),1))7;8; ext avg(x,y) = trunc(lshr(add(zext(x),zext(y),1),1))9;10 11define i8 @test_fixed_i8(i8 %a0, i8 %a1) nounwind {12; RV32I-LABEL: test_fixed_i8:13; RV32I: # %bb.0:14; RV32I-NEXT: zext.b a1, a115; RV32I-NEXT: zext.b a0, a016; RV32I-NEXT: add a0, a0, a117; RV32I-NEXT: addi a0, a0, 118; RV32I-NEXT: srli a0, a0, 119; RV32I-NEXT: ret20;21; RV64I-LABEL: test_fixed_i8:22; RV64I: # %bb.0:23; RV64I-NEXT: zext.b a1, a124; RV64I-NEXT: zext.b a0, a025; RV64I-NEXT: add a0, a0, a126; RV64I-NEXT: addi a0, a0, 127; RV64I-NEXT: srli a0, a0, 128; RV64I-NEXT: ret29 %or = or i8 %a0, %a130 %xor = xor i8 %a0, %a131 %shift = lshr i8 %xor, 132 %res = sub i8 %or, %shift33 ret i8 %res34}35 36define i8 @test_ext_i8(i8 %a0, i8 %a1) nounwind {37; RV32I-LABEL: test_ext_i8:38; RV32I: # %bb.0:39; RV32I-NEXT: zext.b a1, a140; RV32I-NEXT: zext.b a0, a041; RV32I-NEXT: add a0, a0, a142; RV32I-NEXT: addi a0, a0, 143; RV32I-NEXT: srli a0, a0, 144; RV32I-NEXT: ret45;46; RV64I-LABEL: test_ext_i8:47; RV64I: # %bb.0:48; RV64I-NEXT: zext.b a1, a149; RV64I-NEXT: zext.b a0, a050; RV64I-NEXT: add a0, a0, a151; RV64I-NEXT: addi a0, a0, 152; RV64I-NEXT: srli a0, a0, 153; RV64I-NEXT: ret54 %x0 = zext i8 %a0 to i1655 %x1 = zext i8 %a1 to i1656 %sum = add i16 %x0, %x157 %sum1 = add i16 %sum, 158 %shift = lshr i16 %sum1, 159 %res = trunc i16 %shift to i860 ret i8 %res61}62 63define i16 @test_fixed_i16(i16 %a0, i16 %a1) nounwind {64; RV32I-LABEL: test_fixed_i16:65; RV32I: # %bb.0:66; RV32I-NEXT: lui a2, 1667; RV32I-NEXT: addi a2, a2, -168; RV32I-NEXT: and a1, a1, a269; RV32I-NEXT: and a0, a0, a270; RV32I-NEXT: add a0, a0, a171; RV32I-NEXT: addi a0, a0, 172; RV32I-NEXT: srli a0, a0, 173; RV32I-NEXT: ret74;75; RV64I-LABEL: test_fixed_i16:76; RV64I: # %bb.0:77; RV64I-NEXT: lui a2, 1678; RV64I-NEXT: addi a2, a2, -179; RV64I-NEXT: and a1, a1, a280; RV64I-NEXT: and a0, a0, a281; RV64I-NEXT: add a0, a0, a182; RV64I-NEXT: addi a0, a0, 183; RV64I-NEXT: srli a0, a0, 184; RV64I-NEXT: ret85 %or = or i16 %a0, %a186 %xor = xor i16 %a0, %a187 %shift = lshr i16 %xor, 188 %res = sub i16 %or, %shift89 ret i16 %res90}91 92define i16 @test_ext_i16(i16 %a0, i16 %a1) nounwind {93; RV32I-LABEL: test_ext_i16:94; RV32I: # %bb.0:95; RV32I-NEXT: lui a2, 1696; RV32I-NEXT: addi a2, a2, -197; RV32I-NEXT: and a1, a1, a298; RV32I-NEXT: and a0, a0, a299; RV32I-NEXT: add a0, a0, a1100; RV32I-NEXT: addi a0, a0, 1101; RV32I-NEXT: srli a0, a0, 1102; RV32I-NEXT: ret103;104; RV64I-LABEL: test_ext_i16:105; RV64I: # %bb.0:106; RV64I-NEXT: lui a2, 16107; RV64I-NEXT: addi a2, a2, -1108; RV64I-NEXT: and a1, a1, a2109; RV64I-NEXT: and a0, a0, a2110; RV64I-NEXT: add a0, a0, a1111; RV64I-NEXT: addi a0, a0, 1112; RV64I-NEXT: srli a0, a0, 1113; RV64I-NEXT: ret114 %x0 = zext i16 %a0 to i32115 %x1 = zext i16 %a1 to i32116 %sum = add i32 %x0, %x1117 %sum1 = add i32 %sum, 1118 %shift = lshr i32 %sum1, 1119 %res = trunc i32 %shift to i16120 ret i16 %res121}122 123define i32 @test_fixed_i32(i32 %a0, i32 %a1) nounwind {124; RV32I-LABEL: test_fixed_i32:125; RV32I: # %bb.0:126; RV32I-NEXT: or a2, a0, a1127; RV32I-NEXT: xor a0, a0, a1128; RV32I-NEXT: srli a0, a0, 1129; RV32I-NEXT: sub a0, a2, a0130; RV32I-NEXT: ret131;132; RV64I-LABEL: test_fixed_i32:133; RV64I: # %bb.0:134; RV64I-NEXT: slli a1, a1, 32135; RV64I-NEXT: slli a0, a0, 32136; RV64I-NEXT: srli a1, a1, 32137; RV64I-NEXT: srli a0, a0, 32138; RV64I-NEXT: add a0, a0, a1139; RV64I-NEXT: addi a0, a0, 1140; RV64I-NEXT: srli a0, a0, 1141; RV64I-NEXT: ret142 %or = or i32 %a0, %a1143 %xor = xor i32 %a1, %a0144 %shift = lshr i32 %xor, 1145 %res = sub i32 %or, %shift146 ret i32 %res147}148 149define i32 @test_ext_i32(i32 %a0, i32 %a1) nounwind {150; RV32I-LABEL: test_ext_i32:151; RV32I: # %bb.0:152; RV32I-NEXT: or a2, a0, a1153; RV32I-NEXT: xor a0, a0, a1154; RV32I-NEXT: srli a0, a0, 1155; RV32I-NEXT: sub a0, a2, a0156; RV32I-NEXT: ret157;158; RV64I-LABEL: test_ext_i32:159; RV64I: # %bb.0:160; RV64I-NEXT: slli a1, a1, 32161; RV64I-NEXT: slli a0, a0, 32162; RV64I-NEXT: srli a1, a1, 32163; RV64I-NEXT: srli a0, a0, 32164; RV64I-NEXT: add a0, a0, a1165; RV64I-NEXT: addi a0, a0, 1166; RV64I-NEXT: srli a0, a0, 1167; RV64I-NEXT: ret168 %x0 = zext i32 %a0 to i64169 %x1 = zext i32 %a1 to i64170 %sum = add i64 %x0, %x1171 %sum1 = add i64 %sum, 1172 %shift = lshr i64 %sum1, 1173 %res = trunc i64 %shift to i32174 ret i32 %res175}176 177define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {178; RV32I-LABEL: test_fixed_i64:179; RV32I: # %bb.0:180; RV32I-NEXT: or a4, a1, a3181; RV32I-NEXT: xor a1, a1, a3182; RV32I-NEXT: xor a3, a0, a2183; RV32I-NEXT: or a0, a0, a2184; RV32I-NEXT: srli a2, a1, 1185; RV32I-NEXT: slli a1, a1, 31186; RV32I-NEXT: srli a3, a3, 1187; RV32I-NEXT: sub a4, a4, a2188; RV32I-NEXT: or a3, a3, a1189; RV32I-NEXT: sltu a1, a0, a3190; RV32I-NEXT: sub a1, a4, a1191; RV32I-NEXT: sub a0, a0, a3192; RV32I-NEXT: ret193;194; RV64I-LABEL: test_fixed_i64:195; RV64I: # %bb.0:196; RV64I-NEXT: or a2, a0, a1197; RV64I-NEXT: xor a0, a0, a1198; RV64I-NEXT: srli a0, a0, 1199; RV64I-NEXT: sub a0, a2, a0200; RV64I-NEXT: ret201 %or = or i64 %a0, %a1202 %xor = xor i64 %a1, %a0203 %shift = lshr i64 %xor, 1204 %res = sub i64 %or, %shift205 ret i64 %res206}207 208define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {209; RV32I-LABEL: test_ext_i64:210; RV32I: # %bb.0:211; RV32I-NEXT: or a4, a1, a3212; RV32I-NEXT: xor a1, a1, a3213; RV32I-NEXT: xor a3, a0, a2214; RV32I-NEXT: or a0, a0, a2215; RV32I-NEXT: srli a2, a1, 1216; RV32I-NEXT: slli a1, a1, 31217; RV32I-NEXT: srli a3, a3, 1218; RV32I-NEXT: sub a4, a4, a2219; RV32I-NEXT: or a3, a3, a1220; RV32I-NEXT: sltu a1, a0, a3221; RV32I-NEXT: sub a1, a4, a1222; RV32I-NEXT: sub a0, a0, a3223; RV32I-NEXT: ret224;225; RV64I-LABEL: test_ext_i64:226; RV64I: # %bb.0:227; RV64I-NEXT: or a2, a0, a1228; RV64I-NEXT: xor a0, a0, a1229; RV64I-NEXT: srli a0, a0, 1230; RV64I-NEXT: sub a0, a2, a0231; RV64I-NEXT: ret232 %x0 = zext i64 %a0 to i128233 %x1 = zext i64 %a1 to i128234 %sum = add i128 %x0, %x1235 %sum1 = add i128 %sum, 1236 %shift = lshr i128 %sum1, 1237 %res = trunc i128 %shift to i64238 ret i64 %res239}240