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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s4 5;6; fixed avg(x,y) = add(and(x,y),ashr(xor(x,y),1))7;8; ext avg(x,y) = trunc(ashr(add(sext(x),sext(y)),1))9;10 11define i8 @test_fixed_i8(i8 %a0, i8 %a1) nounwind {12; RV32I-LABEL: test_fixed_i8:13; RV32I: # %bb.0:14; RV32I-NEXT: slli a1, a1, 2415; RV32I-NEXT: slli a0, a0, 2416; RV32I-NEXT: srai a1, a1, 2417; RV32I-NEXT: srai a0, a0, 2418; RV32I-NEXT: add a0, a0, a119; RV32I-NEXT: srai a0, a0, 120; RV32I-NEXT: ret21;22; RV64I-LABEL: test_fixed_i8:23; RV64I: # %bb.0:24; RV64I-NEXT: slli a1, a1, 5625; RV64I-NEXT: slli a0, a0, 5626; RV64I-NEXT: srai a1, a1, 5627; RV64I-NEXT: srai a0, a0, 5628; RV64I-NEXT: add a0, a0, a129; RV64I-NEXT: srai a0, a0, 130; RV64I-NEXT: ret31 %and = and i8 %a0, %a132 %xor = xor i8 %a0, %a133 %shift = ashr i8 %xor, 134 %res = add i8 %and, %shift35 ret i8 %res36}37 38define i8 @test_ext_i8(i8 %a0, i8 %a1) nounwind {39; RV32I-LABEL: test_ext_i8:40; RV32I: # %bb.0:41; RV32I-NEXT: slli a1, a1, 2442; RV32I-NEXT: slli a0, a0, 2443; RV32I-NEXT: srai a1, a1, 2444; RV32I-NEXT: srai a0, a0, 2445; RV32I-NEXT: add a0, a0, a146; RV32I-NEXT: srai a0, a0, 147; RV32I-NEXT: ret48;49; RV64I-LABEL: test_ext_i8:50; RV64I: # %bb.0:51; RV64I-NEXT: slli a1, a1, 5652; RV64I-NEXT: slli a0, a0, 5653; RV64I-NEXT: srai a1, a1, 5654; RV64I-NEXT: srai a0, a0, 5655; RV64I-NEXT: add a0, a0, a156; RV64I-NEXT: srai a0, a0, 157; RV64I-NEXT: ret58 %x0 = sext i8 %a0 to i1659 %x1 = sext i8 %a1 to i1660 %sum = add i16 %x0, %x161 %shift = ashr i16 %sum, 162 %res = trunc i16 %shift to i863 ret i8 %res64}65 66define i16 @test_fixed_i16(i16 %a0, i16 %a1) nounwind {67; RV32I-LABEL: test_fixed_i16:68; RV32I: # %bb.0:69; RV32I-NEXT: slli a1, a1, 1670; RV32I-NEXT: slli a0, a0, 1671; RV32I-NEXT: srai a1, a1, 1672; RV32I-NEXT: srai a0, a0, 1673; RV32I-NEXT: add a0, a0, a174; RV32I-NEXT: srai a0, a0, 175; RV32I-NEXT: ret76;77; RV64I-LABEL: test_fixed_i16:78; RV64I: # %bb.0:79; RV64I-NEXT: slli a1, a1, 4880; RV64I-NEXT: slli a0, a0, 4881; RV64I-NEXT: srai a1, a1, 4882; RV64I-NEXT: srai a0, a0, 4883; RV64I-NEXT: add a0, a0, a184; RV64I-NEXT: srai a0, a0, 185; RV64I-NEXT: ret86 %and = and i16 %a0, %a187 %xor = xor i16 %a0, %a188 %shift = ashr i16 %xor, 189 %res = add i16 %and, %shift90 ret i16 %res91}92 93define i16 @test_ext_i16(i16 %a0, i16 %a1) nounwind {94; RV32I-LABEL: test_ext_i16:95; RV32I: # %bb.0:96; RV32I-NEXT: slli a1, a1, 1697; RV32I-NEXT: slli a0, a0, 1698; RV32I-NEXT: srai a1, a1, 1699; RV32I-NEXT: srai a0, a0, 16100; RV32I-NEXT: add a0, a0, a1101; RV32I-NEXT: srai a0, a0, 1102; RV32I-NEXT: ret103;104; RV64I-LABEL: test_ext_i16:105; RV64I: # %bb.0:106; RV64I-NEXT: slli a1, a1, 48107; RV64I-NEXT: slli a0, a0, 48108; RV64I-NEXT: srai a1, a1, 48109; RV64I-NEXT: srai a0, a0, 48110; RV64I-NEXT: add a0, a0, a1111; RV64I-NEXT: srai a0, a0, 1112; RV64I-NEXT: ret113 %x0 = sext i16 %a0 to i32114 %x1 = sext i16 %a1 to i32115 %sum = add i32 %x0, %x1116 %shift = ashr i32 %sum, 1117 %res = trunc i32 %shift to i16118 ret i16 %res119}120 121define i32 @test_fixed_i32(i32 %a0, i32 %a1) nounwind {122; RV32I-LABEL: test_fixed_i32:123; RV32I: # %bb.0:124; RV32I-NEXT: and a2, a0, a1125; RV32I-NEXT: xor a0, a0, a1126; RV32I-NEXT: srai a0, a0, 1127; RV32I-NEXT: add a0, a2, a0128; RV32I-NEXT: ret129;130; RV64I-LABEL: test_fixed_i32:131; RV64I: # %bb.0:132; RV64I-NEXT: sext.w a1, a1133; RV64I-NEXT: sext.w a0, a0134; RV64I-NEXT: add a0, a0, a1135; RV64I-NEXT: srai a0, a0, 1136; RV64I-NEXT: ret137 %and = and i32 %a0, %a1138 %xor = xor i32 %a1, %a0139 %shift = ashr i32 %xor, 1140 %res = add i32 %and, %shift141 ret i32 %res142}143 144define i32 @test_ext_i32(i32 %a0, i32 %a1) nounwind {145; RV32I-LABEL: test_ext_i32:146; RV32I: # %bb.0:147; RV32I-NEXT: and a2, a0, a1148; RV32I-NEXT: xor a0, a0, a1149; RV32I-NEXT: srai a0, a0, 1150; RV32I-NEXT: add a0, a2, a0151; RV32I-NEXT: ret152;153; RV64I-LABEL: test_ext_i32:154; RV64I: # %bb.0:155; RV64I-NEXT: sext.w a1, a1156; RV64I-NEXT: sext.w a0, a0157; RV64I-NEXT: add a0, a0, a1158; RV64I-NEXT: srai a0, a0, 1159; RV64I-NEXT: ret160 %x0 = sext i32 %a0 to i64161 %x1 = sext i32 %a1 to i64162 %sum = add i64 %x0, %x1163 %shift = ashr i64 %sum, 1164 %res = trunc i64 %shift to i32165 ret i32 %res166}167 168define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {169; RV32I-LABEL: test_fixed_i64:170; RV32I: # %bb.0:171; RV32I-NEXT: and a4, a1, a3172; RV32I-NEXT: xor a1, a1, a3173; RV32I-NEXT: srai a3, a1, 1174; RV32I-NEXT: add a3, a4, a3175; RV32I-NEXT: xor a4, a0, a2176; RV32I-NEXT: slli a1, a1, 31177; RV32I-NEXT: srli a4, a4, 1178; RV32I-NEXT: or a1, a4, a1179; RV32I-NEXT: and a2, a0, a2180; RV32I-NEXT: add a0, a2, a1181; RV32I-NEXT: sltu a1, a0, a2182; RV32I-NEXT: add a1, a3, a1183; RV32I-NEXT: ret184;185; RV64I-LABEL: test_fixed_i64:186; RV64I: # %bb.0:187; RV64I-NEXT: and a2, a0, a1188; RV64I-NEXT: xor a0, a0, a1189; RV64I-NEXT: srai a0, a0, 1190; RV64I-NEXT: add a0, a2, a0191; RV64I-NEXT: ret192 %and = and i64 %a0, %a1193 %xor = xor i64 %a1, %a0194 %shift = ashr i64 %xor, 1195 %res = add i64 %and, %shift196 ret i64 %res197}198 199define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {200; RV32I-LABEL: test_ext_i64:201; RV32I: # %bb.0:202; RV32I-NEXT: and a4, a1, a3203; RV32I-NEXT: xor a1, a1, a3204; RV32I-NEXT: srai a3, a1, 1205; RV32I-NEXT: add a3, a4, a3206; RV32I-NEXT: xor a4, a0, a2207; RV32I-NEXT: slli a1, a1, 31208; RV32I-NEXT: srli a4, a4, 1209; RV32I-NEXT: or a1, a4, a1210; RV32I-NEXT: and a2, a0, a2211; RV32I-NEXT: add a0, a2, a1212; RV32I-NEXT: sltu a1, a0, a2213; RV32I-NEXT: add a1, a3, a1214; RV32I-NEXT: ret215;216; RV64I-LABEL: test_ext_i64:217; RV64I: # %bb.0:218; RV64I-NEXT: and a2, a0, a1219; RV64I-NEXT: xor a0, a0, a1220; RV64I-NEXT: srai a0, a0, 1221; RV64I-NEXT: add a0, a2, a0222; RV64I-NEXT: ret223 %x0 = sext i64 %a0 to i128224 %x1 = sext i64 %a1 to i128225 %sum = add i128 %x0, %x1226 %shift = ashr i128 %sum, 1227 %res = trunc i128 %shift to i64228 ret i64 %res229}230