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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s4 5;6; fixed avg(x,y) = add(and(x,y),lshr(xor(x,y),1))7;8; ext avg(x,y) = trunc(lshr(add(zext(x),zext(y)),1))9;10 11define i8 @test_fixed_i8(i8 %a0, i8 %a1) nounwind {12; RV32I-LABEL: test_fixed_i8:13; RV32I: # %bb.0:14; RV32I-NEXT: zext.b a1, a115; RV32I-NEXT: zext.b a0, a016; RV32I-NEXT: add a0, a0, a117; RV32I-NEXT: srli a0, a0, 118; RV32I-NEXT: ret19;20; RV64I-LABEL: test_fixed_i8:21; RV64I: # %bb.0:22; RV64I-NEXT: zext.b a1, a123; RV64I-NEXT: zext.b a0, a024; RV64I-NEXT: add a0, a0, a125; RV64I-NEXT: srli a0, a0, 126; RV64I-NEXT: ret27 %and = and i8 %a0, %a128 %xor = xor i8 %a0, %a129 %shift = lshr i8 %xor, 130 %res = add i8 %and, %shift31 ret i8 %res32}33 34define i8 @test_ext_i8(i8 %a0, i8 %a1) nounwind {35; RV32I-LABEL: test_ext_i8:36; RV32I: # %bb.0:37; RV32I-NEXT: zext.b a1, a138; RV32I-NEXT: zext.b a0, a039; RV32I-NEXT: add a0, a0, a140; RV32I-NEXT: srli a0, a0, 141; RV32I-NEXT: ret42;43; RV64I-LABEL: test_ext_i8:44; RV64I: # %bb.0:45; RV64I-NEXT: zext.b a1, a146; RV64I-NEXT: zext.b a0, a047; RV64I-NEXT: add a0, a0, a148; RV64I-NEXT: srli a0, a0, 149; RV64I-NEXT: ret50 %x0 = zext i8 %a0 to i1651 %x1 = zext i8 %a1 to i1652 %sum = add i16 %x0, %x153 %shift = lshr i16 %sum, 154 %res = trunc i16 %shift to i855 ret i8 %res56}57 58define i16 @test_fixed_i16(i16 %a0, i16 %a1) nounwind {59; RV32I-LABEL: test_fixed_i16:60; RV32I: # %bb.0:61; RV32I-NEXT: lui a2, 1662; RV32I-NEXT: addi a2, a2, -163; RV32I-NEXT: and a1, a1, a264; RV32I-NEXT: and a0, a0, a265; RV32I-NEXT: add a0, a0, a166; RV32I-NEXT: srli a0, a0, 167; RV32I-NEXT: ret68;69; RV64I-LABEL: test_fixed_i16:70; RV64I: # %bb.0:71; RV64I-NEXT: lui a2, 1672; RV64I-NEXT: addi a2, a2, -173; RV64I-NEXT: and a1, a1, a274; RV64I-NEXT: and a0, a0, a275; RV64I-NEXT: add a0, a0, a176; RV64I-NEXT: srli a0, a0, 177; RV64I-NEXT: ret78 %and = and i16 %a0, %a179 %xor = xor i16 %a0, %a180 %shift = lshr i16 %xor, 181 %res = add i16 %and, %shift82 ret i16 %res83}84 85define i16 @test_ext_i16(i16 %a0, i16 %a1) nounwind {86; RV32I-LABEL: test_ext_i16:87; RV32I: # %bb.0:88; RV32I-NEXT: lui a2, 1689; RV32I-NEXT: addi a2, a2, -190; RV32I-NEXT: and a1, a1, a291; RV32I-NEXT: and a0, a0, a292; RV32I-NEXT: add a0, a0, a193; RV32I-NEXT: srli a0, a0, 194; RV32I-NEXT: ret95;96; RV64I-LABEL: test_ext_i16:97; RV64I: # %bb.0:98; RV64I-NEXT: lui a2, 1699; RV64I-NEXT: addi a2, a2, -1100; RV64I-NEXT: and a1, a1, a2101; RV64I-NEXT: and a0, a0, a2102; RV64I-NEXT: add a0, a0, a1103; RV64I-NEXT: srli a0, a0, 1104; RV64I-NEXT: ret105 %x0 = zext i16 %a0 to i32106 %x1 = zext i16 %a1 to i32107 %sum = add i32 %x0, %x1108 %shift = lshr i32 %sum, 1109 %res = trunc i32 %shift to i16110 ret i16 %res111}112 113define i32 @test_fixed_i32(i32 %a0, i32 %a1) nounwind {114; RV32I-LABEL: test_fixed_i32:115; RV32I: # %bb.0:116; RV32I-NEXT: and a2, a0, a1117; RV32I-NEXT: xor a0, a0, a1118; RV32I-NEXT: srli a0, a0, 1119; RV32I-NEXT: add a0, a2, a0120; RV32I-NEXT: ret121;122; RV64I-LABEL: test_fixed_i32:123; RV64I: # %bb.0:124; RV64I-NEXT: slli a1, a1, 32125; RV64I-NEXT: slli a0, a0, 32126; RV64I-NEXT: srli a1, a1, 32127; RV64I-NEXT: srli a0, a0, 32128; RV64I-NEXT: add a0, a0, a1129; RV64I-NEXT: srli a0, a0, 1130; RV64I-NEXT: ret131 %and = and i32 %a0, %a1132 %xor = xor i32 %a1, %a0133 %shift = lshr i32 %xor, 1134 %res = add i32 %and, %shift135 ret i32 %res136}137 138define i32 @test_ext_i32(i32 %a0, i32 %a1) nounwind {139; RV32I-LABEL: test_ext_i32:140; RV32I: # %bb.0:141; RV32I-NEXT: and a2, a0, a1142; RV32I-NEXT: xor a0, a0, a1143; RV32I-NEXT: srli a0, a0, 1144; RV32I-NEXT: add a0, a2, a0145; RV32I-NEXT: ret146;147; RV64I-LABEL: test_ext_i32:148; RV64I: # %bb.0:149; RV64I-NEXT: slli a1, a1, 32150; RV64I-NEXT: slli a0, a0, 32151; RV64I-NEXT: srli a1, a1, 32152; RV64I-NEXT: srli a0, a0, 32153; RV64I-NEXT: add a0, a0, a1154; RV64I-NEXT: srli a0, a0, 1155; RV64I-NEXT: ret156 %x0 = zext i32 %a0 to i64157 %x1 = zext i32 %a1 to i64158 %sum = add i64 %x0, %x1159 %shift = lshr i64 %sum, 1160 %res = trunc i64 %shift to i32161 ret i32 %res162}163 164define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {165; RV32I-LABEL: test_fixed_i64:166; RV32I: # %bb.0:167; RV32I-NEXT: add a1, a3, a1168; RV32I-NEXT: add a0, a2, a0169; RV32I-NEXT: sltu a2, a0, a2170; RV32I-NEXT: add a1, a1, a2171; RV32I-NEXT: beq a1, a3, .LBB6_2172; RV32I-NEXT: # %bb.1:173; RV32I-NEXT: sltu a2, a1, a3174; RV32I-NEXT: .LBB6_2:175; RV32I-NEXT: slli a2, a2, 31176; RV32I-NEXT: srli a3, a1, 1177; RV32I-NEXT: slli a4, a1, 31178; RV32I-NEXT: srli a0, a0, 1179; RV32I-NEXT: or a1, a3, a2180; RV32I-NEXT: or a0, a0, a4181; RV32I-NEXT: ret182;183; RV64I-LABEL: test_fixed_i64:184; RV64I: # %bb.0:185; RV64I-NEXT: and a2, a0, a1186; RV64I-NEXT: xor a0, a0, a1187; RV64I-NEXT: srli a0, a0, 1188; RV64I-NEXT: add a0, a2, a0189; RV64I-NEXT: ret190 %and = and i64 %a0, %a1191 %xor = xor i64 %a1, %a0192 %shift = lshr i64 %xor, 1193 %res = add i64 %and, %shift194 ret i64 %res195}196 197define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {198; RV32I-LABEL: test_ext_i64:199; RV32I: # %bb.0:200; RV32I-NEXT: add a1, a3, a1201; RV32I-NEXT: add a0, a2, a0202; RV32I-NEXT: sltu a2, a0, a2203; RV32I-NEXT: add a1, a1, a2204; RV32I-NEXT: beq a1, a3, .LBB7_2205; RV32I-NEXT: # %bb.1:206; RV32I-NEXT: sltu a2, a1, a3207; RV32I-NEXT: .LBB7_2:208; RV32I-NEXT: slli a2, a2, 31209; RV32I-NEXT: srli a3, a1, 1210; RV32I-NEXT: slli a4, a1, 31211; RV32I-NEXT: srli a0, a0, 1212; RV32I-NEXT: or a1, a3, a2213; RV32I-NEXT: or a0, a0, a4214; RV32I-NEXT: ret215;216; RV64I-LABEL: test_ext_i64:217; RV64I: # %bb.0:218; RV64I-NEXT: and a2, a0, a1219; RV64I-NEXT: xor a0, a0, a1220; RV64I-NEXT: srli a0, a0, 1221; RV64I-NEXT: add a0, a2, a0222; RV64I-NEXT: ret223 %x0 = zext i64 %a0 to i128224 %x1 = zext i64 %a1 to i128225 %sum = add i128 %x0, %x1226 %shift = lshr i128 %sum, 1227 %res = trunc i128 %shift to i64228 ret i64 %res229}230