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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \3; RUN: -target-abi ilp32f < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \5; RUN: -target-abi lp64f < %s | FileCheck %s6 7define i32 @fcmp_false(bfloat %a, bfloat %b) nounwind {8; CHECK-LABEL: fcmp_false:9; CHECK: # %bb.0:10; CHECK-NEXT: li a0, 011; CHECK-NEXT: ret12 %1 = fcmp false bfloat %a, %b13 %2 = zext i1 %1 to i3214 ret i32 %215}16 17define i32 @fcmp_oeq(bfloat %a, bfloat %b) nounwind {18; CHECK-LABEL: fcmp_oeq:19; CHECK: # %bb.0:20; CHECK-NEXT: fcvt.s.bf16 fa5, fa121; CHECK-NEXT: fcvt.s.bf16 fa4, fa022; CHECK-NEXT: feq.s a0, fa4, fa523; CHECK-NEXT: ret24 %1 = fcmp oeq bfloat %a, %b25 %2 = zext i1 %1 to i3226 ret i32 %227}28 29define i32 @fcmp_ogt(bfloat %a, bfloat %b) nounwind {30; CHECK-LABEL: fcmp_ogt:31; CHECK: # %bb.0:32; CHECK-NEXT: fcvt.s.bf16 fa5, fa033; CHECK-NEXT: fcvt.s.bf16 fa4, fa134; CHECK-NEXT: flt.s a0, fa4, fa535; CHECK-NEXT: ret36 %1 = fcmp ogt bfloat %a, %b37 %2 = zext i1 %1 to i3238 ret i32 %239}40 41define i32 @fcmp_oge(bfloat %a, bfloat %b) nounwind {42; CHECK-LABEL: fcmp_oge:43; CHECK: # %bb.0:44; CHECK-NEXT: fcvt.s.bf16 fa5, fa045; CHECK-NEXT: fcvt.s.bf16 fa4, fa146; CHECK-NEXT: fle.s a0, fa4, fa547; CHECK-NEXT: ret48 %1 = fcmp oge bfloat %a, %b49 %2 = zext i1 %1 to i3250 ret i32 %251}52 53define i32 @fcmp_olt(bfloat %a, bfloat %b) nounwind {54; CHECK-LABEL: fcmp_olt:55; CHECK: # %bb.0:56; CHECK-NEXT: fcvt.s.bf16 fa5, fa157; CHECK-NEXT: fcvt.s.bf16 fa4, fa058; CHECK-NEXT: flt.s a0, fa4, fa559; CHECK-NEXT: ret60 %1 = fcmp olt bfloat %a, %b61 %2 = zext i1 %1 to i3262 ret i32 %263}64 65define i32 @fcmp_ole(bfloat %a, bfloat %b) nounwind {66; CHECK-LABEL: fcmp_ole:67; CHECK: # %bb.0:68; CHECK-NEXT: fcvt.s.bf16 fa5, fa169; CHECK-NEXT: fcvt.s.bf16 fa4, fa070; CHECK-NEXT: fle.s a0, fa4, fa571; CHECK-NEXT: ret72 %1 = fcmp ole bfloat %a, %b73 %2 = zext i1 %1 to i3274 ret i32 %275}76 77define i32 @fcmp_one(bfloat %a, bfloat %b) nounwind {78; CHECK-LABEL: fcmp_one:79; CHECK: # %bb.0:80; CHECK-NEXT: fcvt.s.bf16 fa5, fa181; CHECK-NEXT: fcvt.s.bf16 fa4, fa082; CHECK-NEXT: flt.s a0, fa4, fa583; CHECK-NEXT: flt.s a1, fa5, fa484; CHECK-NEXT: or a0, a1, a085; CHECK-NEXT: ret86 %1 = fcmp one bfloat %a, %b87 %2 = zext i1 %1 to i3288 ret i32 %289}90 91define i32 @fcmp_ord(bfloat %a, bfloat %b) nounwind {92; CHECK-LABEL: fcmp_ord:93; CHECK: # %bb.0:94; CHECK-NEXT: fcvt.s.bf16 fa5, fa195; CHECK-NEXT: fcvt.s.bf16 fa4, fa096; CHECK-NEXT: feq.s a0, fa5, fa597; CHECK-NEXT: feq.s a1, fa4, fa498; CHECK-NEXT: and a0, a1, a099; CHECK-NEXT: ret100 %1 = fcmp ord bfloat %a, %b101 %2 = zext i1 %1 to i32102 ret i32 %2103}104 105define i32 @fcmp_ueq(bfloat %a, bfloat %b) nounwind {106; CHECK-LABEL: fcmp_ueq:107; CHECK: # %bb.0:108; CHECK-NEXT: fcvt.s.bf16 fa5, fa1109; CHECK-NEXT: fcvt.s.bf16 fa4, fa0110; CHECK-NEXT: flt.s a0, fa4, fa5111; CHECK-NEXT: flt.s a1, fa5, fa4112; CHECK-NEXT: or a0, a1, a0113; CHECK-NEXT: xori a0, a0, 1114; CHECK-NEXT: ret115 %1 = fcmp ueq bfloat %a, %b116 %2 = zext i1 %1 to i32117 ret i32 %2118}119 120define i32 @fcmp_ugt(bfloat %a, bfloat %b) nounwind {121; CHECK-LABEL: fcmp_ugt:122; CHECK: # %bb.0:123; CHECK-NEXT: fcvt.s.bf16 fa5, fa1124; CHECK-NEXT: fcvt.s.bf16 fa4, fa0125; CHECK-NEXT: fle.s a0, fa4, fa5126; CHECK-NEXT: xori a0, a0, 1127; CHECK-NEXT: ret128 %1 = fcmp ugt bfloat %a, %b129 %2 = zext i1 %1 to i32130 ret i32 %2131}132 133define i32 @fcmp_uge(bfloat %a, bfloat %b) nounwind {134; CHECK-LABEL: fcmp_uge:135; CHECK: # %bb.0:136; CHECK-NEXT: fcvt.s.bf16 fa5, fa1137; CHECK-NEXT: fcvt.s.bf16 fa4, fa0138; CHECK-NEXT: flt.s a0, fa4, fa5139; CHECK-NEXT: xori a0, a0, 1140; CHECK-NEXT: ret141 %1 = fcmp uge bfloat %a, %b142 %2 = zext i1 %1 to i32143 ret i32 %2144}145 146define i32 @fcmp_ult(bfloat %a, bfloat %b) nounwind {147; CHECK-LABEL: fcmp_ult:148; CHECK: # %bb.0:149; CHECK-NEXT: fcvt.s.bf16 fa5, fa0150; CHECK-NEXT: fcvt.s.bf16 fa4, fa1151; CHECK-NEXT: fle.s a0, fa4, fa5152; CHECK-NEXT: xori a0, a0, 1153; CHECK-NEXT: ret154 %1 = fcmp ult bfloat %a, %b155 %2 = zext i1 %1 to i32156 ret i32 %2157}158 159define i32 @fcmp_ule(bfloat %a, bfloat %b) nounwind {160; CHECK-LABEL: fcmp_ule:161; CHECK: # %bb.0:162; CHECK-NEXT: fcvt.s.bf16 fa5, fa0163; CHECK-NEXT: fcvt.s.bf16 fa4, fa1164; CHECK-NEXT: flt.s a0, fa4, fa5165; CHECK-NEXT: xori a0, a0, 1166; CHECK-NEXT: ret167 %1 = fcmp ule bfloat %a, %b168 %2 = zext i1 %1 to i32169 ret i32 %2170}171 172define i32 @fcmp_une(bfloat %a, bfloat %b) nounwind {173; CHECK-LABEL: fcmp_une:174; CHECK: # %bb.0:175; CHECK-NEXT: fcvt.s.bf16 fa5, fa1176; CHECK-NEXT: fcvt.s.bf16 fa4, fa0177; CHECK-NEXT: feq.s a0, fa4, fa5178; CHECK-NEXT: xori a0, a0, 1179; CHECK-NEXT: ret180 %1 = fcmp une bfloat %a, %b181 %2 = zext i1 %1 to i32182 ret i32 %2183}184 185define i32 @fcmp_uno(bfloat %a, bfloat %b) nounwind {186; CHECK-LABEL: fcmp_uno:187; CHECK: # %bb.0:188; CHECK-NEXT: fcvt.s.bf16 fa5, fa1189; CHECK-NEXT: fcvt.s.bf16 fa4, fa0190; CHECK-NEXT: feq.s a0, fa5, fa5191; CHECK-NEXT: feq.s a1, fa4, fa4192; CHECK-NEXT: and a0, a1, a0193; CHECK-NEXT: xori a0, a0, 1194; CHECK-NEXT: ret195 %1 = fcmp uno bfloat %a, %b196 %2 = zext i1 %1 to i32197 ret i32 %2198}199 200define i32 @fcmp_true(bfloat %a, bfloat %b) nounwind {201; CHECK-LABEL: fcmp_true:202; CHECK: # %bb.0:203; CHECK-NEXT: li a0, 1204; CHECK-NEXT: ret205 %1 = fcmp true bfloat %a, %b206 %2 = zext i1 %1 to i32207 ret i32 %2208}209