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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \3; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECK,RV32IZFBFMIN %s4; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \5; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECK,RV64IZFBFMIN %s6 7define bfloat @flh(ptr %a) nounwind {8; CHECK-LABEL: flh:9; CHECK: # %bb.0:10; CHECK-NEXT: flh fa5, 6(a0)11; CHECK-NEXT: flh fa4, 0(a0)12; CHECK-NEXT: fcvt.s.bf16 fa5, fa513; CHECK-NEXT: fcvt.s.bf16 fa4, fa414; CHECK-NEXT: fadd.s fa5, fa4, fa515; CHECK-NEXT: fcvt.bf16.s fa0, fa516; CHECK-NEXT: ret17 %1 = load bfloat, ptr %a18 %2 = getelementptr bfloat, ptr %a, i32 319 %3 = load bfloat, ptr %220; Use both loaded values in an FP op to ensure an flh is used, even for the21; soft bfloat ABI22 %4 = fadd bfloat %1, %323 ret bfloat %424}25 26define dso_local void @fsh(ptr %a, bfloat %b, bfloat %c) nounwind {27; CHECK-LABEL: fsh:28; CHECK: # %bb.0:29; CHECK-NEXT: fcvt.s.bf16 fa5, fa130; CHECK-NEXT: fcvt.s.bf16 fa4, fa031; CHECK-NEXT: fadd.s fa5, fa4, fa532; CHECK-NEXT: fcvt.bf16.s fa5, fa533; CHECK-NEXT: fsh fa5, 0(a0)34; CHECK-NEXT: fsh fa5, 16(a0)35; CHECK-NEXT: ret36 %1 = fadd bfloat %b, %c37 store bfloat %1, ptr %a38 %2 = getelementptr bfloat, ptr %a, i32 839 store bfloat %1, ptr %240 ret void41}42 43; Check load and store to a global44@G = dso_local global bfloat 0.045 46define bfloat @flh_fsh_global(bfloat %a, bfloat %b) nounwind {47; Use %a and %b in an FP op to ensure bfloat precision floating point registers48; are used, even for the soft bfloat ABI49; CHECK-LABEL: flh_fsh_global:50; CHECK: # %bb.0:51; CHECK-NEXT: fcvt.s.bf16 fa5, fa152; CHECK-NEXT: fcvt.s.bf16 fa4, fa053; CHECK-NEXT: lui a0, %hi(G)54; CHECK-NEXT: addi a0, a0, %lo(G)55; CHECK-NEXT: fadd.s fa5, fa4, fa556; CHECK-NEXT: fcvt.bf16.s fa0, fa557; CHECK-NEXT: flh fa5, 0(a0)58; CHECK-NEXT: fsh fa0, 0(a0)59; CHECK-NEXT: flh fa5, 18(a0)60; CHECK-NEXT: fsh fa0, 18(a0)61; CHECK-NEXT: ret62 %1 = fadd bfloat %a, %b63 %2 = load volatile bfloat, ptr @G64 store bfloat %1, ptr @G65 %3 = getelementptr bfloat, ptr @G, i32 966 %4 = load volatile bfloat, ptr %367 store bfloat %1, ptr %368 ret bfloat %169}70 71; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 172define bfloat @flh_fsh_constant(bfloat %a) nounwind {73; RV32IZFBFMIN-LABEL: flh_fsh_constant:74; RV32IZFBFMIN: # %bb.0:75; RV32IZFBFMIN-NEXT: lui a0, 91209276; RV32IZFBFMIN-NEXT: flh fa5, -273(a0)77; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa078; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa579; RV32IZFBFMIN-NEXT: fadd.s fa5, fa4, fa580; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa581; RV32IZFBFMIN-NEXT: fsh fa0, -273(a0)82; RV32IZFBFMIN-NEXT: ret83;84; RV64IZFBFMIN-LABEL: flh_fsh_constant:85; RV64IZFBFMIN: # %bb.0:86; RV64IZFBFMIN-NEXT: lui a0, 22802387; RV64IZFBFMIN-NEXT: slli a0, a0, 288; RV64IZFBFMIN-NEXT: flh fa5, -273(a0)89; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa090; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa591; RV64IZFBFMIN-NEXT: fadd.s fa5, fa4, fa592; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa593; RV64IZFBFMIN-NEXT: fsh fa0, -273(a0)94; RV64IZFBFMIN-NEXT: ret95 %1 = inttoptr i32 3735928559 to ptr96 %2 = load volatile bfloat, ptr %197 %3 = fadd bfloat %a, %298 store bfloat %3, ptr %199 ret bfloat %3100}101 102declare void @notdead(ptr)103 104define bfloat @flh_stack(bfloat %a) nounwind {105; RV32IZFBFMIN-LABEL: flh_stack:106; RV32IZFBFMIN: # %bb.0:107; RV32IZFBFMIN-NEXT: addi sp, sp, -16108; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill109; RV32IZFBFMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill110; RV32IZFBFMIN-NEXT: fmv.s fs0, fa0111; RV32IZFBFMIN-NEXT: addi a0, sp, 4112; RV32IZFBFMIN-NEXT: call notdead113; RV32IZFBFMIN-NEXT: flh fa5, 4(sp)114; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fs0115; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa5116; RV32IZFBFMIN-NEXT: fadd.s fa5, fa5, fa4117; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5118; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload119; RV32IZFBFMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload120; RV32IZFBFMIN-NEXT: addi sp, sp, 16121; RV32IZFBFMIN-NEXT: ret122;123; RV64IZFBFMIN-LABEL: flh_stack:124; RV64IZFBFMIN: # %bb.0:125; RV64IZFBFMIN-NEXT: addi sp, sp, -16126; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill127; RV64IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill128; RV64IZFBFMIN-NEXT: fmv.s fs0, fa0129; RV64IZFBFMIN-NEXT: mv a0, sp130; RV64IZFBFMIN-NEXT: call notdead131; RV64IZFBFMIN-NEXT: flh fa5, 0(sp)132; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fs0133; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa5134; RV64IZFBFMIN-NEXT: fadd.s fa5, fa5, fa4135; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5136; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload137; RV64IZFBFMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload138; RV64IZFBFMIN-NEXT: addi sp, sp, 16139; RV64IZFBFMIN-NEXT: ret140 %1 = alloca bfloat, align 4141 call void @notdead(ptr %1)142 %2 = load bfloat, ptr %1143 %3 = fadd bfloat %2, %a ; force load in to FPR16144 ret bfloat %3145}146 147define dso_local void @fsh_stack(bfloat %a, bfloat %b) nounwind {148; RV32IZFBFMIN-LABEL: fsh_stack:149; RV32IZFBFMIN: # %bb.0:150; RV32IZFBFMIN-NEXT: addi sp, sp, -16151; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill152; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa1153; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0154; RV32IZFBFMIN-NEXT: fadd.s fa5, fa4, fa5155; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5156; RV32IZFBFMIN-NEXT: fsh fa5, 8(sp)157; RV32IZFBFMIN-NEXT: addi a0, sp, 8158; RV32IZFBFMIN-NEXT: call notdead159; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload160; RV32IZFBFMIN-NEXT: addi sp, sp, 16161; RV32IZFBFMIN-NEXT: ret162;163; RV64IZFBFMIN-LABEL: fsh_stack:164; RV64IZFBFMIN: # %bb.0:165; RV64IZFBFMIN-NEXT: addi sp, sp, -16166; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill167; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa1168; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0169; RV64IZFBFMIN-NEXT: fadd.s fa5, fa4, fa5170; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5171; RV64IZFBFMIN-NEXT: fsh fa5, 4(sp)172; RV64IZFBFMIN-NEXT: addi a0, sp, 4173; RV64IZFBFMIN-NEXT: call notdead174; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload175; RV64IZFBFMIN-NEXT: addi sp, sp, 16176; RV64IZFBFMIN-NEXT: ret177 %1 = fadd bfloat %a, %b ; force store from FPR16178 %2 = alloca bfloat, align 4179 store bfloat %1, ptr %2180 call void @notdead(ptr %2)181 ret void182}183