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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv32 -mattr=+zbb -mattr=+m -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV32ZBB6; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefix=RV32XTHEADBB8; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \9; RUN: | FileCheck %s -check-prefix=RV32XTHEADMAC10; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \11; RUN: | FileCheck %s -check-prefix=RV32XTHEAD12; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \13; RUN: | FileCheck %s -check-prefix=RV64I14; RUN: llc -mtriple=riscv64 -mattr=+zbb -mattr=+m -verify-machineinstrs < %s \15; RUN: | FileCheck %s -check-prefix=RV64ZBB16; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \17; RUN: | FileCheck %s -check-prefix=RV64XTHEADMAC18; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \19; RUN: | FileCheck %s -check-prefix=RV64XTHEADBB20; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \21; RUN: | FileCheck %s -check-prefix=RV64XTHEAD22 23define i32 @f(i32 %A, i32 %B, i32 %C) {24; RV32I-LABEL: f:25; RV32I: # %bb.0: # %entry26; RV32I-NEXT: mul a0, a1, a027; RV32I-NEXT: slli a1, a0, 2628; RV32I-NEXT: slli a0, a0, 2029; RV32I-NEXT: srli a1, a1, 2830; RV32I-NEXT: srli a0, a0, 2531; RV32I-NEXT: mul a0, a1, a032; RV32I-NEXT: add a0, a0, a233; RV32I-NEXT: ret34;35; RV32ZBB-LABEL: f:36; RV32ZBB: # %bb.0: # %entry37; RV32ZBB-NEXT: mul a0, a1, a038; RV32ZBB-NEXT: slli a1, a0, 2639; RV32ZBB-NEXT: slli a0, a0, 2040; RV32ZBB-NEXT: srli a1, a1, 2841; RV32ZBB-NEXT: srli a0, a0, 2542; RV32ZBB-NEXT: mul a0, a1, a043; RV32ZBB-NEXT: add a0, a0, a244; RV32ZBB-NEXT: ret45;46; RV32XTHEADBB-LABEL: f:47; RV32XTHEADBB: # %bb.0: # %entry48; RV32XTHEADBB-NEXT: mul a0, a1, a049; RV32XTHEADBB-NEXT: th.extu a1, a0, 5, 250; RV32XTHEADBB-NEXT: th.extu a0, a0, 11, 551; RV32XTHEADBB-NEXT: mul a0, a1, a052; RV32XTHEADBB-NEXT: add a0, a0, a253; RV32XTHEADBB-NEXT: ret54;55; RV32XTHEADMAC-LABEL: f:56; RV32XTHEADMAC: # %bb.0: # %entry57; RV32XTHEADMAC-NEXT: mul a0, a1, a058; RV32XTHEADMAC-NEXT: slli a1, a0, 2659; RV32XTHEADMAC-NEXT: slli a0, a0, 2060; RV32XTHEADMAC-NEXT: srli a1, a1, 2861; RV32XTHEADMAC-NEXT: srli a0, a0, 2562; RV32XTHEADMAC-NEXT: th.mulah a2, a1, a063; RV32XTHEADMAC-NEXT: mv a0, a264; RV32XTHEADMAC-NEXT: ret65;66; RV32XTHEAD-LABEL: f:67; RV32XTHEAD: # %bb.0: # %entry68; RV32XTHEAD-NEXT: mul a0, a1, a069; RV32XTHEAD-NEXT: th.extu a1, a0, 5, 270; RV32XTHEAD-NEXT: th.extu a0, a0, 11, 571; RV32XTHEAD-NEXT: th.mulah a2, a1, a072; RV32XTHEAD-NEXT: mv a0, a273; RV32XTHEAD-NEXT: ret74;75; RV64I-LABEL: f:76; RV64I: # %bb.0: # %entry77; RV64I-NEXT: mul a0, a1, a078; RV64I-NEXT: slli a1, a0, 5879; RV64I-NEXT: slli a0, a0, 5280; RV64I-NEXT: srli a1, a1, 6081; RV64I-NEXT: srli a0, a0, 5782; RV64I-NEXT: mul a0, a1, a083; RV64I-NEXT: addw a0, a0, a284; RV64I-NEXT: ret85;86; RV64ZBB-LABEL: f:87; RV64ZBB: # %bb.0: # %entry88; RV64ZBB-NEXT: mul a0, a1, a089; RV64ZBB-NEXT: slli a1, a0, 5890; RV64ZBB-NEXT: slli a0, a0, 5291; RV64ZBB-NEXT: srli a1, a1, 6092; RV64ZBB-NEXT: srli a0, a0, 5793; RV64ZBB-NEXT: mul a0, a1, a094; RV64ZBB-NEXT: addw a0, a0, a295; RV64ZBB-NEXT: ret96;97; RV64XTHEADMAC-LABEL: f:98; RV64XTHEADMAC: # %bb.0: # %entry99; RV64XTHEADMAC-NEXT: mul a0, a1, a0100; RV64XTHEADMAC-NEXT: slli a1, a0, 58101; RV64XTHEADMAC-NEXT: slli a0, a0, 52102; RV64XTHEADMAC-NEXT: srli a1, a1, 60103; RV64XTHEADMAC-NEXT: srli a0, a0, 57104; RV64XTHEADMAC-NEXT: th.mulah a2, a1, a0105; RV64XTHEADMAC-NEXT: mv a0, a2106; RV64XTHEADMAC-NEXT: ret107;108; RV64XTHEADBB-LABEL: f:109; RV64XTHEADBB: # %bb.0: # %entry110; RV64XTHEADBB-NEXT: mul a0, a1, a0111; RV64XTHEADBB-NEXT: th.extu a1, a0, 5, 2112; RV64XTHEADBB-NEXT: th.extu a0, a0, 11, 5113; RV64XTHEADBB-NEXT: mul a0, a1, a0114; RV64XTHEADBB-NEXT: addw a0, a0, a2115; RV64XTHEADBB-NEXT: ret116;117; RV64XTHEAD-LABEL: f:118; RV64XTHEAD: # %bb.0: # %entry119; RV64XTHEAD-NEXT: mul a0, a1, a0120; RV64XTHEAD-NEXT: th.extu a1, a0, 5, 2121; RV64XTHEAD-NEXT: th.extu a0, a0, 11, 5122; RV64XTHEAD-NEXT: th.mulah a2, a1, a0123; RV64XTHEAD-NEXT: mv a0, a2124; RV64XTHEAD-NEXT: ret125entry:126 %mul = mul nsw i32 %B, %A127 %0 = lshr i32 %mul, 2128 %and = and i32 %0, 15129 %1 = lshr i32 %mul, 5130 %and2 = and i32 %1, 127131 %mul3 = mul nuw nsw i32 %and, %and2132 %add = add i32 %mul3, %C133 ret i32 %add134}135