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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV324; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV646 7define i32 @optbranch_32(i32 %Arg) {8; RV32-LABEL: optbranch_32:9; RV32: # %bb.0: # %bb10; RV32-NEXT: addi a0, a0, 111; RV32-NEXT: bnez a0, .LBB0_212; RV32-NEXT: # %bb.1: # %bb213; RV32-NEXT: li a0, -114; RV32-NEXT: .LBB0_2: # %bb315; RV32-NEXT: ret16;17; RV64-LABEL: optbranch_32:18; RV64: # %bb.0: # %bb19; RV64-NEXT: addiw a0, a0, 120; RV64-NEXT: bnez a0, .LBB0_221; RV64-NEXT: # %bb.1: # %bb222; RV64-NEXT: li a0, -123; RV64-NEXT: .LBB0_2: # %bb324; RV64-NEXT: ret25bb:26 %i1 = icmp eq i32 %Arg, -127 br i1 %i1, label %bb2, label %bb328 29bb2:30 ret i32 -131 32bb3:33 %i4 = add nuw i32 %Arg, 134 ret i32 %i435}36 37define i64 @optbranch_64(i64 %Arg) {38; RV32-LABEL: optbranch_64:39; RV32: # %bb.0: # %bb40; RV32-NEXT: addi a0, a0, 141; RV32-NEXT: seqz a2, a042; RV32-NEXT: add a1, a1, a243; RV32-NEXT: or a2, a0, a144; RV32-NEXT: bnez a2, .LBB1_245; RV32-NEXT: # %bb.1: # %bb246; RV32-NEXT: li a0, -147; RV32-NEXT: li a1, -148; RV32-NEXT: .LBB1_2: # %bb349; RV32-NEXT: ret50;51; RV64-LABEL: optbranch_64:52; RV64: # %bb.0: # %bb53; RV64-NEXT: addi a0, a0, 154; RV64-NEXT: bnez a0, .LBB1_255; RV64-NEXT: # %bb.1: # %bb256; RV64-NEXT: li a0, -157; RV64-NEXT: .LBB1_2: # %bb358; RV64-NEXT: ret59bb:60 %i1 = icmp eq i64 %Arg, -161 br i1 %i1, label %bb2, label %bb362 63bb2:64 ret i64 -165 66bb3:67 %i4 = add nuw i64 %Arg, 168 ret i64 %i469}70 71define i32 @test_lshr(i32 %v) {72; RV32-LABEL: test_lshr:73; RV32: # %bb.0: # %entry74; RV32-NEXT: li a1, 075; RV32-NEXT: beqz a0, .LBB2_276; RV32-NEXT: .LBB2_1: # %for.body77; RV32-NEXT: # =>This Inner Loop Header: Depth=178; RV32-NEXT: andi a2, a0, 179; RV32-NEXT: srli a0, a0, 180; RV32-NEXT: add a1, a1, a281; RV32-NEXT: bnez a0, .LBB2_182; RV32-NEXT: .LBB2_2: # %for.end83; RV32-NEXT: mv a0, a184; RV32-NEXT: ret85;86; RV64-LABEL: test_lshr:87; RV64: # %bb.0: # %entry88; RV64-NEXT: sext.w a1, a089; RV64-NEXT: beqz a1, .LBB2_390; RV64-NEXT: # %bb.1: # %for.body.preheader91; RV64-NEXT: li a1, 092; RV64-NEXT: .LBB2_2: # %for.body93; RV64-NEXT: # =>This Inner Loop Header: Depth=194; RV64-NEXT: andi a2, a0, 195; RV64-NEXT: srliw a0, a0, 196; RV64-NEXT: addw a1, a1, a297; RV64-NEXT: bnez a0, .LBB2_298; RV64-NEXT: .LBB2_3: # %for.end99; RV64-NEXT: mv a0, a1100; RV64-NEXT: ret101entry:102 %tobool.not4 = icmp eq i32 %v, 0103 br i1 %tobool.not4, label %for.end, label %for.body104 105for.body: ; preds = %entry, %for.body106 %c.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]107 %v.addr.05 = phi i32 [ %shr, %for.body ], [ %v, %entry ]108 %and = and i32 %v.addr.05, 1109 %add = add i32 %c.06, %and110 %shr = lshr i32 %v.addr.05, 1111 %tobool.not = icmp ult i32 %v.addr.05, 2112 br i1 %tobool.not, label %for.end, label %for.body113 114for.end: ; preds = %for.body, %entry115 %c.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]116 ret i32 %c.0.lcssa117}118 119define i32 @test_lshr2(ptr nocapture %x, ptr nocapture readonly %y, i32 %n) {120; RV32-LABEL: test_lshr2:121; RV32: # %bb.0: # %entry122; RV32-NEXT: srli a2, a2, 2123; RV32-NEXT: beqz a2, .LBB3_3124; RV32-NEXT: # %bb.1: # %while.body.preheader125; RV32-NEXT: slli a2, a2, 2126; RV32-NEXT: add a2, a1, a2127; RV32-NEXT: .LBB3_2: # %while.body128; RV32-NEXT: # =>This Inner Loop Header: Depth=1129; RV32-NEXT: lw a3, 0(a1)130; RV32-NEXT: addi a4, a1, 4131; RV32-NEXT: slli a3, a3, 1132; RV32-NEXT: addi a1, a0, 4133; RV32-NEXT: sw a3, 0(a0)134; RV32-NEXT: mv a0, a1135; RV32-NEXT: mv a1, a4136; RV32-NEXT: bne a4, a2, .LBB3_2137; RV32-NEXT: .LBB3_3: # %while.end138; RV32-NEXT: li a0, 0139; RV32-NEXT: ret140;141; RV64-LABEL: test_lshr2:142; RV64: # %bb.0: # %entry143; RV64-NEXT: srliw a2, a2, 2144; RV64-NEXT: beqz a2, .LBB3_3145; RV64-NEXT: # %bb.1: # %while.body.preheader146; RV64-NEXT: addi a2, a2, -1147; RV64-NEXT: slli a2, a2, 32148; RV64-NEXT: srli a2, a2, 30149; RV64-NEXT: add a2, a2, a1150; RV64-NEXT: addi a2, a2, 4151; RV64-NEXT: .LBB3_2: # %while.body152; RV64-NEXT: # =>This Inner Loop Header: Depth=1153; RV64-NEXT: lw a3, 0(a1)154; RV64-NEXT: addi a4, a1, 4155; RV64-NEXT: slli a3, a3, 1156; RV64-NEXT: addi a1, a0, 4157; RV64-NEXT: sw a3, 0(a0)158; RV64-NEXT: mv a0, a1159; RV64-NEXT: mv a1, a4160; RV64-NEXT: bne a4, a2, .LBB3_2161; RV64-NEXT: .LBB3_3: # %while.end162; RV64-NEXT: li a0, 0163; RV64-NEXT: ret164entry:165 %tobool.not4 = icmp ult i32 %n, 4166 br i1 %tobool.not4, label %while.end, label %while.body.preheader167 168while.body.preheader: ; preds = %entry169 %shr = lshr i32 %n, 2170 br label %while.body171 172while.body: ; preds = %while.body.preheader, %while.body173 %c.07 = phi i32 [ %dec, %while.body ], [ %shr, %while.body.preheader ]174 %x.addr.06 = phi ptr [ %incdec.ptr1, %while.body ], [ %x, %while.body.preheader ]175 %y.addr.05 = phi ptr [ %incdec.ptr, %while.body ], [ %y, %while.body.preheader ]176 %incdec.ptr = getelementptr inbounds i32, ptr %y.addr.05, i32 1177 %0 = load i32, ptr %y.addr.05, align 4178 %mul = shl nsw i32 %0, 1179 %incdec.ptr1 = getelementptr inbounds i32, ptr %x.addr.06, i32 1180 store i32 %mul, ptr %x.addr.06, align 4181 %dec = add nsw i32 %c.07, -1182 %tobool.not = icmp eq i32 %dec, 0183 br i1 %tobool.not, label %while.end, label %while.body184 185while.end: ; preds = %while.body, %entry186 ret i32 0187}188