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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32I %s4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -block-placement-predecessor-limit=10 < %s \5; RUN: | FileCheck -check-prefix=RV32I-MBPLIMIT %s6 7define void @foo(i32 %a, ptr %b, i1 %c) nounwind {8; RV32I-LABEL: foo:9; RV32I: # %bb.0:10; RV32I-NEXT: lw a3, 0(a1)11; RV32I-NEXT: beq a3, a0, .LBB0_1412; RV32I-NEXT: # %bb.1: # %test213; RV32I-NEXT: lw a3, 0(a1)14; RV32I-NEXT: bne a3, a0, .LBB0_1415; RV32I-NEXT: # %bb.2: # %test316; RV32I-NEXT: lw a3, 0(a1)17; RV32I-NEXT: blt a3, a0, .LBB0_1418; RV32I-NEXT: # %bb.3: # %test419; RV32I-NEXT: lw a3, 0(a1)20; RV32I-NEXT: bge a3, a0, .LBB0_1421; RV32I-NEXT: # %bb.4: # %test522; RV32I-NEXT: lw a3, 0(a1)23; RV32I-NEXT: bltu a3, a0, .LBB0_1424; RV32I-NEXT: # %bb.5: # %test625; RV32I-NEXT: lw a3, 0(a1)26; RV32I-NEXT: bgeu a3, a0, .LBB0_1427; RV32I-NEXT: # %bb.6: # %test728; RV32I-NEXT: lw a3, 0(a1)29; RV32I-NEXT: blt a0, a3, .LBB0_1430; RV32I-NEXT: # %bb.7: # %test831; RV32I-NEXT: lw a3, 0(a1)32; RV32I-NEXT: bge a0, a3, .LBB0_1433; RV32I-NEXT: # %bb.8: # %test934; RV32I-NEXT: lw a3, 0(a1)35; RV32I-NEXT: bltu a0, a3, .LBB0_1436; RV32I-NEXT: # %bb.9: # %test1037; RV32I-NEXT: lw a3, 0(a1)38; RV32I-NEXT: bgeu a0, a3, .LBB0_1439; RV32I-NEXT: # %bb.10: # %test1140; RV32I-NEXT: lw zero, 0(a1)41; RV32I-NEXT: andi a2, a2, 142; RV32I-NEXT: bnez a2, .LBB0_1443; RV32I-NEXT: # %bb.11: # %test1244; RV32I-NEXT: lw a0, 0(a1)45; RV32I-NEXT: bgez a0, .LBB0_1446; RV32I-NEXT: # %bb.12: # %test1347; RV32I-NEXT: lw a0, 0(a1)48; RV32I-NEXT: blez a0, .LBB0_1449; RV32I-NEXT: # %bb.13: # %test1450; RV32I-NEXT: lw zero, 0(a1)51; RV32I-NEXT: .LBB0_14: # %end52; RV32I-NEXT: ret53;54; RV32I-MBPLIMIT-LABEL: foo:55; RV32I-MBPLIMIT: # %bb.0:56; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)57; RV32I-MBPLIMIT-NEXT: bne a3, a0, .LBB0_258; RV32I-MBPLIMIT-NEXT: .LBB0_1: # %end59; RV32I-MBPLIMIT-NEXT: ret60; RV32I-MBPLIMIT-NEXT: .LBB0_2: # %test261; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)62; RV32I-MBPLIMIT-NEXT: bne a3, a0, .LBB0_163; RV32I-MBPLIMIT-NEXT: # %bb.3: # %test364; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)65; RV32I-MBPLIMIT-NEXT: blt a3, a0, .LBB0_166; RV32I-MBPLIMIT-NEXT: # %bb.4: # %test467; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)68; RV32I-MBPLIMIT-NEXT: bge a3, a0, .LBB0_169; RV32I-MBPLIMIT-NEXT: # %bb.5: # %test570; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)71; RV32I-MBPLIMIT-NEXT: bltu a3, a0, .LBB0_172; RV32I-MBPLIMIT-NEXT: # %bb.6: # %test673; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)74; RV32I-MBPLIMIT-NEXT: bgeu a3, a0, .LBB0_175; RV32I-MBPLIMIT-NEXT: # %bb.7: # %test776; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)77; RV32I-MBPLIMIT-NEXT: blt a0, a3, .LBB0_178; RV32I-MBPLIMIT-NEXT: # %bb.8: # %test879; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)80; RV32I-MBPLIMIT-NEXT: bge a0, a3, .LBB0_181; RV32I-MBPLIMIT-NEXT: # %bb.9: # %test982; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)83; RV32I-MBPLIMIT-NEXT: bltu a0, a3, .LBB0_184; RV32I-MBPLIMIT-NEXT: # %bb.10: # %test1085; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)86; RV32I-MBPLIMIT-NEXT: bgeu a0, a3, .LBB0_187; RV32I-MBPLIMIT-NEXT: # %bb.11: # %test1188; RV32I-MBPLIMIT-NEXT: lw zero, 0(a1)89; RV32I-MBPLIMIT-NEXT: andi a2, a2, 190; RV32I-MBPLIMIT-NEXT: bnez a2, .LBB0_191; RV32I-MBPLIMIT-NEXT: # %bb.12: # %test1292; RV32I-MBPLIMIT-NEXT: lw a0, 0(a1)93; RV32I-MBPLIMIT-NEXT: bgez a0, .LBB0_194; RV32I-MBPLIMIT-NEXT: # %bb.13: # %test1395; RV32I-MBPLIMIT-NEXT: lw a0, 0(a1)96; RV32I-MBPLIMIT-NEXT: blez a0, .LBB0_197; RV32I-MBPLIMIT-NEXT: # %bb.14: # %test1498; RV32I-MBPLIMIT-NEXT: lw zero, 0(a1)99; RV32I-MBPLIMIT-NEXT: ret100 %val1 = load volatile i32, ptr %b101 %tst1 = icmp eq i32 %val1, %a102 br i1 %tst1, label %end, label %test2103 104test2:105 %val2 = load volatile i32, ptr %b106 %tst2 = icmp ne i32 %val2, %a107 br i1 %tst2, label %end, label %test3108 109test3:110 %val3 = load volatile i32, ptr %b111 %tst3 = icmp slt i32 %val3, %a112 br i1 %tst3, label %end, label %test4113 114test4:115 %val4 = load volatile i32, ptr %b116 %tst4 = icmp sge i32 %val4, %a117 br i1 %tst4, label %end, label %test5118 119test5:120 %val5 = load volatile i32, ptr %b121 %tst5 = icmp ult i32 %val5, %a122 br i1 %tst5, label %end, label %test6123 124test6:125 %val6 = load volatile i32, ptr %b126 %tst6 = icmp uge i32 %val6, %a127 br i1 %tst6, label %end, label %test7128 129; Check for condition codes that don't have a matching instruction130 131test7:132 %val7 = load volatile i32, ptr %b133 %tst7 = icmp sgt i32 %val7, %a134 br i1 %tst7, label %end, label %test8135 136test8:137 %val8 = load volatile i32, ptr %b138 %tst8 = icmp sle i32 %val8, %a139 br i1 %tst8, label %end, label %test9140 141test9:142 %val9 = load volatile i32, ptr %b143 %tst9 = icmp ugt i32 %val9, %a144 br i1 %tst9, label %end, label %test10145 146test10:147 %val10 = load volatile i32, ptr %b148 %tst10 = icmp ule i32 %val10, %a149 br i1 %tst10, label %end, label %test11150 151; Check the case of a branch where the condition was generated in another152; function153 154test11:155 %val11 = load volatile i32, ptr %b156 br i1 %c, label %end, label %test12157 158; Check that we use bgez for X > -1 which is the canonical form.159 160test12:161 %val12 = load volatile i32, ptr %b162 %tst12 = icmp sgt i32 %val12, -1163 br i1 %tst12, label %end, label %test13164 165; Check that we use blez (X <= 0) for (X < 1)166 167test13:168 %val13 = load volatile i32, ptr %b169 %tst13 = icmp slt i32 %val13, 1170 br i1 %tst13, label %end, label %test14171 172test14:173 %val14 = load volatile i32, ptr %b174 br label %end175 176end:177 ret void178}179