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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \3; RUN: -target-abi ilp32f < %s \4; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s5; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+d \6; RUN: -target-abi ilp32d < %s \7; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s8 9; This file contains tests that should have identical output for the ilp32f10; and ilp32d ABIs.11 12define i32 @callee_float_in_fpr(i32 %a, float %b) nounwind {13; RV32-ILP32FD-LABEL: callee_float_in_fpr:14; RV32-ILP32FD: # %bb.0:15; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz16; RV32-ILP32FD-NEXT: add a0, a0, a117; RV32-ILP32FD-NEXT: ret18 %b_fptosi = fptosi float %b to i3219 %1 = add i32 %a, %b_fptosi20 ret i32 %121}22 23define i32 @caller_float_in_fpr() nounwind {24; RV32-ILP32FD-LABEL: caller_float_in_fpr:25; RV32-ILP32FD: # %bb.0:26; RV32-ILP32FD-NEXT: addi sp, sp, -1627; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill28; RV32-ILP32FD-NEXT: lui a0, 26214429; RV32-ILP32FD-NEXT: fmv.w.x fa0, a030; RV32-ILP32FD-NEXT: li a0, 131; RV32-ILP32FD-NEXT: call callee_float_in_fpr32; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload33; RV32-ILP32FD-NEXT: addi sp, sp, 1634; RV32-ILP32FD-NEXT: ret35 %1 = call i32 @callee_float_in_fpr(i32 1, float 2.0)36 ret i32 %137}38 39; Must keep define on a single line due to an update_llc_test_checks.py limitation40define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind {41; RV32-ILP32FD-LABEL: callee_float_in_fpr_exhausted_gprs:42; RV32-ILP32FD: # %bb.0:43; RV32-ILP32FD-NEXT: lw a0, 0(sp)44; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz45; RV32-ILP32FD-NEXT: add a0, a0, a146; RV32-ILP32FD-NEXT: ret47 %f_fptosi = fptosi float %f to i3248 %1 = add i32 %e, %f_fptosi49 ret i32 %150}51 52define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {53; RV32-ILP32FD-LABEL: caller_float_in_fpr_exhausted_gprs:54; RV32-ILP32FD: # %bb.0:55; RV32-ILP32FD-NEXT: addi sp, sp, -1656; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill57; RV32-ILP32FD-NEXT: li a1, 558; RV32-ILP32FD-NEXT: lui a3, 26521659; RV32-ILP32FD-NEXT: li a0, 160; RV32-ILP32FD-NEXT: li a2, 261; RV32-ILP32FD-NEXT: li a4, 362; RV32-ILP32FD-NEXT: fmv.w.x fa0, a363; RV32-ILP32FD-NEXT: li a6, 464; RV32-ILP32FD-NEXT: sw a1, 0(sp)65; RV32-ILP32FD-NEXT: li a1, 066; RV32-ILP32FD-NEXT: li a3, 067; RV32-ILP32FD-NEXT: li a5, 068; RV32-ILP32FD-NEXT: li a7, 069; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs70; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload71; RV32-ILP32FD-NEXT: addi sp, sp, 1672; RV32-ILP32FD-NEXT: ret73 %1 = call i32 @callee_float_in_fpr_exhausted_gprs(74 i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0)75 ret i32 %176}77 78; Must keep define on a single line due to an update_llc_test_checks.py limitation79define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind {80; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs:81; RV32-ILP32FD: # %bb.0:82; RV32-ILP32FD-NEXT: fmv.w.x fa5, a083; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz84; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa5, rtz85; RV32-ILP32FD-NEXT: add a0, a0, a186; RV32-ILP32FD-NEXT: ret87 %h_fptosi = fptosi float %h to i3288 %i_fptosi = fptosi float %i to i3289 %1 = add i32 %h_fptosi, %i_fptosi90 ret i32 %191}92 93define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {94; RV32-ILP32FD-LABEL: caller_float_in_gpr_exhausted_fprs:95; RV32-ILP32FD: # %bb.0:96; RV32-ILP32FD-NEXT: addi sp, sp, -1697; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill98; RV32-ILP32FD-NEXT: lui a0, 26009699; RV32-ILP32FD-NEXT: lui a1, 262144100; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0101; RV32-ILP32FD-NEXT: lui a0, 263168102; RV32-ILP32FD-NEXT: fmv.w.x fa1, a1103; RV32-ILP32FD-NEXT: lui a1, 264192104; RV32-ILP32FD-NEXT: fmv.w.x fa2, a0105; RV32-ILP32FD-NEXT: lui a0, 264704106; RV32-ILP32FD-NEXT: fmv.w.x fa3, a1107; RV32-ILP32FD-NEXT: lui a1, 265216108; RV32-ILP32FD-NEXT: fmv.w.x fa4, a0109; RV32-ILP32FD-NEXT: lui a0, 265728110; RV32-ILP32FD-NEXT: fmv.w.x fa5, a1111; RV32-ILP32FD-NEXT: lui a1, 266240112; RV32-ILP32FD-NEXT: fmv.w.x fa6, a0113; RV32-ILP32FD-NEXT: fmv.w.x fa7, a1114; RV32-ILP32FD-NEXT: lui a0, 266496115; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs116; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload117; RV32-ILP32FD-NEXT: addi sp, sp, 16118; RV32-ILP32FD-NEXT: ret119 %1 = call i32 @callee_float_in_gpr_exhausted_fprs(120 float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0,121 float 7.0, float 8.0, float 9.0)122 ret i32 %1123}124 125; Must keep define on a single line due to an update_llc_test_checks.py limitation126define i32 @callee_float_on_stack_exhausted_gprs_fprs(i64 %a, float %b, i64 %c, float %d, i64 %e, float %f, i64 %g, float %h, float %i, float %j, float %k, float %l, float %m) nounwind {127; RV32-ILP32FD-LABEL: callee_float_on_stack_exhausted_gprs_fprs:128; RV32-ILP32FD: # %bb.0:129; RV32-ILP32FD-NEXT: flw fa5, 0(sp)130; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa5, rtz131; RV32-ILP32FD-NEXT: add a0, a6, a0132; RV32-ILP32FD-NEXT: ret133 %g_trunc = trunc i64 %g to i32134 %m_fptosi = fptosi float %m to i32135 %1 = add i32 %g_trunc, %m_fptosi136 ret i32 %1137}138 139define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {140; RV32-ILP32FD-LABEL: caller_float_on_stack_exhausted_gprs_fprs:141; RV32-ILP32FD: # %bb.0:142; RV32-ILP32FD-NEXT: addi sp, sp, -16143; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill144; RV32-ILP32FD-NEXT: lui a1, 267520145; RV32-ILP32FD-NEXT: lui a0, 262144146; RV32-ILP32FD-NEXT: lui a2, 264192147; RV32-ILP32FD-NEXT: lui a3, 265216148; RV32-ILP32FD-NEXT: lui a4, 266240149; RV32-ILP32FD-NEXT: lui a5, 266496150; RV32-ILP32FD-NEXT: lui a6, 266752151; RV32-ILP32FD-NEXT: lui a7, 267008152; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0153; RV32-ILP32FD-NEXT: lui t0, 267264154; RV32-ILP32FD-NEXT: fmv.w.x fa1, a2155; RV32-ILP32FD-NEXT: li a0, 1156; RV32-ILP32FD-NEXT: fmv.w.x fa2, a3157; RV32-ILP32FD-NEXT: li a2, 3158; RV32-ILP32FD-NEXT: fmv.w.x fa3, a4159; RV32-ILP32FD-NEXT: li a4, 5160; RV32-ILP32FD-NEXT: fmv.w.x fa4, a5161; RV32-ILP32FD-NEXT: fmv.w.x fa5, a6162; RV32-ILP32FD-NEXT: fmv.w.x fa6, a7163; RV32-ILP32FD-NEXT: fmv.w.x fa7, t0164; RV32-ILP32FD-NEXT: li a6, 7165; RV32-ILP32FD-NEXT: sw a1, 0(sp)166; RV32-ILP32FD-NEXT: li a1, 0167; RV32-ILP32FD-NEXT: li a3, 0168; RV32-ILP32FD-NEXT: li a5, 0169; RV32-ILP32FD-NEXT: li a7, 0170; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs171; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload172; RV32-ILP32FD-NEXT: addi sp, sp, 16173; RV32-ILP32FD-NEXT: ret174 %1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs(175 i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0,176 float 9.0, float 10.0, float 11.0, float 12.0, float 13.0)177 ret i32 %1178}179 180define float @callee_float_ret() nounwind {181; RV32-ILP32FD-LABEL: callee_float_ret:182; RV32-ILP32FD: # %bb.0:183; RV32-ILP32FD-NEXT: lui a0, 260096184; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0185; RV32-ILP32FD-NEXT: ret186 ret float 1.0187}188 189define i32 @caller_float_ret() nounwind {190; RV32-ILP32FD-LABEL: caller_float_ret:191; RV32-ILP32FD: # %bb.0:192; RV32-ILP32FD-NEXT: addi sp, sp, -16193; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill194; RV32-ILP32FD-NEXT: call callee_float_ret195; RV32-ILP32FD-NEXT: fmv.x.w a0, fa0196; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload197; RV32-ILP32FD-NEXT: addi sp, sp, 16198; RV32-ILP32FD-NEXT: ret199 %1 = call float @callee_float_ret()200 %2 = bitcast float %1 to i32201 ret i32 %2202}203