64 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV64 %s4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64LP64F %s6 7define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) {8; RV64-LABEL: callee_v2f32:9; RV64: # %bb.0:10; RV64-NEXT: fmv.w.x fa5, a211; RV64-NEXT: fmv.w.x fa4, a012; RV64-NEXT: fmv.w.x fa3, a313; RV64-NEXT: fmv.w.x fa2, a114; RV64-NEXT: fadd.s fa3, fa2, fa315; RV64-NEXT: fadd.s fa5, fa4, fa516; RV64-NEXT: fmv.x.w a0, fa517; RV64-NEXT: fmv.x.w a1, fa318; RV64-NEXT: ret19;20; RV64LP64F-LABEL: callee_v2f32:21; RV64LP64F: # %bb.0:22; RV64LP64F-NEXT: fadd.s fa0, fa0, fa223; RV64LP64F-NEXT: fadd.s fa1, fa1, fa324; RV64LP64F-NEXT: ret25 %z = fadd <2 x float> %x, %y26 ret <2 x float> %z27}28 29define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) {30; RV64-LABEL: callee_v4f32:31; RV64: # %bb.0:32; RV64-NEXT: fmv.w.x fa5, a433; RV64-NEXT: fmv.w.x fa4, a734; RV64-NEXT: fmv.w.x fa3, a335; RV64-NEXT: fmv.w.x fa2, a636; RV64-NEXT: fmv.w.x fa1, a237; RV64-NEXT: fmv.w.x fa0, a538; RV64-NEXT: fmv.w.x ft0, a139; RV64-NEXT: flw ft1, 0(sp)40; RV64-NEXT: fadd.s fa0, ft0, fa041; RV64-NEXT: fadd.s fa2, fa1, fa242; RV64-NEXT: fadd.s fa4, fa3, fa443; RV64-NEXT: fadd.s fa5, fa5, ft144; RV64-NEXT: fsw fa0, 0(a0)45; RV64-NEXT: fsw fa2, 4(a0)46; RV64-NEXT: fsw fa4, 8(a0)47; RV64-NEXT: fsw fa5, 12(a0)48; RV64-NEXT: ret49;50; RV64LP64F-LABEL: callee_v4f32:51; RV64LP64F: # %bb.0:52; RV64LP64F-NEXT: fadd.s fa4, fa0, fa453; RV64LP64F-NEXT: fadd.s fa5, fa1, fa554; RV64LP64F-NEXT: fadd.s fa2, fa2, fa655; RV64LP64F-NEXT: fadd.s fa3, fa3, fa756; RV64LP64F-NEXT: fsw fa4, 0(a0)57; RV64LP64F-NEXT: fsw fa5, 4(a0)58; RV64LP64F-NEXT: fsw fa2, 8(a0)59; RV64LP64F-NEXT: fsw fa3, 12(a0)60; RV64LP64F-NEXT: ret61 %z = fadd <4 x float> %x, %y62 ret <4 x float> %z63}64