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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=small -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV32I-SMALL,RV32F-SMALL4; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=small -verify-machineinstrs -mattr=+experimental-xqcili < %s \5; RUN: | FileCheck %s -check-prefixes=RV32IXQCILI-SMALL,RV32FXQCILI-SMALL6; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=medium -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=RV32I-MEDIUM,RV32F-MEDIUM8; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=small -verify-machineinstrs < %s \9; RUN: | FileCheck %s -check-prefixes=RV64I-SMALL,RV64F-SMALL10; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=medium -verify-machineinstrs < %s \11; RUN: | FileCheck %s -check-prefixes=RV64I-MEDIUM,RV64F-MEDIUM12; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=large -verify-machineinstrs < %s \13; RUN: | FileCheck %s -check-prefixes=RV64I-LARGE,RV64F-LARGE14; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs < %s \15; RUN: | FileCheck %s -check-prefixes=RV32I-SMALL,RV32FINX-SMALL16; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs -mattr=+experimental-xqcili < %s \17; RUN: | FileCheck %s -check-prefixes=RV32IXQCILI-SMALL,RV32FINXXQCILI-SMALL18; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=medium -verify-machineinstrs < %s \19; RUN: | FileCheck %s -check-prefixes=RV32I-MEDIUM,RV32FINX-MEDIUM20; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=small -verify-machineinstrs < %s \21; RUN: | FileCheck %s -check-prefixes=RV64I-SMALL,RV64FINX-SMALL22; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=medium -verify-machineinstrs < %s \23; RUN: | FileCheck %s -check-prefixes=RV64I-MEDIUM,RV64FINX-MEDIUM24; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=large -verify-machineinstrs < %s \25; RUN: | FileCheck %s -check-prefixes=RV64I-LARGE,RV64FINX-LARGE26 27; Check lowering of globals28@G = global i32 029 30define i32 @lower_global(i32 %a) nounwind {31; RV32I-SMALL-LABEL: lower_global:32; RV32I-SMALL: # %bb.0:33; RV32I-SMALL-NEXT: lui a0, %hi(G)34; RV32I-SMALL-NEXT: lw a0, %lo(G)(a0)35; RV32I-SMALL-NEXT: ret36;37; RV32IXQCILI-SMALL-LABEL: lower_global:38; RV32IXQCILI-SMALL: # %bb.0:39; RV32IXQCILI-SMALL-NEXT: qc.e.li a0, G40; RV32IXQCILI-SMALL-NEXT: lw a0, 0(a0)41; RV32IXQCILI-SMALL-NEXT: ret42;43; RV32I-MEDIUM-LABEL: lower_global:44; RV32I-MEDIUM: # %bb.0:45; RV32I-MEDIUM-NEXT: .Lpcrel_hi0:46; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(G)47; RV32I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0)48; RV32I-MEDIUM-NEXT: ret49;50; RV64I-SMALL-LABEL: lower_global:51; RV64I-SMALL: # %bb.0:52; RV64I-SMALL-NEXT: lui a0, %hi(G)53; RV64I-SMALL-NEXT: lw a0, %lo(G)(a0)54; RV64I-SMALL-NEXT: ret55;56; RV64I-MEDIUM-LABEL: lower_global:57; RV64I-MEDIUM: # %bb.0:58; RV64I-MEDIUM-NEXT: .Lpcrel_hi0:59; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(G)60; RV64I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0)61; RV64I-MEDIUM-NEXT: ret62;63; RV64I-LARGE-LABEL: lower_global:64; RV64I-LARGE: # %bb.0:65; RV64I-LARGE-NEXT: .Lpcrel_hi0:66; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI0_0)67; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)68; RV64I-LARGE-NEXT: lw a0, 0(a0)69; RV64I-LARGE-NEXT: ret70 %1 = load volatile i32, ptr @G71 ret i32 %172}73 74; Check lowering of blockaddresses75 76@addr = global ptr null77 78define void @lower_blockaddress() nounwind {79; RV32I-SMALL-LABEL: lower_blockaddress:80; RV32I-SMALL: # %bb.0:81; RV32I-SMALL-NEXT: lui a0, %hi(addr)82; RV32I-SMALL-NEXT: li a1, 183; RV32I-SMALL-NEXT: sw a1, %lo(addr)(a0)84; RV32I-SMALL-NEXT: ret85;86; RV32IXQCILI-SMALL-LABEL: lower_blockaddress:87; RV32IXQCILI-SMALL: # %bb.0:88; RV32IXQCILI-SMALL-NEXT: qc.e.li a0, addr89; RV32IXQCILI-SMALL-NEXT: li a1, 190; RV32IXQCILI-SMALL-NEXT: sw a1, 0(a0)91; RV32IXQCILI-SMALL-NEXT: ret92;93; RV32I-MEDIUM-LABEL: lower_blockaddress:94; RV32I-MEDIUM: # %bb.0:95; RV32I-MEDIUM-NEXT: .Lpcrel_hi1:96; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(addr)97; RV32I-MEDIUM-NEXT: li a1, 198; RV32I-MEDIUM-NEXT: sw a1, %pcrel_lo(.Lpcrel_hi1)(a0)99; RV32I-MEDIUM-NEXT: ret100;101; RV64I-SMALL-LABEL: lower_blockaddress:102; RV64I-SMALL: # %bb.0:103; RV64I-SMALL-NEXT: lui a0, %hi(addr)104; RV64I-SMALL-NEXT: li a1, 1105; RV64I-SMALL-NEXT: sd a1, %lo(addr)(a0)106; RV64I-SMALL-NEXT: ret107;108; RV64I-MEDIUM-LABEL: lower_blockaddress:109; RV64I-MEDIUM: # %bb.0:110; RV64I-MEDIUM-NEXT: .Lpcrel_hi1:111; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(addr)112; RV64I-MEDIUM-NEXT: li a1, 1113; RV64I-MEDIUM-NEXT: sd a1, %pcrel_lo(.Lpcrel_hi1)(a0)114; RV64I-MEDIUM-NEXT: ret115;116; RV64I-LARGE-LABEL: lower_blockaddress:117; RV64I-LARGE: # %bb.0:118; RV64I-LARGE-NEXT: .Lpcrel_hi1:119; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI1_0)120; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)121; RV64I-LARGE-NEXT: li a1, 1122; RV64I-LARGE-NEXT: sd a1, 0(a0)123; RV64I-LARGE-NEXT: ret124 store volatile ptr blockaddress(@lower_blockaddress, %block), ptr @addr125 ret void126 127block:128 unreachable129}130 131; Check lowering of blockaddress that forces a displacement to be added132 133define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {134; RV32I-SMALL-LABEL: lower_blockaddress_displ:135; RV32I-SMALL: # %bb.0: # %entry136; RV32I-SMALL-NEXT: addi sp, sp, -16137; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0)138; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0)139; RV32I-SMALL-NEXT: li a2, 101140; RV32I-SMALL-NEXT: sw a1, 8(sp)141; RV32I-SMALL-NEXT: blt a0, a2, .LBB2_3142; RV32I-SMALL-NEXT: # %bb.1: # %if.then143; RV32I-SMALL-NEXT: lw a0, 8(sp)144; RV32I-SMALL-NEXT: jr a0145; RV32I-SMALL-NEXT: .Ltmp0: # Block address taken146; RV32I-SMALL-NEXT: .LBB2_2: # %return147; RV32I-SMALL-NEXT: li a0, 4148; RV32I-SMALL-NEXT: addi sp, sp, 16149; RV32I-SMALL-NEXT: ret150; RV32I-SMALL-NEXT: .LBB2_3: # %return.clone151; RV32I-SMALL-NEXT: li a0, 3152; RV32I-SMALL-NEXT: addi sp, sp, 16153; RV32I-SMALL-NEXT: ret154;155; RV32IXQCILI-SMALL-LABEL: lower_blockaddress_displ:156; RV32IXQCILI-SMALL: # %bb.0: # %entry157; RV32IXQCILI-SMALL-NEXT: addi sp, sp, -16158; RV32IXQCILI-SMALL-NEXT: qc.e.li a1, .Ltmp0159; RV32IXQCILI-SMALL-NEXT: li a2, 101160; RV32IXQCILI-SMALL-NEXT: sw a1, 8(sp)161; RV32IXQCILI-SMALL-NEXT: blt a0, a2, .LBB2_3162; RV32IXQCILI-SMALL-NEXT: # %bb.1: # %if.then163; RV32IXQCILI-SMALL-NEXT: lw a0, 8(sp)164; RV32IXQCILI-SMALL-NEXT: jr a0165; RV32IXQCILI-SMALL-NEXT: .Ltmp0: # Block address taken166; RV32IXQCILI-SMALL-NEXT: .LBB2_2: # %return167; RV32IXQCILI-SMALL-NEXT: li a0, 4168; RV32IXQCILI-SMALL-NEXT: addi sp, sp, 16169; RV32IXQCILI-SMALL-NEXT: ret170; RV32IXQCILI-SMALL-NEXT: .LBB2_3: # %return.clone171; RV32IXQCILI-SMALL-NEXT: li a0, 3172; RV32IXQCILI-SMALL-NEXT: addi sp, sp, 16173; RV32IXQCILI-SMALL-NEXT: ret174;175; RV32I-MEDIUM-LABEL: lower_blockaddress_displ:176; RV32I-MEDIUM: # %bb.0: # %entry177; RV32I-MEDIUM-NEXT: addi sp, sp, -16178; RV32I-MEDIUM-NEXT: .Lpcrel_hi2:179; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)180; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi2)181; RV32I-MEDIUM-NEXT: li a2, 101182; RV32I-MEDIUM-NEXT: sw a1, 8(sp)183; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3184; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then185; RV32I-MEDIUM-NEXT: lw a0, 8(sp)186; RV32I-MEDIUM-NEXT: jr a0187; RV32I-MEDIUM-NEXT: .Ltmp0: # Block address taken188; RV32I-MEDIUM-NEXT: .LBB2_2: # %return189; RV32I-MEDIUM-NEXT: li a0, 4190; RV32I-MEDIUM-NEXT: addi sp, sp, 16191; RV32I-MEDIUM-NEXT: ret192; RV32I-MEDIUM-NEXT: .LBB2_3: # %return.clone193; RV32I-MEDIUM-NEXT: li a0, 3194; RV32I-MEDIUM-NEXT: addi sp, sp, 16195; RV32I-MEDIUM-NEXT: ret196;197; RV64I-SMALL-LABEL: lower_blockaddress_displ:198; RV64I-SMALL: # %bb.0: # %entry199; RV64I-SMALL-NEXT: addi sp, sp, -16200; RV64I-SMALL-NEXT: lui a1, %hi(.Ltmp0)201; RV64I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0)202; RV64I-SMALL-NEXT: li a2, 101203; RV64I-SMALL-NEXT: sd a1, 8(sp)204; RV64I-SMALL-NEXT: blt a0, a2, .LBB2_3205; RV64I-SMALL-NEXT: # %bb.1: # %if.then206; RV64I-SMALL-NEXT: ld a0, 8(sp)207; RV64I-SMALL-NEXT: jr a0208; RV64I-SMALL-NEXT: .Ltmp0: # Block address taken209; RV64I-SMALL-NEXT: .LBB2_2: # %return210; RV64I-SMALL-NEXT: li a0, 4211; RV64I-SMALL-NEXT: addi sp, sp, 16212; RV64I-SMALL-NEXT: ret213; RV64I-SMALL-NEXT: .LBB2_3: # %return.clone214; RV64I-SMALL-NEXT: li a0, 3215; RV64I-SMALL-NEXT: addi sp, sp, 16216; RV64I-SMALL-NEXT: ret217;218; RV64I-MEDIUM-LABEL: lower_blockaddress_displ:219; RV64I-MEDIUM: # %bb.0: # %entry220; RV64I-MEDIUM-NEXT: addi sp, sp, -16221; RV64I-MEDIUM-NEXT: .Lpcrel_hi2:222; RV64I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)223; RV64I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi2)224; RV64I-MEDIUM-NEXT: li a2, 101225; RV64I-MEDIUM-NEXT: sd a1, 8(sp)226; RV64I-MEDIUM-NEXT: blt a0, a2, .LBB2_3227; RV64I-MEDIUM-NEXT: # %bb.1: # %if.then228; RV64I-MEDIUM-NEXT: ld a0, 8(sp)229; RV64I-MEDIUM-NEXT: jr a0230; RV64I-MEDIUM-NEXT: .Ltmp0: # Block address taken231; RV64I-MEDIUM-NEXT: .LBB2_2: # %return232; RV64I-MEDIUM-NEXT: li a0, 4233; RV64I-MEDIUM-NEXT: addi sp, sp, 16234; RV64I-MEDIUM-NEXT: ret235; RV64I-MEDIUM-NEXT: .LBB2_3: # %return.clone236; RV64I-MEDIUM-NEXT: li a0, 3237; RV64I-MEDIUM-NEXT: addi sp, sp, 16238; RV64I-MEDIUM-NEXT: ret239;240; RV64I-LARGE-LABEL: lower_blockaddress_displ:241; RV64I-LARGE: # %bb.0: # %entry242; RV64I-LARGE-NEXT: addi sp, sp, -16243; RV64I-LARGE-NEXT: .Lpcrel_hi2:244; RV64I-LARGE-NEXT: auipc a1, %pcrel_hi(.Ltmp0)245; RV64I-LARGE-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi2)246; RV64I-LARGE-NEXT: li a2, 101247; RV64I-LARGE-NEXT: sd a1, 8(sp)248; RV64I-LARGE-NEXT: blt a0, a2, .LBB2_3249; RV64I-LARGE-NEXT: # %bb.1: # %if.then250; RV64I-LARGE-NEXT: ld a0, 8(sp)251; RV64I-LARGE-NEXT: jr a0252; RV64I-LARGE-NEXT: .Ltmp0: # Block address taken253; RV64I-LARGE-NEXT: .LBB2_2: # %return254; RV64I-LARGE-NEXT: li a0, 4255; RV64I-LARGE-NEXT: addi sp, sp, 16256; RV64I-LARGE-NEXT: ret257; RV64I-LARGE-NEXT: .LBB2_3: # %return.clone258; RV64I-LARGE-NEXT: li a0, 3259; RV64I-LARGE-NEXT: addi sp, sp, 16260; RV64I-LARGE-NEXT: ret261entry:262 %x = alloca ptr, align 8263 store ptr blockaddress(@lower_blockaddress_displ, %test_block), ptr %x, align 8264 %cmp = icmp sgt i32 %w, 100265 br i1 %cmp, label %if.then, label %if.end266 267if.then:268 %addr = load ptr, ptr %x, align 8269 br label %indirectgoto270 271if.end:272 br label %return273 274test_block:275 br label %return276 277return:278 %retval = phi i32 [ 3, %if.end ], [ 4, %test_block ]279 ret i32 %retval280 281indirectgoto:282 indirectbr ptr %addr, [ label %test_block ]283}284 285; Check lowering of constantpools286 287define float @lower_constantpool(float %a) nounwind {288; RV32F-SMALL-LABEL: lower_constantpool:289; RV32F-SMALL: # %bb.0:290; RV32F-SMALL-NEXT: lui a0, 260097291; RV32F-SMALL-NEXT: addi a0, a0, -2048292; RV32F-SMALL-NEXT: fmv.w.x fa5, a0293; RV32F-SMALL-NEXT: fadd.s fa0, fa0, fa5294; RV32F-SMALL-NEXT: ret295;296; RV32FXQCILI-SMALL-LABEL: lower_constantpool:297; RV32FXQCILI-SMALL: # %bb.0:298; RV32FXQCILI-SMALL-NEXT: qc.e.li a0, 1065355264299; RV32FXQCILI-SMALL-NEXT: fmv.w.x fa5, a0300; RV32FXQCILI-SMALL-NEXT: fadd.s fa0, fa0, fa5301; RV32FXQCILI-SMALL-NEXT: ret302;303; RV32F-MEDIUM-LABEL: lower_constantpool:304; RV32F-MEDIUM: # %bb.0:305; RV32F-MEDIUM-NEXT: lui a0, 260097306; RV32F-MEDIUM-NEXT: addi a0, a0, -2048307; RV32F-MEDIUM-NEXT: fmv.w.x fa5, a0308; RV32F-MEDIUM-NEXT: fadd.s fa0, fa0, fa5309; RV32F-MEDIUM-NEXT: ret310;311; RV64F-SMALL-LABEL: lower_constantpool:312; RV64F-SMALL: # %bb.0:313; RV64F-SMALL-NEXT: lui a0, 260097314; RV64F-SMALL-NEXT: addi a0, a0, -2048315; RV64F-SMALL-NEXT: fmv.w.x fa5, a0316; RV64F-SMALL-NEXT: fadd.s fa0, fa0, fa5317; RV64F-SMALL-NEXT: ret318;319; RV64F-MEDIUM-LABEL: lower_constantpool:320; RV64F-MEDIUM: # %bb.0:321; RV64F-MEDIUM-NEXT: lui a0, 260097322; RV64F-MEDIUM-NEXT: addi a0, a0, -2048323; RV64F-MEDIUM-NEXT: fmv.w.x fa5, a0324; RV64F-MEDIUM-NEXT: fadd.s fa0, fa0, fa5325; RV64F-MEDIUM-NEXT: ret326;327; RV64F-LARGE-LABEL: lower_constantpool:328; RV64F-LARGE: # %bb.0:329; RV64F-LARGE-NEXT: lui a0, 260097330; RV64F-LARGE-NEXT: addi a0, a0, -2048331; RV64F-LARGE-NEXT: fmv.w.x fa5, a0332; RV64F-LARGE-NEXT: fadd.s fa0, fa0, fa5333; RV64F-LARGE-NEXT: ret334;335; RV32FINX-SMALL-LABEL: lower_constantpool:336; RV32FINX-SMALL: # %bb.0:337; RV32FINX-SMALL-NEXT: lui a1, 260097338; RV32FINX-SMALL-NEXT: addi a1, a1, -2048339; RV32FINX-SMALL-NEXT: fadd.s a0, a0, a1340; RV32FINX-SMALL-NEXT: ret341;342; RV32FINXXQCILI-SMALL-LABEL: lower_constantpool:343; RV32FINXXQCILI-SMALL: # %bb.0:344; RV32FINXXQCILI-SMALL-NEXT: qc.e.li a1, 1065355264345; RV32FINXXQCILI-SMALL-NEXT: fadd.s a0, a0, a1346; RV32FINXXQCILI-SMALL-NEXT: ret347;348; RV32FINX-MEDIUM-LABEL: lower_constantpool:349; RV32FINX-MEDIUM: # %bb.0:350; RV32FINX-MEDIUM-NEXT: lui a1, 260097351; RV32FINX-MEDIUM-NEXT: addi a1, a1, -2048352; RV32FINX-MEDIUM-NEXT: fadd.s a0, a0, a1353; RV32FINX-MEDIUM-NEXT: ret354;355; RV64FINX-SMALL-LABEL: lower_constantpool:356; RV64FINX-SMALL: # %bb.0:357; RV64FINX-SMALL-NEXT: lui a1, 260097358; RV64FINX-SMALL-NEXT: addi a1, a1, -2048359; RV64FINX-SMALL-NEXT: fadd.s a0, a0, a1360; RV64FINX-SMALL-NEXT: ret361;362; RV64FINX-MEDIUM-LABEL: lower_constantpool:363; RV64FINX-MEDIUM: # %bb.0:364; RV64FINX-MEDIUM-NEXT: lui a1, 260097365; RV64FINX-MEDIUM-NEXT: addi a1, a1, -2048366; RV64FINX-MEDIUM-NEXT: fadd.s a0, a0, a1367; RV64FINX-MEDIUM-NEXT: ret368;369; RV64FINX-LARGE-LABEL: lower_constantpool:370; RV64FINX-LARGE: # %bb.0:371; RV64FINX-LARGE-NEXT: lui a1, 260097372; RV64FINX-LARGE-NEXT: addi a1, a1, -2048373; RV64FINX-LARGE-NEXT: fadd.s a0, a0, a1374; RV64FINX-LARGE-NEXT: ret375 %1 = fadd float %a, 1.000244140625376 ret float %1377}378 379; Check lowering of extern_weaks380@W = extern_weak global i32381 382define i32 @lower_extern_weak(i32 %a) nounwind {383; RV32I-SMALL-LABEL: lower_extern_weak:384; RV32I-SMALL: # %bb.0:385; RV32I-SMALL-NEXT: lui a0, %hi(W)386; RV32I-SMALL-NEXT: lw a0, %lo(W)(a0)387; RV32I-SMALL-NEXT: ret388;389; RV32IXQCILI-SMALL-LABEL: lower_extern_weak:390; RV32IXQCILI-SMALL: # %bb.0:391; RV32IXQCILI-SMALL-NEXT: qc.e.li a0, W392; RV32IXQCILI-SMALL-NEXT: lw a0, 0(a0)393; RV32IXQCILI-SMALL-NEXT: ret394;395; RV32I-MEDIUM-LABEL: lower_extern_weak:396; RV32I-MEDIUM: # %bb.0:397; RV32I-MEDIUM-NEXT: .Lpcrel_hi3:398; RV32I-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W)399; RV32I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi3)(a0)400; RV32I-MEDIUM-NEXT: lw a0, 0(a0)401; RV32I-MEDIUM-NEXT: ret402;403; RV64I-SMALL-LABEL: lower_extern_weak:404; RV64I-SMALL: # %bb.0:405; RV64I-SMALL-NEXT: lui a0, %hi(W)406; RV64I-SMALL-NEXT: lw a0, %lo(W)(a0)407; RV64I-SMALL-NEXT: ret408;409; RV64I-MEDIUM-LABEL: lower_extern_weak:410; RV64I-MEDIUM: # %bb.0:411; RV64I-MEDIUM-NEXT: .Lpcrel_hi3:412; RV64I-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W)413; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi3)(a0)414; RV64I-MEDIUM-NEXT: lw a0, 0(a0)415; RV64I-MEDIUM-NEXT: ret416;417; RV64I-LARGE-LABEL: lower_extern_weak:418; RV64I-LARGE: # %bb.0:419; RV64I-LARGE-NEXT: .Lpcrel_hi3:420; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI4_0)421; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi3)(a0)422; RV64I-LARGE-NEXT: lw a0, 0(a0)423; RV64I-LARGE-NEXT: ret424 %1 = load volatile i32, ptr @W425 ret i32 %1426}427 428@X = global half 1.5429 430define half @lower_global_half(half %a) nounwind {431; RV32F-SMALL-LABEL: lower_global_half:432; RV32F-SMALL: # %bb.0:433; RV32F-SMALL-NEXT: lui a0, %hi(X)434; RV32F-SMALL-NEXT: flh fa5, %lo(X)(a0)435; RV32F-SMALL-NEXT: fadd.h fa0, fa0, fa5436; RV32F-SMALL-NEXT: ret437;438; RV32FXQCILI-SMALL-LABEL: lower_global_half:439; RV32FXQCILI-SMALL: # %bb.0:440; RV32FXQCILI-SMALL-NEXT: qc.e.li a0, X441; RV32FXQCILI-SMALL-NEXT: flh fa5, 0(a0)442; RV32FXQCILI-SMALL-NEXT: fadd.h fa0, fa0, fa5443; RV32FXQCILI-SMALL-NEXT: ret444;445; RV32F-MEDIUM-LABEL: lower_global_half:446; RV32F-MEDIUM: # %bb.0:447; RV32F-MEDIUM-NEXT: .Lpcrel_hi4:448; RV32F-MEDIUM-NEXT: auipc a0, %pcrel_hi(X)449; RV32F-MEDIUM-NEXT: flh fa5, %pcrel_lo(.Lpcrel_hi4)(a0)450; RV32F-MEDIUM-NEXT: fadd.h fa0, fa0, fa5451; RV32F-MEDIUM-NEXT: ret452;453; RV64F-SMALL-LABEL: lower_global_half:454; RV64F-SMALL: # %bb.0:455; RV64F-SMALL-NEXT: lui a0, %hi(X)456; RV64F-SMALL-NEXT: flh fa5, %lo(X)(a0)457; RV64F-SMALL-NEXT: fadd.h fa0, fa0, fa5458; RV64F-SMALL-NEXT: ret459;460; RV64F-MEDIUM-LABEL: lower_global_half:461; RV64F-MEDIUM: # %bb.0:462; RV64F-MEDIUM-NEXT: .Lpcrel_hi4:463; RV64F-MEDIUM-NEXT: auipc a0, %pcrel_hi(X)464; RV64F-MEDIUM-NEXT: flh fa5, %pcrel_lo(.Lpcrel_hi4)(a0)465; RV64F-MEDIUM-NEXT: fadd.h fa0, fa0, fa5466; RV64F-MEDIUM-NEXT: ret467;468; RV64F-LARGE-LABEL: lower_global_half:469; RV64F-LARGE: # %bb.0:470; RV64F-LARGE-NEXT: .Lpcrel_hi4:471; RV64F-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI5_0)472; RV64F-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi4)(a0)473; RV64F-LARGE-NEXT: flh fa5, 0(a0)474; RV64F-LARGE-NEXT: fadd.h fa0, fa0, fa5475; RV64F-LARGE-NEXT: ret476;477; RV32FINX-SMALL-LABEL: lower_global_half:478; RV32FINX-SMALL: # %bb.0:479; RV32FINX-SMALL-NEXT: lui a1, %hi(X)480; RV32FINX-SMALL-NEXT: lh a1, %lo(X)(a1)481; RV32FINX-SMALL-NEXT: fadd.h a0, a0, a1482; RV32FINX-SMALL-NEXT: ret483;484; RV32FINXXQCILI-SMALL-LABEL: lower_global_half:485; RV32FINXXQCILI-SMALL: # %bb.0:486; RV32FINXXQCILI-SMALL-NEXT: qc.e.li a1, X487; RV32FINXXQCILI-SMALL-NEXT: lh a1, 0(a1)488; RV32FINXXQCILI-SMALL-NEXT: fadd.h a0, a0, a1489; RV32FINXXQCILI-SMALL-NEXT: ret490;491; RV32FINX-MEDIUM-LABEL: lower_global_half:492; RV32FINX-MEDIUM: # %bb.0:493; RV32FINX-MEDIUM-NEXT: .Lpcrel_hi4:494; RV32FINX-MEDIUM-NEXT: auipc a1, %pcrel_hi(X)495; RV32FINX-MEDIUM-NEXT: lh a1, %pcrel_lo(.Lpcrel_hi4)(a1)496; RV32FINX-MEDIUM-NEXT: fadd.h a0, a0, a1497; RV32FINX-MEDIUM-NEXT: ret498;499; RV64FINX-SMALL-LABEL: lower_global_half:500; RV64FINX-SMALL: # %bb.0:501; RV64FINX-SMALL-NEXT: lui a1, %hi(X)502; RV64FINX-SMALL-NEXT: lh a1, %lo(X)(a1)503; RV64FINX-SMALL-NEXT: fadd.h a0, a0, a1504; RV64FINX-SMALL-NEXT: ret505;506; RV64FINX-MEDIUM-LABEL: lower_global_half:507; RV64FINX-MEDIUM: # %bb.0:508; RV64FINX-MEDIUM-NEXT: .Lpcrel_hi4:509; RV64FINX-MEDIUM-NEXT: auipc a1, %pcrel_hi(X)510; RV64FINX-MEDIUM-NEXT: lh a1, %pcrel_lo(.Lpcrel_hi4)(a1)511; RV64FINX-MEDIUM-NEXT: fadd.h a0, a0, a1512; RV64FINX-MEDIUM-NEXT: ret513;514; RV64FINX-LARGE-LABEL: lower_global_half:515; RV64FINX-LARGE: # %bb.0:516; RV64FINX-LARGE-NEXT: .Lpcrel_hi4:517; RV64FINX-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI5_0)518; RV64FINX-LARGE-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi4)(a1)519; RV64FINX-LARGE-NEXT: lh a1, 0(a1)520; RV64FINX-LARGE-NEXT: fadd.h a0, a0, a1521; RV64FINX-LARGE-NEXT: ret522 %b = load half, ptr @X523 %1 = fadd half %a, %b524 ret half %1525}526