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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64-- -mattr=+m,+v,+f | FileCheck %s -check-prefix=RISCV3 4define void @test_masked_store_success_v4i8(<4 x i8> %x, ptr %ptr, <4 x i1> %mask) {5; RISCV-LABEL: test_masked_store_success_v4i8:6; RISCV: # %bb.0:7; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma8; RISCV-NEXT: vse8.v v8, (a0), v0.t9; RISCV-NEXT: ret10 %load = load <4 x i8>, ptr %ptr, align 3211 %sel = select <4 x i1> %mask, <4 x i8> %x, <4 x i8> %load12 store <4 x i8> %sel, ptr %ptr, align 3213 ret void14}15 16define void @test_masked_store_success_v4i16(<4 x i16> %x, ptr %ptr, <4 x i1> %mask) {17; RISCV-LABEL: test_masked_store_success_v4i16:18; RISCV: # %bb.0:19; RISCV-NEXT: vsetivli zero, 4, e16, mf2, ta, ma20; RISCV-NEXT: vse16.v v8, (a0), v0.t21; RISCV-NEXT: ret22 %load = load <4 x i16>, ptr %ptr, align 3223 %sel = select <4 x i1> %mask, <4 x i16> %x, <4 x i16> %load24 store <4 x i16> %sel, ptr %ptr, align 3225 ret void26}27 28define void @test_masked_store_success_v4i32(<4 x i32> %x, ptr %ptr, <4 x i1> %mask) {29; RISCV-LABEL: test_masked_store_success_v4i32:30; RISCV: # %bb.0:31; RISCV-NEXT: vsetivli zero, 4, e32, m1, ta, ma32; RISCV-NEXT: vse32.v v8, (a0), v0.t33; RISCV-NEXT: ret34 %load = load <4 x i32>, ptr %ptr, align 3235 %sel = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %load36 store <4 x i32> %sel, ptr %ptr, align 3237 ret void38}39 40define void @test_masked_store_success_v4i64(<4 x i64> %x, ptr %ptr, <4 x i1> %mask) {41; RISCV-LABEL: test_masked_store_success_v4i64:42; RISCV: # %bb.0:43; RISCV-NEXT: vsetivli zero, 4, e64, m2, ta, ma44; RISCV-NEXT: vse64.v v8, (a0), v0.t45; RISCV-NEXT: ret46 %load = load <4 x i64>, ptr %ptr, align 3247 %sel = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %load48 store <4 x i64> %sel, ptr %ptr, align 3249 ret void50}51 52define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> %mask) {53; RISCV-LABEL: test_masked_store_success_v4f16:54; RISCV: # %bb.0:55; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma56; RISCV-NEXT: vmv1r.v v9, v057; RISCV-NEXT: vfirst.m a3, v058; RISCV-NEXT: mv a2, a059; RISCV-NEXT: beqz a3, .LBB4_260; RISCV-NEXT: # %bb.1:61; RISCV-NEXT: mv a2, a162; RISCV-NEXT: .LBB4_2:63; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma64; RISCV-NEXT: vmv.v.i v8, 065; RISCV-NEXT: vmv1r.v v0, v966; RISCV-NEXT: vmerge.vim v8, v8, 1, v067; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma68; RISCV-NEXT: vslidedown.vi v8, v8, 269; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma70; RISCV-NEXT: vmsne.vi v8, v8, 071; RISCV-NEXT: vmv.v.i v10, 072; RISCV-NEXT: vmv1r.v v0, v873; RISCV-NEXT: vmerge.vim v11, v10, 1, v074; RISCV-NEXT: vslidedown.vi v11, v11, 175; RISCV-NEXT: vmv.x.s a3, v1176; RISCV-NEXT: andi a3, a3, 177; RISCV-NEXT: bnez a3, .LBB4_478; RISCV-NEXT: # %bb.3:79; RISCV-NEXT: addi a3, a1, 680; RISCV-NEXT: j .LBB4_581; RISCV-NEXT: .LBB4_4:82; RISCV-NEXT: addi a3, a0, 2483; RISCV-NEXT: .LBB4_5:84; RISCV-NEXT: vmv1r.v v0, v985; RISCV-NEXT: vmerge.vim v9, v10, 1, v086; RISCV-NEXT: vslidedown.vi v9, v9, 187; RISCV-NEXT: vmv.x.s a4, v988; RISCV-NEXT: andi a4, a4, 189; RISCV-NEXT: bnez a4, .LBB4_790; RISCV-NEXT: # %bb.6:91; RISCV-NEXT: addi a5, a1, 292; RISCV-NEXT: j .LBB4_893; RISCV-NEXT: .LBB4_7:94; RISCV-NEXT: addi a5, a0, 895; RISCV-NEXT: .LBB4_8:96; RISCV-NEXT: lh a4, 0(a2)97; RISCV-NEXT: lh a2, 0(a3)98; RISCV-NEXT: lh a3, 0(a5)99; RISCV-NEXT: vfirst.m a5, v8100; RISCV-NEXT: beqz a5, .LBB4_10101; RISCV-NEXT: # %bb.9:102; RISCV-NEXT: addi a0, a1, 4103; RISCV-NEXT: j .LBB4_11104; RISCV-NEXT: .LBB4_10:105; RISCV-NEXT: addi a0, a0, 16106; RISCV-NEXT: .LBB4_11:107; RISCV-NEXT: lh a0, 0(a0)108; RISCV-NEXT: sh a4, 0(a1)109; RISCV-NEXT: sh a3, 2(a1)110; RISCV-NEXT: sh a0, 4(a1)111; RISCV-NEXT: sh a2, 6(a1)112; RISCV-NEXT: ret113 %load = load <4 x half>, ptr %ptr, align 32114 %sel = select <4 x i1> %mask, <4 x half> %x, <4 x half> %load115 store <4 x half> %sel, ptr %ptr, align 32116 ret void117}118 119define void @test_masked_store_success_v4f32(<4 x float> %x, ptr %ptr, <4 x i1> %mask) {120; RISCV-LABEL: test_masked_store_success_v4f32:121; RISCV: # %bb.0:122; RISCV-NEXT: vsetivli zero, 4, e32, m1, ta, ma123; RISCV-NEXT: vse32.v v8, (a0), v0.t124; RISCV-NEXT: ret125 %load = load <4 x float>, ptr %ptr, align 32126 %sel = select <4 x i1> %mask, <4 x float> %x, <4 x float> %load127 store <4 x float> %sel, ptr %ptr, align 32128 ret void129}130 131define void @test_masked_store_success_v4f64(<4 x double> %x, ptr %ptr, <4 x i1> %mask) {132; RISCV-LABEL: test_masked_store_success_v4f64:133; RISCV: # %bb.0:134; RISCV-NEXT: vsetivli zero, 4, e64, m2, ta, ma135; RISCV-NEXT: vse64.v v8, (a0), v0.t136; RISCV-NEXT: ret137 %load = load <4 x double>, ptr %ptr, align 32138 %sel = select <4 x i1> %mask, <4 x double> %x, <4 x double> %load139 store <4 x double> %sel, ptr %ptr, align 32140 ret void141}142 143define void @test_masked_store_success_v8i8(<8 x i8> %x, ptr %ptr, <8 x i1> %mask) {144; RISCV-LABEL: test_masked_store_success_v8i8:145; RISCV: # %bb.0:146; RISCV-NEXT: vsetivli zero, 8, e8, mf2, ta, ma147; RISCV-NEXT: vse8.v v8, (a0), v0.t148; RISCV-NEXT: ret149 %load = load <8 x i8>, ptr %ptr, align 32150 %sel = select <8 x i1> %mask, <8 x i8> %x, <8 x i8> %load151 store <8 x i8> %sel, ptr %ptr, align 32152 ret void153}154 155define void @test_masked_store_success_v8i16(<8 x i16> %x, ptr %ptr, <8 x i1> %mask) {156; RISCV-LABEL: test_masked_store_success_v8i16:157; RISCV: # %bb.0:158; RISCV-NEXT: vsetivli zero, 8, e16, m1, ta, ma159; RISCV-NEXT: vse16.v v8, (a0), v0.t160; RISCV-NEXT: ret161 %load = load <8 x i16>, ptr %ptr, align 32162 %sel = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %load163 store <8 x i16> %sel, ptr %ptr, align 32164 ret void165}166 167define void @test_masked_store_success_v8i32(<8 x i32> %x, ptr %ptr, <8 x i1> %mask) {168; RISCV-LABEL: test_masked_store_success_v8i32:169; RISCV: # %bb.0:170; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma171; RISCV-NEXT: vse32.v v8, (a0), v0.t172; RISCV-NEXT: ret173 %load = load <8 x i32>, ptr %ptr, align 32174 %sel = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %load175 store <8 x i32> %sel, ptr %ptr, align 32176 ret void177}178 179define void @test_masked_store_success_v8i64(<8 x i64> %x, ptr %ptr, <8 x i1> %mask) {180; RISCV-LABEL: test_masked_store_success_v8i64:181; RISCV: # %bb.0:182; RISCV-NEXT: vsetivli zero, 8, e64, m4, ta, ma183; RISCV-NEXT: vse64.v v8, (a0), v0.t184; RISCV-NEXT: ret185 %load = load <8 x i64>, ptr %ptr, align 32186 %sel = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %load187 store <8 x i64> %sel, ptr %ptr, align 32188 ret void189}190 191define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %mask) {192; RISCV-LABEL: test_masked_store_success_v8f16:193; RISCV: # %bb.0:194; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma195; RISCV-NEXT: vmv1r.v v8, v0196; RISCV-NEXT: vfirst.m a3, v0197; RISCV-NEXT: mv a2, a0198; RISCV-NEXT: beqz a3, .LBB11_2199; RISCV-NEXT: # %bb.1:200; RISCV-NEXT: mv a2, a1201; RISCV-NEXT: .LBB11_2:202; RISCV-NEXT: vsetivli zero, 8, e8, mf2, ta, ma203; RISCV-NEXT: vmv.v.i v9, 0204; RISCV-NEXT: vmv1r.v v0, v8205; RISCV-NEXT: vmerge.vim v9, v9, 1, v0206; RISCV-NEXT: vsetivli zero, 4, e8, mf2, ta, ma207; RISCV-NEXT: vslidedown.vi v9, v9, 4208; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma209; RISCV-NEXT: vmsne.vi v11, v9, 0210; RISCV-NEXT: vmv.v.i v10, 0211; RISCV-NEXT: vmv1r.v v0, v11212; RISCV-NEXT: vmerge.vim v9, v10, 1, v0213; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma214; RISCV-NEXT: vslidedown.vi v9, v9, 2215; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma216; RISCV-NEXT: vmsne.vi v9, v9, 0217; RISCV-NEXT: vmv.v.i v12, 0218; RISCV-NEXT: vmv1r.v v0, v9219; RISCV-NEXT: vmerge.vim v13, v12, 1, v0220; RISCV-NEXT: vslidedown.vi v13, v13, 1221; RISCV-NEXT: vmv.x.s a3, v13222; RISCV-NEXT: andi a3, a3, 1223; RISCV-NEXT: bnez a3, .LBB11_4224; RISCV-NEXT: # %bb.3:225; RISCV-NEXT: addi a3, a1, 14226; RISCV-NEXT: j .LBB11_5227; RISCV-NEXT: .LBB11_4:228; RISCV-NEXT: addi a3, a0, 56229; RISCV-NEXT: .LBB11_5:230; RISCV-NEXT: vmv1r.v v0, v8231; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma232; RISCV-NEXT: vmerge.vim v10, v10, 1, v0233; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma234; RISCV-NEXT: vslidedown.vi v10, v10, 2235; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma236; RISCV-NEXT: vmsne.vi v10, v10, 0237; RISCV-NEXT: vmv1r.v v0, v10238; RISCV-NEXT: vmerge.vim v13, v12, 1, v0239; RISCV-NEXT: vslidedown.vi v13, v13, 1240; RISCV-NEXT: vmv.x.s a4, v13241; RISCV-NEXT: andi a4, a4, 1242; RISCV-NEXT: bnez a4, .LBB11_8243; RISCV-NEXT: # %bb.6:244; RISCV-NEXT: addi a4, a1, 6245; RISCV-NEXT: vfirst.m a5, v11246; RISCV-NEXT: bnez a5, .LBB11_9247; RISCV-NEXT: .LBB11_7:248; RISCV-NEXT: addi a5, a0, 32249; RISCV-NEXT: j .LBB11_10250; RISCV-NEXT: .LBB11_8:251; RISCV-NEXT: addi a4, a0, 24252; RISCV-NEXT: vfirst.m a5, v11253; RISCV-NEXT: beqz a5, .LBB11_7254; RISCV-NEXT: .LBB11_9:255; RISCV-NEXT: addi a5, a1, 8256; RISCV-NEXT: .LBB11_10:257; RISCV-NEXT: vmv1r.v v0, v11258; RISCV-NEXT: vmerge.vim v11, v12, 1, v0259; RISCV-NEXT: vslidedown.vi v11, v11, 1260; RISCV-NEXT: vmv.x.s a6, v11261; RISCV-NEXT: andi a6, a6, 1262; RISCV-NEXT: bnez a6, .LBB11_14263; RISCV-NEXT: # %bb.11:264; RISCV-NEXT: addi a6, a1, 10265; RISCV-NEXT: vfirst.m a7, v9266; RISCV-NEXT: bnez a7, .LBB11_15267; RISCV-NEXT: .LBB11_12:268; RISCV-NEXT: addi a7, a0, 48269; RISCV-NEXT: vfirst.m t0, v10270; RISCV-NEXT: bnez t0, .LBB11_16271; RISCV-NEXT: .LBB11_13:272; RISCV-NEXT: addi t1, a0, 16273; RISCV-NEXT: j .LBB11_17274; RISCV-NEXT: .LBB11_14:275; RISCV-NEXT: addi a6, a0, 40276; RISCV-NEXT: vfirst.m a7, v9277; RISCV-NEXT: beqz a7, .LBB11_12278; RISCV-NEXT: .LBB11_15:279; RISCV-NEXT: addi a7, a1, 12280; RISCV-NEXT: vfirst.m t0, v10281; RISCV-NEXT: beqz t0, .LBB11_13282; RISCV-NEXT: .LBB11_16:283; RISCV-NEXT: addi t1, a1, 4284; RISCV-NEXT: .LBB11_17:285; RISCV-NEXT: vmv1r.v v0, v8286; RISCV-NEXT: lh t0, 0(a2)287; RISCV-NEXT: lh a2, 0(a3)288; RISCV-NEXT: lh a3, 0(a4)289; RISCV-NEXT: lh a4, 0(a5)290; RISCV-NEXT: lh a5, 0(a6)291; RISCV-NEXT: lh a6, 0(a7)292; RISCV-NEXT: lh a7, 0(t1)293; RISCV-NEXT: vmerge.vim v8, v12, 1, v0294; RISCV-NEXT: vslidedown.vi v8, v8, 1295; RISCV-NEXT: vmv.x.s t1, v8296; RISCV-NEXT: andi t1, t1, 1297; RISCV-NEXT: bnez t1, .LBB11_19298; RISCV-NEXT: # %bb.18:299; RISCV-NEXT: addi a0, a1, 2300; RISCV-NEXT: j .LBB11_20301; RISCV-NEXT: .LBB11_19:302; RISCV-NEXT: addi a0, a0, 8303; RISCV-NEXT: .LBB11_20:304; RISCV-NEXT: lh a0, 0(a0)305; RISCV-NEXT: sh t0, 0(a1)306; RISCV-NEXT: sh a0, 2(a1)307; RISCV-NEXT: sh a7, 4(a1)308; RISCV-NEXT: sh a3, 6(a1)309; RISCV-NEXT: sh a4, 8(a1)310; RISCV-NEXT: sh a5, 10(a1)311; RISCV-NEXT: sh a6, 12(a1)312; RISCV-NEXT: sh a2, 14(a1)313; RISCV-NEXT: ret314 %load = load <8 x half>, ptr %ptr, align 32315 %sel = select <8 x i1> %mask, <8 x half> %x, <8 x half> %load316 store <8 x half> %sel, ptr %ptr, align 32317 ret void318}319 320define void @test_masked_store_success_v8f32(<8 x float> %x, ptr %ptr, <8 x i1> %mask) {321; RISCV-LABEL: test_masked_store_success_v8f32:322; RISCV: # %bb.0:323; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma324; RISCV-NEXT: vse32.v v8, (a0), v0.t325; RISCV-NEXT: ret326 %load = load <8 x float>, ptr %ptr, align 32327 %sel = select <8 x i1> %mask, <8 x float> %x, <8 x float> %load328 store <8 x float> %sel, ptr %ptr, align 32329 ret void330}331 332define void @test_masked_store_success_v8f64(<8 x double> %x, ptr %ptr, <8 x i1> %mask) {333; RISCV-LABEL: test_masked_store_success_v8f64:334; RISCV: # %bb.0:335; RISCV-NEXT: vsetivli zero, 8, e64, m4, ta, ma336; RISCV-NEXT: vse64.v v8, (a0), v0.t337; RISCV-NEXT: ret338 %load = load <8 x double>, ptr %ptr, align 32339 %sel = select <8 x i1> %mask, <8 x double> %x, <8 x double> %load340 store <8 x double> %sel, ptr %ptr, align 32341 ret void342}343 344define void @test_masked_store_success_v16i8(<16 x i8> %x, ptr %ptr, <16 x i1> %mask) {345; RISCV-LABEL: test_masked_store_success_v16i8:346; RISCV: # %bb.0:347; RISCV-NEXT: vsetivli zero, 16, e8, m1, ta, ma348; RISCV-NEXT: vse8.v v8, (a0), v0.t349; RISCV-NEXT: ret350 %load = load <16 x i8>, ptr %ptr, align 32351 %sel = select <16 x i1> %mask, <16 x i8> %x, <16 x i8> %load352 store <16 x i8> %sel, ptr %ptr, align 32353 ret void354}355 356define void @test_masked_store_success_v16i16(<16 x i16> %x, ptr %ptr, <16 x i1> %mask) {357; RISCV-LABEL: test_masked_store_success_v16i16:358; RISCV: # %bb.0:359; RISCV-NEXT: vsetivli zero, 16, e16, m2, ta, ma360; RISCV-NEXT: vse16.v v8, (a0), v0.t361; RISCV-NEXT: ret362 %load = load <16 x i16>, ptr %ptr, align 32363 %sel = select <16 x i1> %mask, <16 x i16> %x, <16 x i16> %load364 store <16 x i16> %sel, ptr %ptr, align 32365 ret void366}367 368define void @test_masked_store_success_v16i32(<16 x i32> %x, ptr %ptr, <16 x i1> %mask) {369; RISCV-LABEL: test_masked_store_success_v16i32:370; RISCV: # %bb.0:371; RISCV-NEXT: vsetivli zero, 16, e32, m4, ta, ma372; RISCV-NEXT: vse32.v v8, (a0), v0.t373; RISCV-NEXT: ret374 %load = load <16 x i32>, ptr %ptr, align 32375 %sel = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %load376 store <16 x i32> %sel, ptr %ptr, align 32377 ret void378}379 380define void @test_masked_store_success_v32i8(<32 x i8> %x, ptr %ptr, <32 x i1> %mask) {381; RISCV-LABEL: test_masked_store_success_v32i8:382; RISCV: # %bb.0:383; RISCV-NEXT: li a1, 32384; RISCV-NEXT: vsetvli zero, a1, e8, m2, ta, ma385; RISCV-NEXT: vse8.v v8, (a0), v0.t386; RISCV-NEXT: ret387 %load = load <32 x i8>, ptr %ptr, align 32388 %sel = select <32 x i1> %mask, <32 x i8> %x, <32 x i8> %load389 store <32 x i8> %sel, ptr %ptr, align 32390 ret void391}392 393define void @test_masked_store_success_v32i16(<32 x i16> %x, ptr %ptr, <32 x i1> %mask) {394; RISCV-LABEL: test_masked_store_success_v32i16:395; RISCV: # %bb.0:396; RISCV-NEXT: li a1, 32397; RISCV-NEXT: vsetvli zero, a1, e16, m4, ta, ma398; RISCV-NEXT: vse16.v v8, (a0), v0.t399; RISCV-NEXT: ret400 %load = load <32 x i16>, ptr %ptr, align 32401 %sel = select <32 x i1> %mask, <32 x i16> %x, <32 x i16> %load402 store <32 x i16> %sel, ptr %ptr, align 32403 ret void404}405 406define void @test_masked_store_success_v64i8(<64 x i8> %x, ptr %ptr, <64 x i1> %mask) {407; RISCV-LABEL: test_masked_store_success_v64i8:408; RISCV: # %bb.0:409; RISCV-NEXT: li a1, 64410; RISCV-NEXT: vsetvli zero, a1, e8, m4, ta, ma411; RISCV-NEXT: vse8.v v8, (a0), v0.t412; RISCV-NEXT: ret413 %load = load <64 x i8>, ptr %ptr, align 32414 %sel = select <64 x i1> %mask, <64 x i8> %x, <64 x i8> %load415 store <64 x i8> %sel, ptr %ptr, align 32416 ret void417}418 419define void @test_masked_store_success_invert_mask_v4i32(<4 x i32> %x, ptr %ptr, <4 x i1> %mask) {420; RISCV-LABEL: test_masked_store_success_invert_mask_v4i32:421; RISCV: # %bb.0:422; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma423; RISCV-NEXT: vmnot.m v0, v0424; RISCV-NEXT: vse32.v v8, (a0), v0.t425; RISCV-NEXT: ret426 %load = load <4 x i32>, ptr %ptr, align 32427 %sel = select <4 x i1> %mask, <4 x i32> %load, <4 x i32> %x428 store <4 x i32> %sel, ptr %ptr, align 32429 ret void430}431 432define void @test_masked_store_success_invert_mask_v8i32(<8 x i32> %x, ptr %ptr, <8 x i1> %mask) {433; RISCV-LABEL: test_masked_store_success_invert_mask_v8i32:434; RISCV: # %bb.0:435; RISCV-NEXT: vsetivli zero, 8, e8, mf2, ta, ma436; RISCV-NEXT: vmnot.m v0, v0437; RISCV-NEXT: vse32.v v8, (a0), v0.t438; RISCV-NEXT: ret439 %load = load <8 x i32>, ptr %ptr, align 32440 %sel = select <8 x i1> %mask, <8 x i32> %load, <8 x i32> %x441 store <8 x i32> %sel, ptr %ptr, align 32442 ret void443}444 445define void @test_masked_store_success_invert_mask_v16i32(<16 x i32> %x, ptr %ptr, <16 x i1> %mask) {446; RISCV-LABEL: test_masked_store_success_invert_mask_v16i32:447; RISCV: # %bb.0:448; RISCV-NEXT: vsetivli zero, 16, e8, m1, ta, ma449; RISCV-NEXT: vmnot.m v0, v0450; RISCV-NEXT: vse32.v v8, (a0), v0.t451; RISCV-NEXT: ret452 %load = load <16 x i32>, ptr %ptr, align 32453 %sel = select <16 x i1> %mask, <16 x i32> %load, <16 x i32> %x454 store <16 x i32> %sel, ptr %ptr, align 32455 ret void456}457 458define void @test_masked_store_zextload(<4 x i64> %x, ptr %ptr, <4 x i1> %mask) {459; RISCV-LABEL: test_masked_store_zextload:460; RISCV: # %bb.0:461; RISCV-NEXT: vsetivli zero, 4, e64, m2, ta, ma462; RISCV-NEXT: vle32.v v12, (a0)463; RISCV-NEXT: vzext.vf2 v10, v12464; RISCV-NEXT: vmerge.vvm v8, v10, v8, v0465; RISCV-NEXT: vse64.v v8, (a0)466; RISCV-NEXT: ret467 %load = load <4 x i32>, ptr %ptr, align 32468 %zext = zext <4 x i32> %load to <4 x i64>469 %masked = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %zext470 store <4 x i64> %masked, ptr %ptr, align 32471 ret void472}473 474define void @test_masked_store_volatile_load(<8 x i32> %x, ptr %ptr, <8 x i1> %mask) {475; RISCV-LABEL: test_masked_store_volatile_load:476; RISCV: # %bb.0:477; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma478; RISCV-NEXT: vle32.v v10, (a0)479; RISCV-NEXT: vmerge.vvm v8, v10, v8, v0480; RISCV-NEXT: vse32.v v8, (a0)481; RISCV-NEXT: ret482 %load = load volatile <8 x i32>, ptr %ptr, align 32483 %sel = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %load484 store <8 x i32> %sel, ptr %ptr, align 32485 ret void486}487 488define void @test_masked_store_volatile_store(<8 x i32> %x, ptr %ptr, <8 x i1> %mask) {489; RISCV-LABEL: test_masked_store_volatile_store:490; RISCV: # %bb.0:491; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma492; RISCV-NEXT: vle32.v v10, (a0)493; RISCV-NEXT: vmerge.vvm v8, v10, v8, v0494; RISCV-NEXT: vse32.v v8, (a0)495; RISCV-NEXT: ret496 %load = load <8 x i32>, ptr %ptr, align 32497 %sel = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %load498 store volatile <8 x i32> %sel, ptr %ptr, align 32499 ret void500}501 502declare void @use_vec(<8 x i32>)503 504define void @test_masked_store_intervening(<8 x i32> %x, ptr %ptr, <8 x i1> %mask) nounwind {505; RISCV-LABEL: test_masked_store_intervening:506; RISCV: # %bb.0:507; RISCV-NEXT: addi sp, sp, -32508; RISCV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill509; RISCV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill510; RISCV-NEXT: csrr a1, vlenb511; RISCV-NEXT: slli a2, a1, 2512; RISCV-NEXT: add a1, a2, a1513; RISCV-NEXT: sub sp, sp, a1514; RISCV-NEXT: csrr a1, vlenb515; RISCV-NEXT: slli a1, a1, 2516; RISCV-NEXT: add a1, sp, a1517; RISCV-NEXT: addi a1, a1, 16518; RISCV-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill519; RISCV-NEXT: mv s0, a0520; RISCV-NEXT: csrr a1, vlenb521; RISCV-NEXT: slli a1, a1, 1522; RISCV-NEXT: add a1, sp, a1523; RISCV-NEXT: addi a1, a1, 16524; RISCV-NEXT: vs2r.v v8, (a1) # vscale x 16-byte Folded Spill525; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma526; RISCV-NEXT: vle32.v v8, (a0)527; RISCV-NEXT: addi a1, sp, 16528; RISCV-NEXT: vs2r.v v8, (a1) # vscale x 16-byte Folded Spill529; RISCV-NEXT: vmv.v.i v8, 0530; RISCV-NEXT: vse32.v v8, (a0)531; RISCV-NEXT: call use_vec532; RISCV-NEXT: csrr a0, vlenb533; RISCV-NEXT: slli a0, a0, 2534; RISCV-NEXT: add a0, sp, a0535; RISCV-NEXT: addi a0, a0, 16536; RISCV-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload537; RISCV-NEXT: csrr a0, vlenb538; RISCV-NEXT: slli a0, a0, 1539; RISCV-NEXT: add a0, sp, a0540; RISCV-NEXT: addi a0, a0, 16541; RISCV-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload542; RISCV-NEXT: addi a0, sp, 16543; RISCV-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload544; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma545; RISCV-NEXT: vmerge.vvm v8, v10, v8, v0546; RISCV-NEXT: vse32.v v8, (s0)547; RISCV-NEXT: csrr a0, vlenb548; RISCV-NEXT: slli a1, a0, 2549; RISCV-NEXT: add a0, a1, a0550; RISCV-NEXT: add sp, sp, a0551; RISCV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload552; RISCV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload553; RISCV-NEXT: addi sp, sp, 32554; RISCV-NEXT: ret555 %load = load <8 x i32>, ptr %ptr, align 32556 store <8 x i32> zeroinitializer, ptr %ptr, align 32557 %tmp = load <8 x i32>, ptr %ptr558 call void @use_vec(<8 x i32> %tmp)559 %sel = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %load560 store <8 x i32> %sel, ptr %ptr, align 32561 ret void562}563 564 565define void @test_masked_store_multiple_v8i32(<8 x i32> %x, <8 x i32> %y, ptr %ptr1, ptr %ptr2, <8 x i1> %mask, <8 x i1> %mask2) {566; RISCV-LABEL: test_masked_store_multiple_v8i32:567; RISCV: # %bb.0:568; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma569; RISCV-NEXT: vmv1r.v v13, v0570; RISCV-NEXT: vle32.v v14, (a1)571; RISCV-NEXT: vmv1r.v v0, v12572; RISCV-NEXT: vmerge.vvm v10, v14, v10, v0573; RISCV-NEXT: vmv1r.v v0, v13574; RISCV-NEXT: vse32.v v8, (a0), v0.t575; RISCV-NEXT: vse32.v v10, (a1)576; RISCV-NEXT: ret577 %load = load <8 x i32>, ptr %ptr1, align 32578 %load2 = load <8 x i32>, ptr %ptr2, align 32579 %sel = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %load580 %sel2 = select <8 x i1> %mask2, <8 x i32> %y, <8 x i32> %load2581 store <8 x i32> %sel, ptr %ptr1, align 32582 store <8 x i32> %sel2, ptr %ptr2, align 32583 ret void584}585 586define void @test_masked_store_multiple_v8i64(<8 x i64> %x, <8 x i64> %y, ptr %ptr1, ptr %ptr2, <8 x i1> %mask, <8 x i1> %mask2) {587; RISCV-LABEL: test_masked_store_multiple_v8i64:588; RISCV: # %bb.0:589; RISCV-NEXT: vsetivli zero, 8, e64, m4, ta, ma590; RISCV-NEXT: vmv1r.v v17, v0591; RISCV-NEXT: vle64.v v20, (a1)592; RISCV-NEXT: vmv1r.v v0, v16593; RISCV-NEXT: vmerge.vvm v12, v20, v12, v0594; RISCV-NEXT: vmv1r.v v0, v17595; RISCV-NEXT: vse64.v v8, (a0), v0.t596; RISCV-NEXT: vse64.v v12, (a1)597; RISCV-NEXT: ret598 %load = load <8 x i64>, ptr %ptr1, align 32599 %load2 = load <8 x i64>, ptr %ptr2, align 32600 %sel = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %load601 %sel2 = select <8 x i1> %mask2, <8 x i64> %y, <8 x i64> %load2602 store <8 x i64> %sel, ptr %ptr1, align 32603 store <8 x i64> %sel2, ptr %ptr2, align 32604 ret void605}606 607define void @test_masked_store_unaligned_v4i32(<4 x i32> %data, ptr %ptr, <4 x i1> %mask) {608; RISCV-LABEL: test_masked_store_unaligned_v4i32:609; RISCV: # %bb.0:610; RISCV-NEXT: addi a0, a0, 1611; RISCV-NEXT: vsetivli zero, 16, e8, m1, ta, ma612; RISCV-NEXT: vle8.v v9, (a0)613; RISCV-NEXT: vsetivli zero, 4, e32, m1, ta, ma614; RISCV-NEXT: vmerge.vvm v8, v9, v8, v0615; RISCV-NEXT: vsetivli zero, 16, e8, m1, ta, ma616; RISCV-NEXT: vse8.v v8, (a0)617; RISCV-NEXT: ret618 %ptr_i8 = getelementptr i8, ptr %ptr, i32 1619 %ptr_vec = bitcast ptr %ptr_i8 to ptr620 %load = load <4 x i32>, ptr %ptr_vec, align 1621 %sel = select <4 x i1> %mask, <4 x i32> %data, <4 x i32> %load622 store <4 x i32> %sel, ptr %ptr_vec, align 1623 ret void624}625 626define void @test_masked_store_unaligned_v4i64(<4 x i64> %data, ptr %ptr, <4 x i1> %mask) {627; RISCV-LABEL: test_masked_store_unaligned_v4i64:628; RISCV: # %bb.0:629; RISCV-NEXT: addi a0, a0, 1630; RISCV-NEXT: li a1, 32631; RISCV-NEXT: vsetvli zero, a1, e8, m2, ta, ma632; RISCV-NEXT: vle8.v v10, (a0)633; RISCV-NEXT: vsetivli zero, 4, e64, m2, ta, ma634; RISCV-NEXT: vmerge.vvm v8, v10, v8, v0635; RISCV-NEXT: vsetvli zero, a1, e8, m2, ta, ma636; RISCV-NEXT: vse8.v v8, (a0)637; RISCV-NEXT: ret638 %ptr_i8 = getelementptr i8, ptr %ptr, i64 1639 %ptr_vec = bitcast ptr %ptr_i8 to ptr640 %load = load <4 x i64>, ptr %ptr_vec, align 1641 %sel = select <4 x i1> %mask, <4 x i64> %data, <4 x i64> %load642 store <4 x i64> %sel, ptr %ptr_vec, align 1643 ret void644}645 646define void @test_masked_store_unaligned_v8i32(<8 x i32> %data, ptr %ptr, <8 x i1> %mask) {647; RISCV-LABEL: test_masked_store_unaligned_v8i32:648; RISCV: # %bb.0:649; RISCV-NEXT: addi a0, a0, 1650; RISCV-NEXT: li a1, 32651; RISCV-NEXT: vsetvli zero, a1, e8, m2, ta, ma652; RISCV-NEXT: vle8.v v10, (a0)653; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma654; RISCV-NEXT: vmerge.vvm v8, v10, v8, v0655; RISCV-NEXT: vsetvli zero, a1, e8, m2, ta, ma656; RISCV-NEXT: vse8.v v8, (a0)657; RISCV-NEXT: ret658 %ptr_i8 = getelementptr i8, ptr %ptr, i32 1659 %ptr_vec = bitcast ptr %ptr_i8 to ptr660 %load = load <8 x i32>, ptr %ptr_vec, align 1661 %sel = select <8 x i1> %mask, <8 x i32> %data, <8 x i32> %load662 store <8 x i32> %sel, ptr %ptr_vec, align 1663 ret void664}665 666define void @test_masked_store_unaligned_v8i64(<8 x i64> %data, ptr %ptr, <8 x i1> %mask) {667; RISCV-LABEL: test_masked_store_unaligned_v8i64:668; RISCV: # %bb.0:669; RISCV-NEXT: addi a0, a0, 1670; RISCV-NEXT: li a1, 64671; RISCV-NEXT: vsetvli zero, a1, e8, m4, ta, ma672; RISCV-NEXT: vle8.v v12, (a0)673; RISCV-NEXT: vsetivli zero, 8, e64, m4, ta, ma674; RISCV-NEXT: vmerge.vvm v8, v12, v8, v0675; RISCV-NEXT: vsetvli zero, a1, e8, m4, ta, ma676; RISCV-NEXT: vse8.v v8, (a0)677; RISCV-NEXT: ret678 %ptr_i8 = getelementptr i8, ptr %ptr, i64 1679 %ptr_vec = bitcast ptr %ptr_i8 to ptr680 %load = load <8 x i64>, ptr %ptr_vec, align 1681 %sel = select <8 x i1> %mask, <8 x i64> %data, <8 x i64> %load682 store <8 x i64> %sel, ptr %ptr_vec, align 1683 ret void684}685