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1; This test is designed to run three times, once with function attributes, once2; with all target attributes added on the command line, and once with compress3; added with the command line and float added via function attributes, all4; three of these should result in the same output.5;6; RUN: cat %s > %t.tgtattr7; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr8; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c,+f -filetype=obj \9; RUN:   -disable-block-placement < %t.tgtattr \10; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \11; RUN:   | FileCheck -check-prefix=RV32IFDC %s12;13; RUN: cat %s > %t.fnattr14; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f" }' >> %t.fnattr15; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \16; RUN:   -disable-block-placement < %t.fnattr \17; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \18; RUN:   | FileCheck -check-prefix=RV32IFDC %s19;20; RUN: cat %s > %t.mixedattr21; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr22; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c -filetype=obj \23; RUN:   -disable-block-placement < %t.mixedattr \24; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \25; RUN:   | FileCheck -check-prefix=RV32IFDC %s26;27; RUN: cat %s > %t.tgtattr28; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr29; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf,+f -filetype=obj \30; RUN:   -disable-block-placement < %t.tgtattr \31; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \32; RUN:   | FileCheck -check-prefix=RV32IFDC %s33;34; RUN: cat %s > %t.fnattr35; RUN: echo 'attributes #0 = { nounwind "target-features"="+zcf,+f" }' >> %t.fnattr36; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \37; RUN:   -disable-block-placement < %t.fnattr \38; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \39; RUN:   | FileCheck -check-prefix=RV32IFDC %s40;41; RUN: cat %s > %t.mixedattr42; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr43; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf -filetype=obj \44; RUN:   -disable-block-placement < %t.mixedattr \45; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \46; RUN:   | FileCheck -check-prefix=RV32IFDC %s47;48; RUN: cat %s > %t.tgtattr49; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr50; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce,+f -filetype=obj \51; RUN:   -disable-block-placement < %t.tgtattr \52; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \53; RUN:   | FileCheck -check-prefix=RV32IFDC %s54;55; RUN: cat %s > %t.fnattr56; RUN: echo 'attributes #0 = { nounwind "target-features"="+zce,+f" }' >> %t.fnattr57; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \58; RUN:   -disable-block-placement < %t.fnattr \59; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \60; RUN:   | FileCheck -check-prefix=RV32IFDC %s61;62; RUN: cat %s > %t.mixedattr63; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr64; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce -filetype=obj \65; RUN:   -disable-block-placement < %t.mixedattr \66; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \67; RUN:   | FileCheck -check-prefix=RV32IFDC %s68 69; This acts as a basic correctness check for the codegen instruction compression70; path, verifying that the assembled file contains compressed instructions when71; expected. Handling of the compressed ISA is implemented so the same72; transformation patterns should be used whether compressing an input .s file or73; compressing codegen output. This file contains basic functionality tests using74; instructions which also require one of the floating point extensions.75 76define float @float_load(ptr %a) #0 {77; RV32IFDC-LABEL: <float_load>:78; RV32IFDC:         c.flw fa0, 0x0(a0)79; RV32IFDC-NEXT:    c.jr ra80  %1 = load volatile float, ptr %a81  ret float %182}83