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1; This test is designed to run twice, once with function attributes and once2; with target attributes added on the command line.3;4; RUN: cat %s > %t.tgtattr5; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr6; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj \7; RUN: -disable-block-placement < %t.tgtattr \8; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \9; RUN: | FileCheck -check-prefix=RV32IC %s10;11; RUN: cat %s > %t.fnattr12; RUN: echo 'attributes #0 = { nounwind "target-features"="+c" }' >> %t.fnattr13; RUN: llc -mtriple=riscv32 -filetype=obj \14; RUN: -disable-block-placement < %t.fnattr \15; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \16; RUN: | FileCheck -check-prefix=RV32IC %s17 18; This acts as a basic correctness check for the codegen instruction compression19; path, verifying that the assembled file contains compressed instructions when20; expected. Handling of the compressed ISA is implemented so the same21; transformation patterns should be used whether compressing an input .s file or22; compressing codegen output. This file contains basic functionality checks to23; ensure that is working as expected. Particular care should be taken to test24; pseudo instructions.25 26; Note: TODOs in this file are only appropriate if they highlight a case where27; a generated instruction that can be compressed by an existing pattern isn't.28; It may be useful to have tests that indicate where better compression would be29; possible if alternative codegen choices were made, but they belong in a30; different test file.31 32define i32 @simple_arith(i32 %a, i32 %b) #0 {33; RV32IC-LABEL: <simple_arith>:34; RV32IC: addi a2, a0, 0x135; RV32IC-NEXT: c.srai a1, 0x936; RV32IC-NEXT: c.andi a2, 0xb37; RV32IC-NEXT: c.slli a2, 0x738; RV32IC-NEXT: sub a0, a1, a039; RV32IC-NEXT: c.add a0, a240; RV32IC-NEXT: c.jr ra41 %1 = add i32 %a, 142 %2 = and i32 %1, 1143 %3 = shl i32 %2, 744 %4 = ashr i32 %b, 945 %5 = add i32 %3, %446 %6 = sub i32 %5, %a47 ret i32 %648}49 50define i32 @select(i32 %a, ptr %b) #0 {51; RV32IC-LABEL: <select>:52; RV32IC: c.lw a2, 0x0(a1)53; RV32IC-NEXT: c.beqz a2, 0x1854; RV32IC-NEXT: c.mv a0, a255; RV32IC-NEXT: c.lw a2, 0x0(a1)56; RV32IC-NEXT: c.bnez a2, 0x1e57; RV32IC-NEXT: c.mv a0, a258; RV32IC-NEXT: c.lw a2, 0x0(a1)59; RV32IC-NEXT: bltu a2, a0, 0x2660; RV32IC-NEXT: c.mv a0, a261; RV32IC-NEXT: c.lw a2, 0x0(a1)62; RV32IC-NEXT: bgeu a0, a2, 0x2e63; RV32IC-NEXT: c.mv a0, a264; RV32IC-NEXT: c.lw a2, 0x0(a1)65; RV32IC-NEXT: bltu a0, a2, 0x3666; RV32IC-NEXT: c.mv a0, a267; RV32IC-NEXT: c.lw a2, 0x0(a1)68; RV32IC-NEXT: bgeu a2, a0, 0x3e69; RV32IC-NEXT: c.mv a0, a270; RV32IC-NEXT: c.lw a2, 0x0(a1)71; RV32IC-NEXT: blt a2, a0, 0x4672; RV32IC-NEXT: c.mv a0, a273; RV32IC-NEXT: c.lw a2, 0x0(a1)74; RV32IC-NEXT: bge a0, a2, 0x4e75; RV32IC-NEXT: c.mv a0, a276; RV32IC-NEXT: c.lw a2, 0x0(a1)77; RV32IC-NEXT: blt a0, a2, 0x5678; RV32IC-NEXT: c.mv a0, a279; RV32IC-NEXT: c.lw a1, 0x0(a1)80; RV32IC-NEXT: bge a1, a0, 0x5e81; RV32IC-NEXT: c.mv a0, a182; RV32IC-NEXT: c.jr ra83 %val1 = load volatile i32, ptr %b84 %tst1 = icmp eq i32 0, %val185 %val2 = select i1 %tst1, i32 %a, i32 %val186 87 %val3 = load volatile i32, ptr %b88 %tst2 = icmp ne i32 0, %val389 %val4 = select i1 %tst2, i32 %val2, i32 %val390 91 %val5 = load volatile i32, ptr %b92 %tst3 = icmp ugt i32 %val4, %val593 %val6 = select i1 %tst3, i32 %val4, i32 %val594 95 %val7 = load volatile i32, ptr %b96 %tst4 = icmp uge i32 %val6, %val797 %val8 = select i1 %tst4, i32 %val6, i32 %val798 99 %val9 = load volatile i32, ptr %b100 %tst5 = icmp ult i32 %val8, %val9101 %val10 = select i1 %tst5, i32 %val8, i32 %val9102 103 %val11 = load volatile i32, ptr %b104 %tst6 = icmp ule i32 %val10, %val11105 %val12 = select i1 %tst6, i32 %val10, i32 %val11106 107 %val13 = load volatile i32, ptr %b108 %tst7 = icmp sgt i32 %val12, %val13109 %val14 = select i1 %tst7, i32 %val12, i32 %val13110 111 %val15 = load volatile i32, ptr %b112 %tst8 = icmp sge i32 %val14, %val15113 %val16 = select i1 %tst8, i32 %val14, i32 %val15114 115 %val17 = load volatile i32, ptr %b116 %tst9 = icmp slt i32 %val16, %val17117 %val18 = select i1 %tst9, i32 %val16, i32 %val17118 119 %val19 = load volatile i32, ptr %b120 %tst10 = icmp sle i32 %val18, %val19121 %val20 = select i1 %tst10, i32 %val18, i32 %val19122 123 ret i32 %val20124}125 126define i32 @pos_tiny() #0 {127; RV32IC-LABEL: <pos_tiny>:128; RV32IC: c.li a0, 0x12129; RV32IC-NEXT: c.jr ra130 ret i32 18131}132 133define i32 @pos_i32() #0 {134; RV32IC-LABEL: <pos_i32>:135; RV32IC: lui a0, 0x67783136; RV32IC-NEXT: addi a0, a0, -0x511137; RV32IC-NEXT: c.jr ra138 ret i32 1735928559139}140 141define i32 @pos_i32_half_compressible() #0 {142; RV32IC-LABEL: <pos_i32_half_compressible>:143; RV32IC: lui a0, 0x67782144; RV32IC-NEXT: c.addi a0, 0x1c145; RV32IC-NEXT: c.jr ra146 ret i32 1735925788147}148 149define i32 @neg_tiny() #0 {150; RV32IC-LABEL: <neg_tiny>:151; RV32IC: c.li a0, -0x13152; RV32IC-NEXT: c.jr ra153 ret i32 -19154}155 156define i32 @neg_i32() #0 {157; RV32IC-LABEL: <neg_i32>:158; RV32IC: lui a0, 0xdeadc159; RV32IC-NEXT: addi a0, a0, -0x111160; RV32IC-NEXT: c.jr ra161 ret i32 -559038737162}163 164define i32 @pos_i32_hi20_only() #0 {165; RV32IC-LABEL: <pos_i32_hi20_only>:166; RV32IC: c.lui a0, 0x10167; RV32IC-NEXT: c.jr ra168 ret i32 65536169}170 171define i32 @neg_i32_hi20_only() #0 {172; RV32IC-LABEL: <neg_i32_hi20_only>:173; RV32IC: c.lui a0, 0xffff0174; RV32IC-NEXT: c.jr ra175 ret i32 -65536176}177