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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I3; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I4; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS5; RUN: llc -mtriple=riscv64 -mattr=+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV6; RUN: llc -mtriple=riscv32 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND7; RUN: llc -mtriple=riscv64 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND8 9define i32 @shl32(i32 %x, i32 %y, i1 %c) {10; RV32I-LABEL: shl32:11; RV32I: # %bb.0:12; RV32I-NEXT: slli a2, a2, 3113; RV32I-NEXT: srai a2, a2, 3114; RV32I-NEXT: and a1, a2, a115; RV32I-NEXT: sll a0, a0, a116; RV32I-NEXT: ret17;18; RV64I-LABEL: shl32:19; RV64I: # %bb.0:20; RV64I-NEXT: slli a2, a2, 6321; RV64I-NEXT: srai a2, a2, 6322; RV64I-NEXT: and a1, a2, a123; RV64I-NEXT: sllw a0, a0, a124; RV64I-NEXT: ret25;26; RV64XVENTANACONDOPS-LABEL: shl32:27; RV64XVENTANACONDOPS: # %bb.0:28; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 129; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a230; RV64XVENTANACONDOPS-NEXT: sllw a0, a0, a131; RV64XVENTANACONDOPS-NEXT: ret32;33; RV64XTHEADCONDMOV-LABEL: shl32:34; RV64XTHEADCONDMOV: # %bb.0:35; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 136; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a237; RV64XTHEADCONDMOV-NEXT: sllw a0, a0, a138; RV64XTHEADCONDMOV-NEXT: ret39;40; RV32ZICOND-LABEL: shl32:41; RV32ZICOND: # %bb.0:42; RV32ZICOND-NEXT: andi a2, a2, 143; RV32ZICOND-NEXT: czero.eqz a1, a1, a244; RV32ZICOND-NEXT: sll a0, a0, a145; RV32ZICOND-NEXT: ret46;47; RV64ZICOND-LABEL: shl32:48; RV64ZICOND: # %bb.0:49; RV64ZICOND-NEXT: andi a2, a2, 150; RV64ZICOND-NEXT: czero.eqz a1, a1, a251; RV64ZICOND-NEXT: sllw a0, a0, a152; RV64ZICOND-NEXT: ret53 %binop = shl i32 %x, %y54 %select_ = select i1 %c, i32 %binop, i32 %x55 ret i32 %select_56}57 58define i32 @ashr32(i32 %x, i32 %y, i1 %c) {59; RV32I-LABEL: ashr32:60; RV32I: # %bb.0:61; RV32I-NEXT: slli a2, a2, 3162; RV32I-NEXT: srai a2, a2, 3163; RV32I-NEXT: and a1, a2, a164; RV32I-NEXT: sra a0, a0, a165; RV32I-NEXT: ret66;67; RV64I-LABEL: ashr32:68; RV64I: # %bb.0:69; RV64I-NEXT: slli a2, a2, 6370; RV64I-NEXT: srai a2, a2, 6371; RV64I-NEXT: and a1, a2, a172; RV64I-NEXT: sraw a0, a0, a173; RV64I-NEXT: ret74;75; RV64XVENTANACONDOPS-LABEL: ashr32:76; RV64XVENTANACONDOPS: # %bb.0:77; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 178; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a279; RV64XVENTANACONDOPS-NEXT: sraw a0, a0, a180; RV64XVENTANACONDOPS-NEXT: ret81;82; RV64XTHEADCONDMOV-LABEL: ashr32:83; RV64XTHEADCONDMOV: # %bb.0:84; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 185; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a286; RV64XTHEADCONDMOV-NEXT: sraw a0, a0, a187; RV64XTHEADCONDMOV-NEXT: ret88;89; RV32ZICOND-LABEL: ashr32:90; RV32ZICOND: # %bb.0:91; RV32ZICOND-NEXT: andi a2, a2, 192; RV32ZICOND-NEXT: czero.eqz a1, a1, a293; RV32ZICOND-NEXT: sra a0, a0, a194; RV32ZICOND-NEXT: ret95;96; RV64ZICOND-LABEL: ashr32:97; RV64ZICOND: # %bb.0:98; RV64ZICOND-NEXT: andi a2, a2, 199; RV64ZICOND-NEXT: czero.eqz a1, a1, a2100; RV64ZICOND-NEXT: sraw a0, a0, a1101; RV64ZICOND-NEXT: ret102 %binop = ashr i32 %x, %y103 %select_ = select i1 %c, i32 %binop, i32 %x104 ret i32 %select_105}106 107define i32 @lshr32(i32 %x, i32 %y, i1 %c) {108; RV32I-LABEL: lshr32:109; RV32I: # %bb.0:110; RV32I-NEXT: slli a2, a2, 31111; RV32I-NEXT: srai a2, a2, 31112; RV32I-NEXT: and a1, a2, a1113; RV32I-NEXT: srl a0, a0, a1114; RV32I-NEXT: ret115;116; RV64I-LABEL: lshr32:117; RV64I: # %bb.0:118; RV64I-NEXT: slli a2, a2, 63119; RV64I-NEXT: srai a2, a2, 63120; RV64I-NEXT: and a1, a2, a1121; RV64I-NEXT: srlw a0, a0, a1122; RV64I-NEXT: ret123;124; RV64XVENTANACONDOPS-LABEL: lshr32:125; RV64XVENTANACONDOPS: # %bb.0:126; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1127; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2128; RV64XVENTANACONDOPS-NEXT: srlw a0, a0, a1129; RV64XVENTANACONDOPS-NEXT: ret130;131; RV64XTHEADCONDMOV-LABEL: lshr32:132; RV64XTHEADCONDMOV: # %bb.0:133; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1134; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2135; RV64XTHEADCONDMOV-NEXT: srlw a0, a0, a1136; RV64XTHEADCONDMOV-NEXT: ret137;138; RV32ZICOND-LABEL: lshr32:139; RV32ZICOND: # %bb.0:140; RV32ZICOND-NEXT: andi a2, a2, 1141; RV32ZICOND-NEXT: czero.eqz a1, a1, a2142; RV32ZICOND-NEXT: srl a0, a0, a1143; RV32ZICOND-NEXT: ret144;145; RV64ZICOND-LABEL: lshr32:146; RV64ZICOND: # %bb.0:147; RV64ZICOND-NEXT: andi a2, a2, 1148; RV64ZICOND-NEXT: czero.eqz a1, a1, a2149; RV64ZICOND-NEXT: srlw a0, a0, a1150; RV64ZICOND-NEXT: ret151 %binop = lshr i32 %x, %y152 %select_ = select i1 %c, i32 %binop, i32 %x153 ret i32 %select_154}155 156define i32 @sub32(i32 %x, i32 %y, i1 %c) {157; RV32I-LABEL: sub32:158; RV32I: # %bb.0:159; RV32I-NEXT: slli a2, a2, 31160; RV32I-NEXT: srai a2, a2, 31161; RV32I-NEXT: and a1, a2, a1162; RV32I-NEXT: sub a0, a0, a1163; RV32I-NEXT: ret164;165; RV64I-LABEL: sub32:166; RV64I: # %bb.0:167; RV64I-NEXT: slli a2, a2, 63168; RV64I-NEXT: srai a2, a2, 63169; RV64I-NEXT: and a1, a2, a1170; RV64I-NEXT: subw a0, a0, a1171; RV64I-NEXT: ret172;173; RV64XVENTANACONDOPS-LABEL: sub32:174; RV64XVENTANACONDOPS: # %bb.0:175; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1176; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2177; RV64XVENTANACONDOPS-NEXT: subw a0, a0, a1178; RV64XVENTANACONDOPS-NEXT: ret179;180; RV64XTHEADCONDMOV-LABEL: sub32:181; RV64XTHEADCONDMOV: # %bb.0:182; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1183; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2184; RV64XTHEADCONDMOV-NEXT: subw a0, a0, a1185; RV64XTHEADCONDMOV-NEXT: ret186;187; RV32ZICOND-LABEL: sub32:188; RV32ZICOND: # %bb.0:189; RV32ZICOND-NEXT: andi a2, a2, 1190; RV32ZICOND-NEXT: czero.eqz a1, a1, a2191; RV32ZICOND-NEXT: sub a0, a0, a1192; RV32ZICOND-NEXT: ret193;194; RV64ZICOND-LABEL: sub32:195; RV64ZICOND: # %bb.0:196; RV64ZICOND-NEXT: andi a2, a2, 1197; RV64ZICOND-NEXT: czero.eqz a1, a1, a2198; RV64ZICOND-NEXT: subw a0, a0, a1199; RV64ZICOND-NEXT: ret200 %binop = sub i32 %x, %y201 %select_ = select i1 %c, i32 %binop, i32 %x202 ret i32 %select_203}204 205define i32 @and32(i32 %x, i32 %y, i1 %c) {206; RV32I-LABEL: and32:207; RV32I: # %bb.0:208; RV32I-NEXT: andi a2, a2, 1209; RV32I-NEXT: beqz a2, .LBB4_2210; RV32I-NEXT: # %bb.1:211; RV32I-NEXT: and a0, a0, a1212; RV32I-NEXT: .LBB4_2:213; RV32I-NEXT: ret214;215; RV64I-LABEL: and32:216; RV64I: # %bb.0:217; RV64I-NEXT: andi a2, a2, 1218; RV64I-NEXT: beqz a2, .LBB4_2219; RV64I-NEXT: # %bb.1:220; RV64I-NEXT: and a0, a0, a1221; RV64I-NEXT: .LBB4_2:222; RV64I-NEXT: ret223;224; RV64XVENTANACONDOPS-LABEL: and32:225; RV64XVENTANACONDOPS: # %bb.0:226; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1227; RV64XVENTANACONDOPS-NEXT: and a1, a0, a1228; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2229; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0230; RV64XVENTANACONDOPS-NEXT: ret231;232; RV64XTHEADCONDMOV-LABEL: and32:233; RV64XTHEADCONDMOV: # %bb.0:234; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1235; RV64XTHEADCONDMOV-NEXT: and a1, a0, a1236; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2237; RV64XTHEADCONDMOV-NEXT: ret238;239; RV32ZICOND-LABEL: and32:240; RV32ZICOND: # %bb.0:241; RV32ZICOND-NEXT: andi a2, a2, 1242; RV32ZICOND-NEXT: and a1, a0, a1243; RV32ZICOND-NEXT: czero.nez a0, a0, a2244; RV32ZICOND-NEXT: or a0, a1, a0245; RV32ZICOND-NEXT: ret246;247; RV64ZICOND-LABEL: and32:248; RV64ZICOND: # %bb.0:249; RV64ZICOND-NEXT: andi a2, a2, 1250; RV64ZICOND-NEXT: and a1, a0, a1251; RV64ZICOND-NEXT: czero.nez a0, a0, a2252; RV64ZICOND-NEXT: or a0, a1, a0253; RV64ZICOND-NEXT: ret254 %binop = and i32 %x, %y255 %select_ = select i1 %c, i32 %binop, i32 %x256 ret i32 %select_257}258 259 260define i32 @add32(i32 %x, i32 %y, i1 %c) {261; RV32I-LABEL: add32:262; RV32I: # %bb.0:263; RV32I-NEXT: slli a2, a2, 31264; RV32I-NEXT: srai a2, a2, 31265; RV32I-NEXT: and a1, a2, a1266; RV32I-NEXT: add a0, a0, a1267; RV32I-NEXT: ret268;269; RV64I-LABEL: add32:270; RV64I: # %bb.0:271; RV64I-NEXT: slli a2, a2, 63272; RV64I-NEXT: srai a2, a2, 63273; RV64I-NEXT: and a1, a2, a1274; RV64I-NEXT: addw a0, a0, a1275; RV64I-NEXT: ret276;277; RV64XVENTANACONDOPS-LABEL: add32:278; RV64XVENTANACONDOPS: # %bb.0:279; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1280; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2281; RV64XVENTANACONDOPS-NEXT: addw a0, a0, a1282; RV64XVENTANACONDOPS-NEXT: ret283;284; RV64XTHEADCONDMOV-LABEL: add32:285; RV64XTHEADCONDMOV: # %bb.0:286; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1287; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2288; RV64XTHEADCONDMOV-NEXT: addw a0, a0, a1289; RV64XTHEADCONDMOV-NEXT: ret290;291; RV32ZICOND-LABEL: add32:292; RV32ZICOND: # %bb.0:293; RV32ZICOND-NEXT: andi a2, a2, 1294; RV32ZICOND-NEXT: czero.eqz a1, a1, a2295; RV32ZICOND-NEXT: add a0, a0, a1296; RV32ZICOND-NEXT: ret297;298; RV64ZICOND-LABEL: add32:299; RV64ZICOND: # %bb.0:300; RV64ZICOND-NEXT: andi a2, a2, 1301; RV64ZICOND-NEXT: czero.eqz a1, a1, a2302; RV64ZICOND-NEXT: addw a0, a0, a1303; RV64ZICOND-NEXT: ret304 %binop = add i32 %x, %y305 %select_ = select i1 %c, i32 %binop, i32 %x306 ret i32 %select_307}308 309 310define i32 @or32(i32 %x, i32 %y, i1 %c) {311; RV32I-LABEL: or32:312; RV32I: # %bb.0:313; RV32I-NEXT: slli a2, a2, 31314; RV32I-NEXT: srai a2, a2, 31315; RV32I-NEXT: and a1, a2, a1316; RV32I-NEXT: or a0, a0, a1317; RV32I-NEXT: ret318;319; RV64I-LABEL: or32:320; RV64I: # %bb.0:321; RV64I-NEXT: slli a2, a2, 63322; RV64I-NEXT: srai a2, a2, 63323; RV64I-NEXT: and a1, a2, a1324; RV64I-NEXT: or a0, a0, a1325; RV64I-NEXT: ret326;327; RV64XVENTANACONDOPS-LABEL: or32:328; RV64XVENTANACONDOPS: # %bb.0:329; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1330; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2331; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1332; RV64XVENTANACONDOPS-NEXT: ret333;334; RV64XTHEADCONDMOV-LABEL: or32:335; RV64XTHEADCONDMOV: # %bb.0:336; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1337; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2338; RV64XTHEADCONDMOV-NEXT: or a0, a0, a1339; RV64XTHEADCONDMOV-NEXT: ret340;341; RV32ZICOND-LABEL: or32:342; RV32ZICOND: # %bb.0:343; RV32ZICOND-NEXT: andi a2, a2, 1344; RV32ZICOND-NEXT: czero.eqz a1, a1, a2345; RV32ZICOND-NEXT: or a0, a0, a1346; RV32ZICOND-NEXT: ret347;348; RV64ZICOND-LABEL: or32:349; RV64ZICOND: # %bb.0:350; RV64ZICOND-NEXT: andi a2, a2, 1351; RV64ZICOND-NEXT: czero.eqz a1, a1, a2352; RV64ZICOND-NEXT: or a0, a0, a1353; RV64ZICOND-NEXT: ret354 %binop = or i32 %x, %y355 %select_ = select i1 %c, i32 %binop, i32 %x356 ret i32 %select_357}358 359define i32 @xor32(i32 %x, i32 %y, i1 %c) {360; RV32I-LABEL: xor32:361; RV32I: # %bb.0:362; RV32I-NEXT: slli a2, a2, 31363; RV32I-NEXT: srai a2, a2, 31364; RV32I-NEXT: and a1, a2, a1365; RV32I-NEXT: xor a0, a0, a1366; RV32I-NEXT: ret367;368; RV64I-LABEL: xor32:369; RV64I: # %bb.0:370; RV64I-NEXT: slli a2, a2, 63371; RV64I-NEXT: srai a2, a2, 63372; RV64I-NEXT: and a1, a2, a1373; RV64I-NEXT: xor a0, a0, a1374; RV64I-NEXT: ret375;376; RV64XVENTANACONDOPS-LABEL: xor32:377; RV64XVENTANACONDOPS: # %bb.0:378; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1379; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2380; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1381; RV64XVENTANACONDOPS-NEXT: ret382;383; RV64XTHEADCONDMOV-LABEL: xor32:384; RV64XTHEADCONDMOV: # %bb.0:385; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1386; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2387; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a1388; RV64XTHEADCONDMOV-NEXT: ret389;390; RV32ZICOND-LABEL: xor32:391; RV32ZICOND: # %bb.0:392; RV32ZICOND-NEXT: andi a2, a2, 1393; RV32ZICOND-NEXT: czero.eqz a1, a1, a2394; RV32ZICOND-NEXT: xor a0, a0, a1395; RV32ZICOND-NEXT: ret396;397; RV64ZICOND-LABEL: xor32:398; RV64ZICOND: # %bb.0:399; RV64ZICOND-NEXT: andi a2, a2, 1400; RV64ZICOND-NEXT: czero.eqz a1, a1, a2401; RV64ZICOND-NEXT: xor a0, a0, a1402; RV64ZICOND-NEXT: ret403 %binop = xor i32 %x, %y404 %select_ = select i1 %c, i32 %binop, i32 %x405 ret i32 %select_406}407 408define i64 @shl64(i64 %x, i64 %y, i1 %c) {409; RV32I-LABEL: shl64:410; RV32I: # %bb.0:411; RV32I-NEXT: slli a4, a4, 31412; RV32I-NEXT: srai a4, a4, 31413; RV32I-NEXT: and a4, a4, a2414; RV32I-NEXT: addi a3, a4, -32415; RV32I-NEXT: sll a2, a0, a4416; RV32I-NEXT: bltz a3, .LBB8_2417; RV32I-NEXT: # %bb.1:418; RV32I-NEXT: mv a1, a2419; RV32I-NEXT: j .LBB8_3420; RV32I-NEXT: .LBB8_2:421; RV32I-NEXT: sll a1, a1, a4422; RV32I-NEXT: not a4, a4423; RV32I-NEXT: srli a0, a0, 1424; RV32I-NEXT: srl a0, a0, a4425; RV32I-NEXT: or a1, a1, a0426; RV32I-NEXT: .LBB8_3:427; RV32I-NEXT: srai a0, a3, 31428; RV32I-NEXT: and a0, a0, a2429; RV32I-NEXT: ret430;431; RV64I-LABEL: shl64:432; RV64I: # %bb.0:433; RV64I-NEXT: slli a2, a2, 63434; RV64I-NEXT: srai a2, a2, 63435; RV64I-NEXT: and a1, a2, a1436; RV64I-NEXT: sll a0, a0, a1437; RV64I-NEXT: ret438;439; RV64XVENTANACONDOPS-LABEL: shl64:440; RV64XVENTANACONDOPS: # %bb.0:441; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1442; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2443; RV64XVENTANACONDOPS-NEXT: sll a0, a0, a1444; RV64XVENTANACONDOPS-NEXT: ret445;446; RV64XTHEADCONDMOV-LABEL: shl64:447; RV64XTHEADCONDMOV: # %bb.0:448; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1449; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2450; RV64XTHEADCONDMOV-NEXT: sll a0, a0, a1451; RV64XTHEADCONDMOV-NEXT: ret452;453; RV32ZICOND-LABEL: shl64:454; RV32ZICOND: # %bb.0:455; RV32ZICOND-NEXT: andi a4, a4, 1456; RV32ZICOND-NEXT: srli a3, a0, 1457; RV32ZICOND-NEXT: czero.eqz a2, a2, a4458; RV32ZICOND-NEXT: sll a0, a0, a2459; RV32ZICOND-NEXT: addi a4, a2, -32460; RV32ZICOND-NEXT: sll a1, a1, a2461; RV32ZICOND-NEXT: not a2, a2462; RV32ZICOND-NEXT: srli a4, a4, 31463; RV32ZICOND-NEXT: srl a2, a3, a2464; RV32ZICOND-NEXT: czero.nez a3, a0, a4465; RV32ZICOND-NEXT: or a1, a1, a2466; RV32ZICOND-NEXT: czero.eqz a1, a1, a4467; RV32ZICOND-NEXT: or a1, a1, a3468; RV32ZICOND-NEXT: czero.eqz a0, a0, a4469; RV32ZICOND-NEXT: ret470;471; RV64ZICOND-LABEL: shl64:472; RV64ZICOND: # %bb.0:473; RV64ZICOND-NEXT: andi a2, a2, 1474; RV64ZICOND-NEXT: czero.eqz a1, a1, a2475; RV64ZICOND-NEXT: sll a0, a0, a1476; RV64ZICOND-NEXT: ret477 %binop = shl i64 %x, %y478 %select_ = select i1 %c, i64 %binop, i64 %x479 ret i64 %select_480}481 482define i64 @ashr64(i64 %x, i64 %y, i1 %c) {483; RV32I-LABEL: ashr64:484; RV32I: # %bb.0:485; RV32I-NEXT: mv a3, a0486; RV32I-NEXT: slli a4, a4, 31487; RV32I-NEXT: srai a4, a4, 31488; RV32I-NEXT: and a2, a4, a2489; RV32I-NEXT: addi a4, a2, -32490; RV32I-NEXT: sra a0, a1, a2491; RV32I-NEXT: bltz a4, .LBB9_2492; RV32I-NEXT: # %bb.1:493; RV32I-NEXT: srai a1, a1, 31494; RV32I-NEXT: ret495; RV32I-NEXT: .LBB9_2:496; RV32I-NEXT: srl a3, a3, a2497; RV32I-NEXT: not a2, a2498; RV32I-NEXT: slli a1, a1, 1499; RV32I-NEXT: sll a1, a1, a2500; RV32I-NEXT: or a3, a3, a1501; RV32I-NEXT: mv a1, a0502; RV32I-NEXT: mv a0, a3503; RV32I-NEXT: ret504;505; RV64I-LABEL: ashr64:506; RV64I: # %bb.0:507; RV64I-NEXT: slli a2, a2, 63508; RV64I-NEXT: srai a2, a2, 63509; RV64I-NEXT: and a1, a2, a1510; RV64I-NEXT: sra a0, a0, a1511; RV64I-NEXT: ret512;513; RV64XVENTANACONDOPS-LABEL: ashr64:514; RV64XVENTANACONDOPS: # %bb.0:515; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1516; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2517; RV64XVENTANACONDOPS-NEXT: sra a0, a0, a1518; RV64XVENTANACONDOPS-NEXT: ret519;520; RV64XTHEADCONDMOV-LABEL: ashr64:521; RV64XTHEADCONDMOV: # %bb.0:522; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1523; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2524; RV64XTHEADCONDMOV-NEXT: sra a0, a0, a1525; RV64XTHEADCONDMOV-NEXT: ret526;527; RV32ZICOND-LABEL: ashr64:528; RV32ZICOND: # %bb.0:529; RV32ZICOND-NEXT: andi a4, a4, 1530; RV32ZICOND-NEXT: slli a3, a1, 1531; RV32ZICOND-NEXT: srai a5, a1, 31532; RV32ZICOND-NEXT: czero.eqz a2, a2, a4533; RV32ZICOND-NEXT: sra a1, a1, a2534; RV32ZICOND-NEXT: addi a4, a2, -32535; RV32ZICOND-NEXT: srl a0, a0, a2536; RV32ZICOND-NEXT: not a2, a2537; RV32ZICOND-NEXT: srli a4, a4, 31538; RV32ZICOND-NEXT: sll a2, a3, a2539; RV32ZICOND-NEXT: czero.nez a3, a1, a4540; RV32ZICOND-NEXT: or a0, a0, a2541; RV32ZICOND-NEXT: czero.eqz a1, a1, a4542; RV32ZICOND-NEXT: czero.nez a2, a5, a4543; RV32ZICOND-NEXT: czero.eqz a0, a0, a4544; RV32ZICOND-NEXT: or a0, a0, a3545; RV32ZICOND-NEXT: or a1, a1, a2546; RV32ZICOND-NEXT: ret547;548; RV64ZICOND-LABEL: ashr64:549; RV64ZICOND: # %bb.0:550; RV64ZICOND-NEXT: andi a2, a2, 1551; RV64ZICOND-NEXT: czero.eqz a1, a1, a2552; RV64ZICOND-NEXT: sra a0, a0, a1553; RV64ZICOND-NEXT: ret554 %binop = ashr i64 %x, %y555 %select_ = select i1 %c, i64 %binop, i64 %x556 ret i64 %select_557}558 559define i64 @lshr64(i64 %x, i64 %y, i1 %c) {560; RV32I-LABEL: lshr64:561; RV32I: # %bb.0:562; RV32I-NEXT: slli a4, a4, 31563; RV32I-NEXT: srai a4, a4, 31564; RV32I-NEXT: and a4, a4, a2565; RV32I-NEXT: addi a3, a4, -32566; RV32I-NEXT: srl a2, a1, a4567; RV32I-NEXT: bltz a3, .LBB10_2568; RV32I-NEXT: # %bb.1:569; RV32I-NEXT: mv a0, a2570; RV32I-NEXT: j .LBB10_3571; RV32I-NEXT: .LBB10_2:572; RV32I-NEXT: srl a0, a0, a4573; RV32I-NEXT: not a4, a4574; RV32I-NEXT: slli a1, a1, 1575; RV32I-NEXT: sll a1, a1, a4576; RV32I-NEXT: or a0, a0, a1577; RV32I-NEXT: .LBB10_3:578; RV32I-NEXT: srai a1, a3, 31579; RV32I-NEXT: and a1, a1, a2580; RV32I-NEXT: ret581;582; RV64I-LABEL: lshr64:583; RV64I: # %bb.0:584; RV64I-NEXT: slli a2, a2, 63585; RV64I-NEXT: srai a2, a2, 63586; RV64I-NEXT: and a1, a2, a1587; RV64I-NEXT: srl a0, a0, a1588; RV64I-NEXT: ret589;590; RV64XVENTANACONDOPS-LABEL: lshr64:591; RV64XVENTANACONDOPS: # %bb.0:592; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1593; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2594; RV64XVENTANACONDOPS-NEXT: srl a0, a0, a1595; RV64XVENTANACONDOPS-NEXT: ret596;597; RV64XTHEADCONDMOV-LABEL: lshr64:598; RV64XTHEADCONDMOV: # %bb.0:599; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1600; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2601; RV64XTHEADCONDMOV-NEXT: srl a0, a0, a1602; RV64XTHEADCONDMOV-NEXT: ret603;604; RV32ZICOND-LABEL: lshr64:605; RV32ZICOND: # %bb.0:606; RV32ZICOND-NEXT: andi a4, a4, 1607; RV32ZICOND-NEXT: slli a3, a1, 1608; RV32ZICOND-NEXT: czero.eqz a2, a2, a4609; RV32ZICOND-NEXT: srl a1, a1, a2610; RV32ZICOND-NEXT: addi a4, a2, -32611; RV32ZICOND-NEXT: srl a0, a0, a2612; RV32ZICOND-NEXT: not a2, a2613; RV32ZICOND-NEXT: srli a4, a4, 31614; RV32ZICOND-NEXT: sll a2, a3, a2615; RV32ZICOND-NEXT: czero.nez a3, a1, a4616; RV32ZICOND-NEXT: or a0, a0, a2617; RV32ZICOND-NEXT: czero.eqz a0, a0, a4618; RV32ZICOND-NEXT: or a0, a0, a3619; RV32ZICOND-NEXT: czero.eqz a1, a1, a4620; RV32ZICOND-NEXT: ret621;622; RV64ZICOND-LABEL: lshr64:623; RV64ZICOND: # %bb.0:624; RV64ZICOND-NEXT: andi a2, a2, 1625; RV64ZICOND-NEXT: czero.eqz a1, a1, a2626; RV64ZICOND-NEXT: srl a0, a0, a1627; RV64ZICOND-NEXT: ret628 %binop = lshr i64 %x, %y629 %select_ = select i1 %c, i64 %binop, i64 %x630 ret i64 %select_631}632 633define i64 @sub64(i64 %x, i64 %y, i1 %c) {634; RV32I-LABEL: sub64:635; RV32I: # %bb.0:636; RV32I-NEXT: slli a4, a4, 31637; RV32I-NEXT: srai a4, a4, 31638; RV32I-NEXT: and a2, a4, a2639; RV32I-NEXT: and a3, a4, a3640; RV32I-NEXT: sltu a4, a0, a2641; RV32I-NEXT: sub a1, a1, a3642; RV32I-NEXT: sub a1, a1, a4643; RV32I-NEXT: sub a0, a0, a2644; RV32I-NEXT: ret645;646; RV64I-LABEL: sub64:647; RV64I: # %bb.0:648; RV64I-NEXT: slli a2, a2, 63649; RV64I-NEXT: srai a2, a2, 63650; RV64I-NEXT: and a1, a2, a1651; RV64I-NEXT: sub a0, a0, a1652; RV64I-NEXT: ret653;654; RV64XVENTANACONDOPS-LABEL: sub64:655; RV64XVENTANACONDOPS: # %bb.0:656; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1657; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2658; RV64XVENTANACONDOPS-NEXT: sub a0, a0, a1659; RV64XVENTANACONDOPS-NEXT: ret660;661; RV64XTHEADCONDMOV-LABEL: sub64:662; RV64XTHEADCONDMOV: # %bb.0:663; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1664; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2665; RV64XTHEADCONDMOV-NEXT: sub a0, a0, a1666; RV64XTHEADCONDMOV-NEXT: ret667;668; RV32ZICOND-LABEL: sub64:669; RV32ZICOND: # %bb.0:670; RV32ZICOND-NEXT: andi a4, a4, 1671; RV32ZICOND-NEXT: czero.eqz a2, a2, a4672; RV32ZICOND-NEXT: czero.eqz a3, a3, a4673; RV32ZICOND-NEXT: sltu a4, a0, a2674; RV32ZICOND-NEXT: sub a1, a1, a3675; RV32ZICOND-NEXT: sub a1, a1, a4676; RV32ZICOND-NEXT: sub a0, a0, a2677; RV32ZICOND-NEXT: ret678;679; RV64ZICOND-LABEL: sub64:680; RV64ZICOND: # %bb.0:681; RV64ZICOND-NEXT: andi a2, a2, 1682; RV64ZICOND-NEXT: czero.eqz a1, a1, a2683; RV64ZICOND-NEXT: sub a0, a0, a1684; RV64ZICOND-NEXT: ret685 %binop = sub i64 %x, %y686 %select_ = select i1 %c, i64 %binop, i64 %x687 ret i64 %select_688}689 690define i64 @and64(i64 %x, i64 %y, i1 %c) {691; RV32I-LABEL: and64:692; RV32I: # %bb.0:693; RV32I-NEXT: andi a4, a4, 1694; RV32I-NEXT: beqz a4, .LBB12_2695; RV32I-NEXT: # %bb.1:696; RV32I-NEXT: and a1, a1, a3697; RV32I-NEXT: and a0, a0, a2698; RV32I-NEXT: .LBB12_2:699; RV32I-NEXT: ret700;701; RV64I-LABEL: and64:702; RV64I: # %bb.0:703; RV64I-NEXT: andi a2, a2, 1704; RV64I-NEXT: beqz a2, .LBB12_2705; RV64I-NEXT: # %bb.1:706; RV64I-NEXT: and a0, a0, a1707; RV64I-NEXT: .LBB12_2:708; RV64I-NEXT: ret709;710; RV64XVENTANACONDOPS-LABEL: and64:711; RV64XVENTANACONDOPS: # %bb.0:712; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1713; RV64XVENTANACONDOPS-NEXT: and a1, a0, a1714; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2715; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0716; RV64XVENTANACONDOPS-NEXT: ret717;718; RV64XTHEADCONDMOV-LABEL: and64:719; RV64XTHEADCONDMOV: # %bb.0:720; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1721; RV64XTHEADCONDMOV-NEXT: and a1, a0, a1722; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2723; RV64XTHEADCONDMOV-NEXT: ret724;725; RV32ZICOND-LABEL: and64:726; RV32ZICOND: # %bb.0:727; RV32ZICOND-NEXT: andi a4, a4, 1728; RV32ZICOND-NEXT: and a3, a1, a3729; RV32ZICOND-NEXT: and a2, a0, a2730; RV32ZICOND-NEXT: czero.nez a0, a0, a4731; RV32ZICOND-NEXT: czero.nez a1, a1, a4732; RV32ZICOND-NEXT: or a0, a2, a0733; RV32ZICOND-NEXT: or a1, a3, a1734; RV32ZICOND-NEXT: ret735;736; RV64ZICOND-LABEL: and64:737; RV64ZICOND: # %bb.0:738; RV64ZICOND-NEXT: andi a2, a2, 1739; RV64ZICOND-NEXT: and a1, a0, a1740; RV64ZICOND-NEXT: czero.nez a0, a0, a2741; RV64ZICOND-NEXT: or a0, a1, a0742; RV64ZICOND-NEXT: ret743 %binop = and i64 %x, %y744 %select_ = select i1 %c, i64 %binop, i64 %x745 ret i64 %select_746}747 748 749define i64 @add64(i64 %x, i64 %y, i1 %c) {750; RV32I-LABEL: add64:751; RV32I: # %bb.0:752; RV32I-NEXT: slli a4, a4, 31753; RV32I-NEXT: srai a4, a4, 31754; RV32I-NEXT: and a3, a4, a3755; RV32I-NEXT: and a2, a4, a2756; RV32I-NEXT: add a1, a1, a3757; RV32I-NEXT: add a2, a0, a2758; RV32I-NEXT: sltu a0, a2, a0759; RV32I-NEXT: add a1, a1, a0760; RV32I-NEXT: mv a0, a2761; RV32I-NEXT: ret762;763; RV64I-LABEL: add64:764; RV64I: # %bb.0:765; RV64I-NEXT: slli a2, a2, 63766; RV64I-NEXT: srai a2, a2, 63767; RV64I-NEXT: and a1, a2, a1768; RV64I-NEXT: add a0, a0, a1769; RV64I-NEXT: ret770;771; RV64XVENTANACONDOPS-LABEL: add64:772; RV64XVENTANACONDOPS: # %bb.0:773; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1774; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2775; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1776; RV64XVENTANACONDOPS-NEXT: ret777;778; RV64XTHEADCONDMOV-LABEL: add64:779; RV64XTHEADCONDMOV: # %bb.0:780; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1781; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2782; RV64XTHEADCONDMOV-NEXT: add a0, a0, a1783; RV64XTHEADCONDMOV-NEXT: ret784;785; RV32ZICOND-LABEL: add64:786; RV32ZICOND: # %bb.0:787; RV32ZICOND-NEXT: andi a4, a4, 1788; RV32ZICOND-NEXT: czero.eqz a3, a3, a4789; RV32ZICOND-NEXT: czero.eqz a2, a2, a4790; RV32ZICOND-NEXT: add a1, a1, a3791; RV32ZICOND-NEXT: add a2, a0, a2792; RV32ZICOND-NEXT: sltu a0, a2, a0793; RV32ZICOND-NEXT: add a1, a1, a0794; RV32ZICOND-NEXT: mv a0, a2795; RV32ZICOND-NEXT: ret796;797; RV64ZICOND-LABEL: add64:798; RV64ZICOND: # %bb.0:799; RV64ZICOND-NEXT: andi a2, a2, 1800; RV64ZICOND-NEXT: czero.eqz a1, a1, a2801; RV64ZICOND-NEXT: add a0, a0, a1802; RV64ZICOND-NEXT: ret803 %binop = add i64 %x, %y804 %select_ = select i1 %c, i64 %binop, i64 %x805 ret i64 %select_806}807 808 809define i64 @or64(i64 %x, i64 %y, i1 %c) {810; RV32I-LABEL: or64:811; RV32I: # %bb.0:812; RV32I-NEXT: slli a4, a4, 31813; RV32I-NEXT: srai a4, a4, 31814; RV32I-NEXT: and a2, a4, a2815; RV32I-NEXT: and a3, a4, a3816; RV32I-NEXT: or a0, a0, a2817; RV32I-NEXT: or a1, a1, a3818; RV32I-NEXT: ret819;820; RV64I-LABEL: or64:821; RV64I: # %bb.0:822; RV64I-NEXT: slli a2, a2, 63823; RV64I-NEXT: srai a2, a2, 63824; RV64I-NEXT: and a1, a2, a1825; RV64I-NEXT: or a0, a0, a1826; RV64I-NEXT: ret827;828; RV64XVENTANACONDOPS-LABEL: or64:829; RV64XVENTANACONDOPS: # %bb.0:830; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1831; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2832; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1833; RV64XVENTANACONDOPS-NEXT: ret834;835; RV64XTHEADCONDMOV-LABEL: or64:836; RV64XTHEADCONDMOV: # %bb.0:837; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1838; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2839; RV64XTHEADCONDMOV-NEXT: or a0, a0, a1840; RV64XTHEADCONDMOV-NEXT: ret841;842; RV32ZICOND-LABEL: or64:843; RV32ZICOND: # %bb.0:844; RV32ZICOND-NEXT: andi a4, a4, 1845; RV32ZICOND-NEXT: czero.eqz a2, a2, a4846; RV32ZICOND-NEXT: czero.eqz a3, a3, a4847; RV32ZICOND-NEXT: or a0, a0, a2848; RV32ZICOND-NEXT: or a1, a1, a3849; RV32ZICOND-NEXT: ret850;851; RV64ZICOND-LABEL: or64:852; RV64ZICOND: # %bb.0:853; RV64ZICOND-NEXT: andi a2, a2, 1854; RV64ZICOND-NEXT: czero.eqz a1, a1, a2855; RV64ZICOND-NEXT: or a0, a0, a1856; RV64ZICOND-NEXT: ret857 %binop = or i64 %x, %y858 %select_ = select i1 %c, i64 %binop, i64 %x859 ret i64 %select_860}861 862define i64 @xor64(i64 %x, i64 %y, i1 %c) {863; RV32I-LABEL: xor64:864; RV32I: # %bb.0:865; RV32I-NEXT: slli a4, a4, 31866; RV32I-NEXT: srai a4, a4, 31867; RV32I-NEXT: and a2, a4, a2868; RV32I-NEXT: and a3, a4, a3869; RV32I-NEXT: xor a0, a0, a2870; RV32I-NEXT: xor a1, a1, a3871; RV32I-NEXT: ret872;873; RV64I-LABEL: xor64:874; RV64I: # %bb.0:875; RV64I-NEXT: slli a2, a2, 63876; RV64I-NEXT: srai a2, a2, 63877; RV64I-NEXT: and a1, a2, a1878; RV64I-NEXT: xor a0, a0, a1879; RV64I-NEXT: ret880;881; RV64XVENTANACONDOPS-LABEL: xor64:882; RV64XVENTANACONDOPS: # %bb.0:883; RV64XVENTANACONDOPS-NEXT: andi a2, a2, 1884; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2885; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1886; RV64XVENTANACONDOPS-NEXT: ret887;888; RV64XTHEADCONDMOV-LABEL: xor64:889; RV64XTHEADCONDMOV: # %bb.0:890; RV64XTHEADCONDMOV-NEXT: andi a2, a2, 1891; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a2892; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a1893; RV64XTHEADCONDMOV-NEXT: ret894;895; RV32ZICOND-LABEL: xor64:896; RV32ZICOND: # %bb.0:897; RV32ZICOND-NEXT: andi a4, a4, 1898; RV32ZICOND-NEXT: czero.eqz a2, a2, a4899; RV32ZICOND-NEXT: czero.eqz a3, a3, a4900; RV32ZICOND-NEXT: xor a0, a0, a2901; RV32ZICOND-NEXT: xor a1, a1, a3902; RV32ZICOND-NEXT: ret903;904; RV64ZICOND-LABEL: xor64:905; RV64ZICOND: # %bb.0:906; RV64ZICOND-NEXT: andi a2, a2, 1907; RV64ZICOND-NEXT: czero.eqz a1, a1, a2908; RV64ZICOND-NEXT: xor a0, a0, a1909; RV64ZICOND-NEXT: ret910 %binop = xor i64 %x, %y911 %select_ = select i1 %c, i64 %binop, i64 %x912 ret i64 %select_913}914