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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV32I3; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV64I4; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV32XVENTANACONDOPS5; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS6; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+xtheadbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV7; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND8; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND9 10define i64 @zero1(i64 %rs1, i1 zeroext %rc) {11; RV32I-LABEL: zero1:12; RV32I: # %bb.0:13; RV32I-NEXT: neg a2, a214; RV32I-NEXT: and a0, a2, a015; RV32I-NEXT: and a1, a2, a116; RV32I-NEXT: ret17;18; RV64I-LABEL: zero1:19; RV64I: # %bb.0:20; RV64I-NEXT: neg a1, a121; RV64I-NEXT: and a0, a1, a022; RV64I-NEXT: ret23;24; RV32XVENTANACONDOPS-LABEL: zero1:25; RV32XVENTANACONDOPS: # %bb.0:26; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a227; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a228; RV32XVENTANACONDOPS-NEXT: ret29;30; RV64XVENTANACONDOPS-LABEL: zero1:31; RV64XVENTANACONDOPS: # %bb.0:32; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a133; RV64XVENTANACONDOPS-NEXT: ret34;35; RV64XTHEADCONDMOV-LABEL: zero1:36; RV64XTHEADCONDMOV: # %bb.0:37; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a138; RV64XTHEADCONDMOV-NEXT: ret39;40; RV32ZICOND-LABEL: zero1:41; RV32ZICOND: # %bb.0:42; RV32ZICOND-NEXT: czero.eqz a0, a0, a243; RV32ZICOND-NEXT: czero.eqz a1, a1, a244; RV32ZICOND-NEXT: ret45;46; RV64ZICOND-LABEL: zero1:47; RV64ZICOND: # %bb.0:48; RV64ZICOND-NEXT: czero.eqz a0, a0, a149; RV64ZICOND-NEXT: ret50 %sel = select i1 %rc, i64 %rs1, i64 051 ret i64 %sel52}53 54define i64 @zero2(i64 %rs1, i1 zeroext %rc) {55; RV32I-LABEL: zero2:56; RV32I: # %bb.0:57; RV32I-NEXT: addi a2, a2, -158; RV32I-NEXT: and a0, a2, a059; RV32I-NEXT: and a1, a2, a160; RV32I-NEXT: ret61;62; RV64I-LABEL: zero2:63; RV64I: # %bb.0:64; RV64I-NEXT: addi a1, a1, -165; RV64I-NEXT: and a0, a1, a066; RV64I-NEXT: ret67;68; RV32XVENTANACONDOPS-LABEL: zero2:69; RV32XVENTANACONDOPS: # %bb.0:70; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a271; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a272; RV32XVENTANACONDOPS-NEXT: ret73;74; RV64XVENTANACONDOPS-LABEL: zero2:75; RV64XVENTANACONDOPS: # %bb.0:76; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a177; RV64XVENTANACONDOPS-NEXT: ret78;79; RV64XTHEADCONDMOV-LABEL: zero2:80; RV64XTHEADCONDMOV: # %bb.0:81; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, zero, a182; RV64XTHEADCONDMOV-NEXT: ret83;84; RV32ZICOND-LABEL: zero2:85; RV32ZICOND: # %bb.0:86; RV32ZICOND-NEXT: czero.nez a0, a0, a287; RV32ZICOND-NEXT: czero.nez a1, a1, a288; RV32ZICOND-NEXT: ret89;90; RV64ZICOND-LABEL: zero2:91; RV64ZICOND: # %bb.0:92; RV64ZICOND-NEXT: czero.nez a0, a0, a193; RV64ZICOND-NEXT: ret94 %sel = select i1 %rc, i64 0, i64 %rs195 ret i64 %sel96}97 98define i64 @zero_singlebit1(i64 %rs1, i64 %rs2) {99; RV32I-LABEL: zero_singlebit1:100; RV32I: # %bb.0:101; RV32I-NEXT: bexti a2, a2, 12102; RV32I-NEXT: addi a2, a2, -1103; RV32I-NEXT: and a0, a2, a0104; RV32I-NEXT: and a1, a2, a1105; RV32I-NEXT: ret106;107; RV64I-LABEL: zero_singlebit1:108; RV64I: # %bb.0:109; RV64I-NEXT: bexti a1, a1, 12110; RV64I-NEXT: addi a1, a1, -1111; RV64I-NEXT: and a0, a1, a0112; RV64I-NEXT: ret113;114; RV32XVENTANACONDOPS-LABEL: zero_singlebit1:115; RV32XVENTANACONDOPS: # %bb.0:116; RV32XVENTANACONDOPS-NEXT: bexti a2, a2, 12117; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2118; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a2119; RV32XVENTANACONDOPS-NEXT: ret120;121; RV64XVENTANACONDOPS-LABEL: zero_singlebit1:122; RV64XVENTANACONDOPS: # %bb.0:123; RV64XVENTANACONDOPS-NEXT: bexti a1, a1, 12124; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a1125; RV64XVENTANACONDOPS-NEXT: ret126;127; RV64XTHEADCONDMOV-LABEL: zero_singlebit1:128; RV64XTHEADCONDMOV: # %bb.0:129; RV64XTHEADCONDMOV-NEXT: th.tst a1, a1, 12130; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, zero, a1131; RV64XTHEADCONDMOV-NEXT: ret132;133; RV32ZICOND-LABEL: zero_singlebit1:134; RV32ZICOND: # %bb.0:135; RV32ZICOND-NEXT: bexti a2, a2, 12136; RV32ZICOND-NEXT: czero.nez a0, a0, a2137; RV32ZICOND-NEXT: czero.nez a1, a1, a2138; RV32ZICOND-NEXT: ret139;140; RV64ZICOND-LABEL: zero_singlebit1:141; RV64ZICOND: # %bb.0:142; RV64ZICOND-NEXT: bexti a1, a1, 12143; RV64ZICOND-NEXT: czero.nez a0, a0, a1144; RV64ZICOND-NEXT: ret145 %and = and i64 %rs2, 4096146 %rc = icmp eq i64 %and, 0147 %sel = select i1 %rc, i64 %rs1, i64 0148 ret i64 %sel149}150 151define i64 @zero_singlebit2(i64 %rs1, i64 %rs2) {152; RV32I-LABEL: zero_singlebit2:153; RV32I: # %bb.0:154; RV32I-NEXT: slli a2, a2, 19155; RV32I-NEXT: srai a2, a2, 31156; RV32I-NEXT: and a0, a2, a0157; RV32I-NEXT: and a1, a2, a1158; RV32I-NEXT: ret159;160; RV64I-LABEL: zero_singlebit2:161; RV64I: # %bb.0:162; RV64I-NEXT: slli a1, a1, 51163; RV64I-NEXT: srai a1, a1, 63164; RV64I-NEXT: and a0, a1, a0165; RV64I-NEXT: ret166;167; RV32XVENTANACONDOPS-LABEL: zero_singlebit2:168; RV32XVENTANACONDOPS: # %bb.0:169; RV32XVENTANACONDOPS-NEXT: bexti a2, a2, 12170; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2171; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2172; RV32XVENTANACONDOPS-NEXT: ret173;174; RV64XVENTANACONDOPS-LABEL: zero_singlebit2:175; RV64XVENTANACONDOPS: # %bb.0:176; RV64XVENTANACONDOPS-NEXT: bexti a1, a1, 12177; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a1178; RV64XVENTANACONDOPS-NEXT: ret179;180; RV64XTHEADCONDMOV-LABEL: zero_singlebit2:181; RV64XTHEADCONDMOV: # %bb.0:182; RV64XTHEADCONDMOV-NEXT: th.tst a1, a1, 12183; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a1184; RV64XTHEADCONDMOV-NEXT: ret185;186; RV32ZICOND-LABEL: zero_singlebit2:187; RV32ZICOND: # %bb.0:188; RV32ZICOND-NEXT: bexti a2, a2, 12189; RV32ZICOND-NEXT: czero.eqz a0, a0, a2190; RV32ZICOND-NEXT: czero.eqz a1, a1, a2191; RV32ZICOND-NEXT: ret192;193; RV64ZICOND-LABEL: zero_singlebit2:194; RV64ZICOND: # %bb.0:195; RV64ZICOND-NEXT: bexti a1, a1, 12196; RV64ZICOND-NEXT: czero.eqz a0, a0, a1197; RV64ZICOND-NEXT: ret198 %and = and i64 %rs2, 4096199 %rc = icmp eq i64 %and, 0200 %sel = select i1 %rc, i64 0, i64 %rs1201 ret i64 %sel202}203 204define i64 @add1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {205; RV32I-LABEL: add1:206; RV32I: # %bb.0:207; RV32I-NEXT: neg a0, a0208; RV32I-NEXT: and a4, a0, a4209; RV32I-NEXT: and a0, a0, a3210; RV32I-NEXT: add a2, a2, a4211; RV32I-NEXT: add a0, a1, a0212; RV32I-NEXT: sltu a1, a0, a1213; RV32I-NEXT: add a1, a2, a1214; RV32I-NEXT: ret215;216; RV64I-LABEL: add1:217; RV64I: # %bb.0:218; RV64I-NEXT: neg a0, a0219; RV64I-NEXT: and a0, a0, a2220; RV64I-NEXT: add a0, a1, a0221; RV64I-NEXT: ret222;223; RV32XVENTANACONDOPS-LABEL: add1:224; RV32XVENTANACONDOPS: # %bb.0:225; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a0226; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0227; RV32XVENTANACONDOPS-NEXT: add a2, a2, a4228; RV32XVENTANACONDOPS-NEXT: add a0, a1, a0229; RV32XVENTANACONDOPS-NEXT: sltu a1, a0, a1230; RV32XVENTANACONDOPS-NEXT: add a1, a2, a1231; RV32XVENTANACONDOPS-NEXT: ret232;233; RV64XVENTANACONDOPS-LABEL: add1:234; RV64XVENTANACONDOPS: # %bb.0:235; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0236; RV64XVENTANACONDOPS-NEXT: add a0, a1, a0237; RV64XVENTANACONDOPS-NEXT: ret238;239; RV64XTHEADCONDMOV-LABEL: add1:240; RV64XTHEADCONDMOV: # %bb.0:241; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0242; RV64XTHEADCONDMOV-NEXT: add a0, a1, a2243; RV64XTHEADCONDMOV-NEXT: ret244;245; RV32ZICOND-LABEL: add1:246; RV32ZICOND: # %bb.0:247; RV32ZICOND-NEXT: czero.eqz a4, a4, a0248; RV32ZICOND-NEXT: czero.eqz a0, a3, a0249; RV32ZICOND-NEXT: add a2, a2, a4250; RV32ZICOND-NEXT: add a0, a1, a0251; RV32ZICOND-NEXT: sltu a1, a0, a1252; RV32ZICOND-NEXT: add a1, a2, a1253; RV32ZICOND-NEXT: ret254;255; RV64ZICOND-LABEL: add1:256; RV64ZICOND: # %bb.0:257; RV64ZICOND-NEXT: czero.eqz a0, a2, a0258; RV64ZICOND-NEXT: add a0, a1, a0259; RV64ZICOND-NEXT: ret260 %add = add i64 %rs1, %rs2261 %sel = select i1 %rc, i64 %add, i64 %rs1262 ret i64 %sel263}264 265define i64 @add2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {266; RV32I-LABEL: add2:267; RV32I: # %bb.0:268; RV32I-NEXT: neg a0, a0269; RV32I-NEXT: and a2, a0, a2270; RV32I-NEXT: and a0, a0, a1271; RV32I-NEXT: add a1, a4, a2272; RV32I-NEXT: add a0, a3, a0273; RV32I-NEXT: sltu a2, a0, a3274; RV32I-NEXT: add a1, a1, a2275; RV32I-NEXT: ret276;277; RV64I-LABEL: add2:278; RV64I: # %bb.0:279; RV64I-NEXT: neg a0, a0280; RV64I-NEXT: and a0, a0, a1281; RV64I-NEXT: add a0, a2, a0282; RV64I-NEXT: ret283;284; RV32XVENTANACONDOPS-LABEL: add2:285; RV32XVENTANACONDOPS: # %bb.0:286; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0287; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0288; RV32XVENTANACONDOPS-NEXT: add a1, a4, a2289; RV32XVENTANACONDOPS-NEXT: add a0, a3, a0290; RV32XVENTANACONDOPS-NEXT: sltu a2, a0, a3291; RV32XVENTANACONDOPS-NEXT: add a1, a1, a2292; RV32XVENTANACONDOPS-NEXT: ret293;294; RV64XVENTANACONDOPS-LABEL: add2:295; RV64XVENTANACONDOPS: # %bb.0:296; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0297; RV64XVENTANACONDOPS-NEXT: add a0, a2, a0298; RV64XVENTANACONDOPS-NEXT: ret299;300; RV64XTHEADCONDMOV-LABEL: add2:301; RV64XTHEADCONDMOV: # %bb.0:302; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0303; RV64XTHEADCONDMOV-NEXT: add a0, a2, a1304; RV64XTHEADCONDMOV-NEXT: ret305;306; RV32ZICOND-LABEL: add2:307; RV32ZICOND: # %bb.0:308; RV32ZICOND-NEXT: czero.eqz a2, a2, a0309; RV32ZICOND-NEXT: czero.eqz a0, a1, a0310; RV32ZICOND-NEXT: add a1, a4, a2311; RV32ZICOND-NEXT: add a0, a3, a0312; RV32ZICOND-NEXT: sltu a2, a0, a3313; RV32ZICOND-NEXT: add a1, a1, a2314; RV32ZICOND-NEXT: ret315;316; RV64ZICOND-LABEL: add2:317; RV64ZICOND: # %bb.0:318; RV64ZICOND-NEXT: czero.eqz a0, a1, a0319; RV64ZICOND-NEXT: add a0, a2, a0320; RV64ZICOND-NEXT: ret321 %add = add i64 %rs1, %rs2322 %sel = select i1 %rc, i64 %add, i64 %rs2323 ret i64 %sel324}325 326define i64 @add3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {327; RV32I-LABEL: add3:328; RV32I: # %bb.0:329; RV32I-NEXT: addi a0, a0, -1330; RV32I-NEXT: and a4, a0, a4331; RV32I-NEXT: and a0, a0, a3332; RV32I-NEXT: add a2, a2, a4333; RV32I-NEXT: add a0, a1, a0334; RV32I-NEXT: sltu a1, a0, a1335; RV32I-NEXT: add a1, a2, a1336; RV32I-NEXT: ret337;338; RV64I-LABEL: add3:339; RV64I: # %bb.0:340; RV64I-NEXT: addi a0, a0, -1341; RV64I-NEXT: and a0, a0, a2342; RV64I-NEXT: add a0, a1, a0343; RV64I-NEXT: ret344;345; RV32XVENTANACONDOPS-LABEL: add3:346; RV32XVENTANACONDOPS: # %bb.0:347; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0348; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a3, a0349; RV32XVENTANACONDOPS-NEXT: add a2, a2, a4350; RV32XVENTANACONDOPS-NEXT: add a0, a1, a0351; RV32XVENTANACONDOPS-NEXT: sltu a1, a0, a1352; RV32XVENTANACONDOPS-NEXT: add a1, a2, a1353; RV32XVENTANACONDOPS-NEXT: ret354;355; RV64XVENTANACONDOPS-LABEL: add3:356; RV64XVENTANACONDOPS: # %bb.0:357; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0358; RV64XVENTANACONDOPS-NEXT: add a0, a1, a0359; RV64XVENTANACONDOPS-NEXT: ret360;361; RV64XTHEADCONDMOV-LABEL: add3:362; RV64XTHEADCONDMOV: # %bb.0:363; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0364; RV64XTHEADCONDMOV-NEXT: add a0, a1, a2365; RV64XTHEADCONDMOV-NEXT: ret366;367; RV32ZICOND-LABEL: add3:368; RV32ZICOND: # %bb.0:369; RV32ZICOND-NEXT: czero.nez a4, a4, a0370; RV32ZICOND-NEXT: czero.nez a0, a3, a0371; RV32ZICOND-NEXT: add a2, a2, a4372; RV32ZICOND-NEXT: add a0, a1, a0373; RV32ZICOND-NEXT: sltu a1, a0, a1374; RV32ZICOND-NEXT: add a1, a2, a1375; RV32ZICOND-NEXT: ret376;377; RV64ZICOND-LABEL: add3:378; RV64ZICOND: # %bb.0:379; RV64ZICOND-NEXT: czero.nez a0, a2, a0380; RV64ZICOND-NEXT: add a0, a1, a0381; RV64ZICOND-NEXT: ret382 %add = add i64 %rs1, %rs2383 %sel = select i1 %rc, i64 %rs1, i64 %add384 ret i64 %sel385}386 387define i64 @add4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {388; RV32I-LABEL: add4:389; RV32I: # %bb.0:390; RV32I-NEXT: addi a0, a0, -1391; RV32I-NEXT: and a2, a0, a2392; RV32I-NEXT: and a0, a0, a1393; RV32I-NEXT: add a1, a4, a2394; RV32I-NEXT: add a0, a3, a0395; RV32I-NEXT: sltu a2, a0, a3396; RV32I-NEXT: add a1, a1, a2397; RV32I-NEXT: ret398;399; RV64I-LABEL: add4:400; RV64I: # %bb.0:401; RV64I-NEXT: addi a0, a0, -1402; RV64I-NEXT: and a0, a0, a1403; RV64I-NEXT: add a0, a2, a0404; RV64I-NEXT: ret405;406; RV32XVENTANACONDOPS-LABEL: add4:407; RV32XVENTANACONDOPS: # %bb.0:408; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0409; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0410; RV32XVENTANACONDOPS-NEXT: add a1, a4, a2411; RV32XVENTANACONDOPS-NEXT: add a0, a3, a0412; RV32XVENTANACONDOPS-NEXT: sltu a2, a0, a3413; RV32XVENTANACONDOPS-NEXT: add a1, a1, a2414; RV32XVENTANACONDOPS-NEXT: ret415;416; RV64XVENTANACONDOPS-LABEL: add4:417; RV64XVENTANACONDOPS: # %bb.0:418; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0419; RV64XVENTANACONDOPS-NEXT: add a0, a2, a0420; RV64XVENTANACONDOPS-NEXT: ret421;422; RV64XTHEADCONDMOV-LABEL: add4:423; RV64XTHEADCONDMOV: # %bb.0:424; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0425; RV64XTHEADCONDMOV-NEXT: add a0, a2, a1426; RV64XTHEADCONDMOV-NEXT: ret427;428; RV32ZICOND-LABEL: add4:429; RV32ZICOND: # %bb.0:430; RV32ZICOND-NEXT: czero.nez a2, a2, a0431; RV32ZICOND-NEXT: czero.nez a0, a1, a0432; RV32ZICOND-NEXT: add a1, a4, a2433; RV32ZICOND-NEXT: add a0, a3, a0434; RV32ZICOND-NEXT: sltu a2, a0, a3435; RV32ZICOND-NEXT: add a1, a1, a2436; RV32ZICOND-NEXT: ret437;438; RV64ZICOND-LABEL: add4:439; RV64ZICOND: # %bb.0:440; RV64ZICOND-NEXT: czero.nez a0, a1, a0441; RV64ZICOND-NEXT: add a0, a2, a0442; RV64ZICOND-NEXT: ret443 %add = add i64 %rs1, %rs2444 %sel = select i1 %rc, i64 %rs2, i64 %add445 ret i64 %sel446}447 448define i64 @sub1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {449; RV32I-LABEL: sub1:450; RV32I: # %bb.0:451; RV32I-NEXT: neg a0, a0452; RV32I-NEXT: and a3, a0, a3453; RV32I-NEXT: and a0, a0, a4454; RV32I-NEXT: sltu a4, a1, a3455; RV32I-NEXT: sub a2, a2, a0456; RV32I-NEXT: sub a2, a2, a4457; RV32I-NEXT: sub a0, a1, a3458; RV32I-NEXT: mv a1, a2459; RV32I-NEXT: ret460;461; RV64I-LABEL: sub1:462; RV64I: # %bb.0:463; RV64I-NEXT: neg a0, a0464; RV64I-NEXT: and a0, a0, a2465; RV64I-NEXT: sub a0, a1, a0466; RV64I-NEXT: ret467;468; RV32XVENTANACONDOPS-LABEL: sub1:469; RV32XVENTANACONDOPS: # %bb.0:470; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0471; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a0472; RV32XVENTANACONDOPS-NEXT: sltu a4, a1, a3473; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a0474; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a4475; RV32XVENTANACONDOPS-NEXT: sub a0, a1, a3476; RV32XVENTANACONDOPS-NEXT: mv a1, a2477; RV32XVENTANACONDOPS-NEXT: ret478;479; RV64XVENTANACONDOPS-LABEL: sub1:480; RV64XVENTANACONDOPS: # %bb.0:481; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0482; RV64XVENTANACONDOPS-NEXT: sub a0, a1, a0483; RV64XVENTANACONDOPS-NEXT: ret484;485; RV64XTHEADCONDMOV-LABEL: sub1:486; RV64XTHEADCONDMOV: # %bb.0:487; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0488; RV64XTHEADCONDMOV-NEXT: sub a0, a1, a2489; RV64XTHEADCONDMOV-NEXT: ret490;491; RV32ZICOND-LABEL: sub1:492; RV32ZICOND: # %bb.0:493; RV32ZICOND-NEXT: czero.eqz a3, a3, a0494; RV32ZICOND-NEXT: czero.eqz a0, a4, a0495; RV32ZICOND-NEXT: sltu a4, a1, a3496; RV32ZICOND-NEXT: sub a2, a2, a0497; RV32ZICOND-NEXT: sub a2, a2, a4498; RV32ZICOND-NEXT: sub a0, a1, a3499; RV32ZICOND-NEXT: mv a1, a2500; RV32ZICOND-NEXT: ret501;502; RV64ZICOND-LABEL: sub1:503; RV64ZICOND: # %bb.0:504; RV64ZICOND-NEXT: czero.eqz a0, a2, a0505; RV64ZICOND-NEXT: sub a0, a1, a0506; RV64ZICOND-NEXT: ret507 %sub = sub i64 %rs1, %rs2508 %sel = select i1 %rc, i64 %sub, i64 %rs1509 ret i64 %sel510}511 512define i64 @sub2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {513; RV32I-LABEL: sub2:514; RV32I: # %bb.0:515; RV32I-NEXT: addi a0, a0, -1516; RV32I-NEXT: and a3, a0, a3517; RV32I-NEXT: and a0, a0, a4518; RV32I-NEXT: sltu a4, a1, a3519; RV32I-NEXT: sub a2, a2, a0520; RV32I-NEXT: sub a2, a2, a4521; RV32I-NEXT: sub a0, a1, a3522; RV32I-NEXT: mv a1, a2523; RV32I-NEXT: ret524;525; RV64I-LABEL: sub2:526; RV64I: # %bb.0:527; RV64I-NEXT: addi a0, a0, -1528; RV64I-NEXT: and a0, a0, a2529; RV64I-NEXT: sub a0, a1, a0530; RV64I-NEXT: ret531;532; RV32XVENTANACONDOPS-LABEL: sub2:533; RV32XVENTANACONDOPS: # %bb.0:534; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0535; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a0536; RV32XVENTANACONDOPS-NEXT: sltu a4, a1, a3537; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a0538; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a4539; RV32XVENTANACONDOPS-NEXT: sub a0, a1, a3540; RV32XVENTANACONDOPS-NEXT: mv a1, a2541; RV32XVENTANACONDOPS-NEXT: ret542;543; RV64XVENTANACONDOPS-LABEL: sub2:544; RV64XVENTANACONDOPS: # %bb.0:545; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0546; RV64XVENTANACONDOPS-NEXT: sub a0, a1, a0547; RV64XVENTANACONDOPS-NEXT: ret548;549; RV64XTHEADCONDMOV-LABEL: sub2:550; RV64XTHEADCONDMOV: # %bb.0:551; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0552; RV64XTHEADCONDMOV-NEXT: sub a0, a1, a2553; RV64XTHEADCONDMOV-NEXT: ret554;555; RV32ZICOND-LABEL: sub2:556; RV32ZICOND: # %bb.0:557; RV32ZICOND-NEXT: czero.nez a3, a3, a0558; RV32ZICOND-NEXT: czero.nez a0, a4, a0559; RV32ZICOND-NEXT: sltu a4, a1, a3560; RV32ZICOND-NEXT: sub a2, a2, a0561; RV32ZICOND-NEXT: sub a2, a2, a4562; RV32ZICOND-NEXT: sub a0, a1, a3563; RV32ZICOND-NEXT: mv a1, a2564; RV32ZICOND-NEXT: ret565;566; RV64ZICOND-LABEL: sub2:567; RV64ZICOND: # %bb.0:568; RV64ZICOND-NEXT: czero.nez a0, a2, a0569; RV64ZICOND-NEXT: sub a0, a1, a0570; RV64ZICOND-NEXT: ret571 %sub = sub i64 %rs1, %rs2572 %sel = select i1 %rc, i64 %rs1, i64 %sub573 ret i64 %sel574}575 576define i64 @or1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {577; RV32I-LABEL: or1:578; RV32I: # %bb.0:579; RV32I-NEXT: neg a0, a0580; RV32I-NEXT: and a3, a0, a3581; RV32I-NEXT: and a4, a0, a4582; RV32I-NEXT: or a0, a1, a3583; RV32I-NEXT: or a1, a2, a4584; RV32I-NEXT: ret585;586; RV64I-LABEL: or1:587; RV64I: # %bb.0:588; RV64I-NEXT: neg a0, a0589; RV64I-NEXT: and a0, a0, a2590; RV64I-NEXT: or a0, a1, a0591; RV64I-NEXT: ret592;593; RV32XVENTANACONDOPS-LABEL: or1:594; RV32XVENTANACONDOPS: # %bb.0:595; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0596; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a0597; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3598; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4599; RV32XVENTANACONDOPS-NEXT: ret600;601; RV64XVENTANACONDOPS-LABEL: or1:602; RV64XVENTANACONDOPS: # %bb.0:603; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0604; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0605; RV64XVENTANACONDOPS-NEXT: ret606;607; RV64XTHEADCONDMOV-LABEL: or1:608; RV64XTHEADCONDMOV: # %bb.0:609; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0610; RV64XTHEADCONDMOV-NEXT: or a0, a1, a2611; RV64XTHEADCONDMOV-NEXT: ret612;613; RV32ZICOND-LABEL: or1:614; RV32ZICOND: # %bb.0:615; RV32ZICOND-NEXT: czero.eqz a3, a3, a0616; RV32ZICOND-NEXT: czero.eqz a4, a4, a0617; RV32ZICOND-NEXT: or a0, a1, a3618; RV32ZICOND-NEXT: or a1, a2, a4619; RV32ZICOND-NEXT: ret620;621; RV64ZICOND-LABEL: or1:622; RV64ZICOND: # %bb.0:623; RV64ZICOND-NEXT: czero.eqz a0, a2, a0624; RV64ZICOND-NEXT: or a0, a1, a0625; RV64ZICOND-NEXT: ret626 %or = or i64 %rs1, %rs2627 %sel = select i1 %rc, i64 %or, i64 %rs1628 ret i64 %sel629}630 631define i64 @or2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {632; RV32I-LABEL: or2:633; RV32I: # %bb.0:634; RV32I-NEXT: neg a0, a0635; RV32I-NEXT: and a1, a0, a1636; RV32I-NEXT: and a2, a0, a2637; RV32I-NEXT: or a0, a3, a1638; RV32I-NEXT: or a1, a4, a2639; RV32I-NEXT: ret640;641; RV64I-LABEL: or2:642; RV64I: # %bb.0:643; RV64I-NEXT: neg a0, a0644; RV64I-NEXT: and a0, a0, a1645; RV64I-NEXT: or a0, a2, a0646; RV64I-NEXT: ret647;648; RV32XVENTANACONDOPS-LABEL: or2:649; RV32XVENTANACONDOPS: # %bb.0:650; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0651; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0652; RV32XVENTANACONDOPS-NEXT: or a0, a3, a1653; RV32XVENTANACONDOPS-NEXT: or a1, a4, a2654; RV32XVENTANACONDOPS-NEXT: ret655;656; RV64XVENTANACONDOPS-LABEL: or2:657; RV64XVENTANACONDOPS: # %bb.0:658; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0659; RV64XVENTANACONDOPS-NEXT: or a0, a2, a0660; RV64XVENTANACONDOPS-NEXT: ret661;662; RV64XTHEADCONDMOV-LABEL: or2:663; RV64XTHEADCONDMOV: # %bb.0:664; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0665; RV64XTHEADCONDMOV-NEXT: or a0, a2, a1666; RV64XTHEADCONDMOV-NEXT: ret667;668; RV32ZICOND-LABEL: or2:669; RV32ZICOND: # %bb.0:670; RV32ZICOND-NEXT: czero.eqz a1, a1, a0671; RV32ZICOND-NEXT: czero.eqz a2, a2, a0672; RV32ZICOND-NEXT: or a0, a3, a1673; RV32ZICOND-NEXT: or a1, a4, a2674; RV32ZICOND-NEXT: ret675;676; RV64ZICOND-LABEL: or2:677; RV64ZICOND: # %bb.0:678; RV64ZICOND-NEXT: czero.eqz a0, a1, a0679; RV64ZICOND-NEXT: or a0, a2, a0680; RV64ZICOND-NEXT: ret681 %or = or i64 %rs1, %rs2682 %sel = select i1 %rc, i64 %or, i64 %rs2683 ret i64 %sel684}685 686define i64 @or3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {687; RV32I-LABEL: or3:688; RV32I: # %bb.0:689; RV32I-NEXT: addi a0, a0, -1690; RV32I-NEXT: and a3, a0, a3691; RV32I-NEXT: and a4, a0, a4692; RV32I-NEXT: or a0, a1, a3693; RV32I-NEXT: or a1, a2, a4694; RV32I-NEXT: ret695;696; RV64I-LABEL: or3:697; RV64I: # %bb.0:698; RV64I-NEXT: addi a0, a0, -1699; RV64I-NEXT: and a0, a0, a2700; RV64I-NEXT: or a0, a1, a0701; RV64I-NEXT: ret702;703; RV32XVENTANACONDOPS-LABEL: or3:704; RV32XVENTANACONDOPS: # %bb.0:705; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0706; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0707; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3708; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4709; RV32XVENTANACONDOPS-NEXT: ret710;711; RV64XVENTANACONDOPS-LABEL: or3:712; RV64XVENTANACONDOPS: # %bb.0:713; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0714; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0715; RV64XVENTANACONDOPS-NEXT: ret716;717; RV64XTHEADCONDMOV-LABEL: or3:718; RV64XTHEADCONDMOV: # %bb.0:719; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0720; RV64XTHEADCONDMOV-NEXT: or a0, a1, a2721; RV64XTHEADCONDMOV-NEXT: ret722;723; RV32ZICOND-LABEL: or3:724; RV32ZICOND: # %bb.0:725; RV32ZICOND-NEXT: czero.nez a3, a3, a0726; RV32ZICOND-NEXT: czero.nez a4, a4, a0727; RV32ZICOND-NEXT: or a0, a1, a3728; RV32ZICOND-NEXT: or a1, a2, a4729; RV32ZICOND-NEXT: ret730;731; RV64ZICOND-LABEL: or3:732; RV64ZICOND: # %bb.0:733; RV64ZICOND-NEXT: czero.nez a0, a2, a0734; RV64ZICOND-NEXT: or a0, a1, a0735; RV64ZICOND-NEXT: ret736 %or = or i64 %rs1, %rs2737 %sel = select i1 %rc, i64 %rs1, i64 %or738 ret i64 %sel739}740 741define i64 @or4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {742; RV32I-LABEL: or4:743; RV32I: # %bb.0:744; RV32I-NEXT: addi a0, a0, -1745; RV32I-NEXT: and a1, a0, a1746; RV32I-NEXT: and a2, a0, a2747; RV32I-NEXT: or a0, a3, a1748; RV32I-NEXT: or a1, a4, a2749; RV32I-NEXT: ret750;751; RV64I-LABEL: or4:752; RV64I: # %bb.0:753; RV64I-NEXT: addi a0, a0, -1754; RV64I-NEXT: and a0, a0, a1755; RV64I-NEXT: or a0, a2, a0756; RV64I-NEXT: ret757;758; RV32XVENTANACONDOPS-LABEL: or4:759; RV32XVENTANACONDOPS: # %bb.0:760; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a0761; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0762; RV32XVENTANACONDOPS-NEXT: or a0, a3, a1763; RV32XVENTANACONDOPS-NEXT: or a1, a4, a2764; RV32XVENTANACONDOPS-NEXT: ret765;766; RV64XVENTANACONDOPS-LABEL: or4:767; RV64XVENTANACONDOPS: # %bb.0:768; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0769; RV64XVENTANACONDOPS-NEXT: or a0, a2, a0770; RV64XVENTANACONDOPS-NEXT: ret771;772; RV64XTHEADCONDMOV-LABEL: or4:773; RV64XTHEADCONDMOV: # %bb.0:774; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0775; RV64XTHEADCONDMOV-NEXT: or a0, a2, a1776; RV64XTHEADCONDMOV-NEXT: ret777;778; RV32ZICOND-LABEL: or4:779; RV32ZICOND: # %bb.0:780; RV32ZICOND-NEXT: czero.nez a1, a1, a0781; RV32ZICOND-NEXT: czero.nez a2, a2, a0782; RV32ZICOND-NEXT: or a0, a3, a1783; RV32ZICOND-NEXT: or a1, a4, a2784; RV32ZICOND-NEXT: ret785;786; RV64ZICOND-LABEL: or4:787; RV64ZICOND: # %bb.0:788; RV64ZICOND-NEXT: czero.nez a0, a1, a0789; RV64ZICOND-NEXT: or a0, a2, a0790; RV64ZICOND-NEXT: ret791 %or = or i64 %rs1, %rs2792 %sel = select i1 %rc, i64 %rs2, i64 %or793 ret i64 %sel794}795 796define i64 @xor1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {797; RV32I-LABEL: xor1:798; RV32I: # %bb.0:799; RV32I-NEXT: neg a0, a0800; RV32I-NEXT: and a3, a0, a3801; RV32I-NEXT: and a4, a0, a4802; RV32I-NEXT: xor a0, a1, a3803; RV32I-NEXT: xor a1, a2, a4804; RV32I-NEXT: ret805;806; RV64I-LABEL: xor1:807; RV64I: # %bb.0:808; RV64I-NEXT: neg a0, a0809; RV64I-NEXT: and a0, a0, a2810; RV64I-NEXT: xor a0, a1, a0811; RV64I-NEXT: ret812;813; RV32XVENTANACONDOPS-LABEL: xor1:814; RV32XVENTANACONDOPS: # %bb.0:815; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0816; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a0817; RV32XVENTANACONDOPS-NEXT: xor a0, a1, a3818; RV32XVENTANACONDOPS-NEXT: xor a1, a2, a4819; RV32XVENTANACONDOPS-NEXT: ret820;821; RV64XVENTANACONDOPS-LABEL: xor1:822; RV64XVENTANACONDOPS: # %bb.0:823; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0824; RV64XVENTANACONDOPS-NEXT: xor a0, a1, a0825; RV64XVENTANACONDOPS-NEXT: ret826;827; RV64XTHEADCONDMOV-LABEL: xor1:828; RV64XTHEADCONDMOV: # %bb.0:829; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a0830; RV64XTHEADCONDMOV-NEXT: xor a0, a1, a2831; RV64XTHEADCONDMOV-NEXT: ret832;833; RV32ZICOND-LABEL: xor1:834; RV32ZICOND: # %bb.0:835; RV32ZICOND-NEXT: czero.eqz a3, a3, a0836; RV32ZICOND-NEXT: czero.eqz a4, a4, a0837; RV32ZICOND-NEXT: xor a0, a1, a3838; RV32ZICOND-NEXT: xor a1, a2, a4839; RV32ZICOND-NEXT: ret840;841; RV64ZICOND-LABEL: xor1:842; RV64ZICOND: # %bb.0:843; RV64ZICOND-NEXT: czero.eqz a0, a2, a0844; RV64ZICOND-NEXT: xor a0, a1, a0845; RV64ZICOND-NEXT: ret846 %xor = xor i64 %rs1, %rs2847 %sel = select i1 %rc, i64 %xor, i64 %rs1848 ret i64 %sel849}850 851define i64 @xor2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {852; RV32I-LABEL: xor2:853; RV32I: # %bb.0:854; RV32I-NEXT: neg a0, a0855; RV32I-NEXT: and a1, a0, a1856; RV32I-NEXT: and a2, a0, a2857; RV32I-NEXT: xor a0, a3, a1858; RV32I-NEXT: xor a1, a4, a2859; RV32I-NEXT: ret860;861; RV64I-LABEL: xor2:862; RV64I: # %bb.0:863; RV64I-NEXT: neg a0, a0864; RV64I-NEXT: and a0, a0, a1865; RV64I-NEXT: xor a0, a2, a0866; RV64I-NEXT: ret867;868; RV32XVENTANACONDOPS-LABEL: xor2:869; RV32XVENTANACONDOPS: # %bb.0:870; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0871; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0872; RV32XVENTANACONDOPS-NEXT: xor a0, a3, a1873; RV32XVENTANACONDOPS-NEXT: xor a1, a4, a2874; RV32XVENTANACONDOPS-NEXT: ret875;876; RV64XVENTANACONDOPS-LABEL: xor2:877; RV64XVENTANACONDOPS: # %bb.0:878; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0879; RV64XVENTANACONDOPS-NEXT: xor a0, a2, a0880; RV64XVENTANACONDOPS-NEXT: ret881;882; RV64XTHEADCONDMOV-LABEL: xor2:883; RV64XTHEADCONDMOV: # %bb.0:884; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a0885; RV64XTHEADCONDMOV-NEXT: xor a0, a2, a1886; RV64XTHEADCONDMOV-NEXT: ret887;888; RV32ZICOND-LABEL: xor2:889; RV32ZICOND: # %bb.0:890; RV32ZICOND-NEXT: czero.eqz a1, a1, a0891; RV32ZICOND-NEXT: czero.eqz a2, a2, a0892; RV32ZICOND-NEXT: xor a0, a3, a1893; RV32ZICOND-NEXT: xor a1, a4, a2894; RV32ZICOND-NEXT: ret895;896; RV64ZICOND-LABEL: xor2:897; RV64ZICOND: # %bb.0:898; RV64ZICOND-NEXT: czero.eqz a0, a1, a0899; RV64ZICOND-NEXT: xor a0, a2, a0900; RV64ZICOND-NEXT: ret901 %xor = xor i64 %rs1, %rs2902 %sel = select i1 %rc, i64 %xor, i64 %rs2903 ret i64 %sel904}905 906define i64 @xor3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {907; RV32I-LABEL: xor3:908; RV32I: # %bb.0:909; RV32I-NEXT: addi a0, a0, -1910; RV32I-NEXT: and a3, a0, a3911; RV32I-NEXT: and a4, a0, a4912; RV32I-NEXT: xor a0, a1, a3913; RV32I-NEXT: xor a1, a2, a4914; RV32I-NEXT: ret915;916; RV64I-LABEL: xor3:917; RV64I: # %bb.0:918; RV64I-NEXT: addi a0, a0, -1919; RV64I-NEXT: and a0, a0, a2920; RV64I-NEXT: xor a0, a1, a0921; RV64I-NEXT: ret922;923; RV32XVENTANACONDOPS-LABEL: xor3:924; RV32XVENTANACONDOPS: # %bb.0:925; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0926; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0927; RV32XVENTANACONDOPS-NEXT: xor a0, a1, a3928; RV32XVENTANACONDOPS-NEXT: xor a1, a2, a4929; RV32XVENTANACONDOPS-NEXT: ret930;931; RV64XVENTANACONDOPS-LABEL: xor3:932; RV64XVENTANACONDOPS: # %bb.0:933; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0934; RV64XVENTANACONDOPS-NEXT: xor a0, a1, a0935; RV64XVENTANACONDOPS-NEXT: ret936;937; RV64XTHEADCONDMOV-LABEL: xor3:938; RV64XTHEADCONDMOV: # %bb.0:939; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a0940; RV64XTHEADCONDMOV-NEXT: xor a0, a1, a2941; RV64XTHEADCONDMOV-NEXT: ret942;943; RV32ZICOND-LABEL: xor3:944; RV32ZICOND: # %bb.0:945; RV32ZICOND-NEXT: czero.nez a3, a3, a0946; RV32ZICOND-NEXT: czero.nez a4, a4, a0947; RV32ZICOND-NEXT: xor a0, a1, a3948; RV32ZICOND-NEXT: xor a1, a2, a4949; RV32ZICOND-NEXT: ret950;951; RV64ZICOND-LABEL: xor3:952; RV64ZICOND: # %bb.0:953; RV64ZICOND-NEXT: czero.nez a0, a2, a0954; RV64ZICOND-NEXT: xor a0, a1, a0955; RV64ZICOND-NEXT: ret956 %xor = xor i64 %rs1, %rs2957 %sel = select i1 %rc, i64 %rs1, i64 %xor958 ret i64 %sel959}960 961define i64 @xor4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {962; RV32I-LABEL: xor4:963; RV32I: # %bb.0:964; RV32I-NEXT: addi a0, a0, -1965; RV32I-NEXT: and a1, a0, a1966; RV32I-NEXT: and a2, a0, a2967; RV32I-NEXT: xor a0, a3, a1968; RV32I-NEXT: xor a1, a4, a2969; RV32I-NEXT: ret970;971; RV64I-LABEL: xor4:972; RV64I: # %bb.0:973; RV64I-NEXT: addi a0, a0, -1974; RV64I-NEXT: and a0, a0, a1975; RV64I-NEXT: xor a0, a2, a0976; RV64I-NEXT: ret977;978; RV32XVENTANACONDOPS-LABEL: xor4:979; RV32XVENTANACONDOPS: # %bb.0:980; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a0981; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0982; RV32XVENTANACONDOPS-NEXT: xor a0, a3, a1983; RV32XVENTANACONDOPS-NEXT: xor a1, a4, a2984; RV32XVENTANACONDOPS-NEXT: ret985;986; RV64XVENTANACONDOPS-LABEL: xor4:987; RV64XVENTANACONDOPS: # %bb.0:988; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0989; RV64XVENTANACONDOPS-NEXT: xor a0, a2, a0990; RV64XVENTANACONDOPS-NEXT: ret991;992; RV64XTHEADCONDMOV-LABEL: xor4:993; RV64XTHEADCONDMOV: # %bb.0:994; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a0995; RV64XTHEADCONDMOV-NEXT: xor a0, a2, a1996; RV64XTHEADCONDMOV-NEXT: ret997;998; RV32ZICOND-LABEL: xor4:999; RV32ZICOND: # %bb.0:1000; RV32ZICOND-NEXT: czero.nez a1, a1, a01001; RV32ZICOND-NEXT: czero.nez a2, a2, a01002; RV32ZICOND-NEXT: xor a0, a3, a11003; RV32ZICOND-NEXT: xor a1, a4, a21004; RV32ZICOND-NEXT: ret1005;1006; RV64ZICOND-LABEL: xor4:1007; RV64ZICOND: # %bb.0:1008; RV64ZICOND-NEXT: czero.nez a0, a1, a01009; RV64ZICOND-NEXT: xor a0, a2, a01010; RV64ZICOND-NEXT: ret1011 %xor = xor i64 %rs1, %rs21012 %sel = select i1 %rc, i64 %rs2, i64 %xor1013 ret i64 %sel1014}1015 1016define i64 @and1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {1017; RV32I-LABEL: and1:1018; RV32I: # %bb.0:1019; RV32I-NEXT: beqz a0, .LBB18_21020; RV32I-NEXT: # %bb.1:1021; RV32I-NEXT: and a2, a2, a41022; RV32I-NEXT: and a1, a1, a31023; RV32I-NEXT: .LBB18_2:1024; RV32I-NEXT: mv a0, a11025; RV32I-NEXT: mv a1, a21026; RV32I-NEXT: ret1027;1028; RV64I-LABEL: and1:1029; RV64I: # %bb.0:1030; RV64I-NEXT: beqz a0, .LBB18_21031; RV64I-NEXT: # %bb.1:1032; RV64I-NEXT: and a1, a1, a21033; RV64I-NEXT: .LBB18_2:1034; RV64I-NEXT: mv a0, a11035; RV64I-NEXT: ret1036;1037; RV32XVENTANACONDOPS-LABEL: and1:1038; RV32XVENTANACONDOPS: # %bb.0:1039; RV32XVENTANACONDOPS-NEXT: and a4, a2, a41040; RV32XVENTANACONDOPS-NEXT: and a3, a1, a31041; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a01042; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a01043; RV32XVENTANACONDOPS-NEXT: or a0, a3, a11044; RV32XVENTANACONDOPS-NEXT: or a1, a4, a21045; RV32XVENTANACONDOPS-NEXT: ret1046;1047; RV64XVENTANACONDOPS-LABEL: and1:1048; RV64XVENTANACONDOPS: # %bb.0:1049; RV64XVENTANACONDOPS-NEXT: and a2, a1, a21050; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a01051; RV64XVENTANACONDOPS-NEXT: or a0, a2, a01052; RV64XVENTANACONDOPS-NEXT: ret1053;1054; RV64XTHEADCONDMOV-LABEL: and1:1055; RV64XTHEADCONDMOV: # %bb.0:1056; RV64XTHEADCONDMOV-NEXT: and a2, a1, a21057; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a1, a01058; RV64XTHEADCONDMOV-NEXT: mv a0, a21059; RV64XTHEADCONDMOV-NEXT: ret1060;1061; RV32ZICOND-LABEL: and1:1062; RV32ZICOND: # %bb.0:1063; RV32ZICOND-NEXT: and a4, a2, a41064; RV32ZICOND-NEXT: and a3, a1, a31065; RV32ZICOND-NEXT: czero.nez a1, a1, a01066; RV32ZICOND-NEXT: czero.nez a2, a2, a01067; RV32ZICOND-NEXT: or a0, a3, a11068; RV32ZICOND-NEXT: or a1, a4, a21069; RV32ZICOND-NEXT: ret1070;1071; RV64ZICOND-LABEL: and1:1072; RV64ZICOND: # %bb.0:1073; RV64ZICOND-NEXT: and a2, a1, a21074; RV64ZICOND-NEXT: czero.nez a0, a1, a01075; RV64ZICOND-NEXT: or a0, a2, a01076; RV64ZICOND-NEXT: ret1077 %and = and i64 %rs1, %rs21078 %sel = select i1 %rc, i64 %and, i64 %rs11079 ret i64 %sel1080}1081 1082define i64 @and2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {1083; RV32I-LABEL: and2:1084; RV32I: # %bb.0:1085; RV32I-NEXT: beqz a0, .LBB19_21086; RV32I-NEXT: # %bb.1:1087; RV32I-NEXT: and a4, a2, a41088; RV32I-NEXT: and a3, a1, a31089; RV32I-NEXT: .LBB19_2:1090; RV32I-NEXT: mv a0, a31091; RV32I-NEXT: mv a1, a41092; RV32I-NEXT: ret1093;1094; RV64I-LABEL: and2:1095; RV64I: # %bb.0:1096; RV64I-NEXT: beqz a0, .LBB19_21097; RV64I-NEXT: # %bb.1:1098; RV64I-NEXT: and a2, a1, a21099; RV64I-NEXT: .LBB19_2:1100; RV64I-NEXT: mv a0, a21101; RV64I-NEXT: ret1102;1103; RV32XVENTANACONDOPS-LABEL: and2:1104; RV32XVENTANACONDOPS: # %bb.0:1105; RV32XVENTANACONDOPS-NEXT: and a2, a2, a41106; RV32XVENTANACONDOPS-NEXT: and a1, a1, a31107; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a01108; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a01109; RV32XVENTANACONDOPS-NEXT: or a0, a1, a31110; RV32XVENTANACONDOPS-NEXT: or a1, a2, a41111; RV32XVENTANACONDOPS-NEXT: ret1112;1113; RV64XVENTANACONDOPS-LABEL: and2:1114; RV64XVENTANACONDOPS: # %bb.0:1115; RV64XVENTANACONDOPS-NEXT: and a1, a1, a21116; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a01117; RV64XVENTANACONDOPS-NEXT: or a0, a1, a01118; RV64XVENTANACONDOPS-NEXT: ret1119;1120; RV64XTHEADCONDMOV-LABEL: and2:1121; RV64XTHEADCONDMOV: # %bb.0:1122; RV64XTHEADCONDMOV-NEXT: and a1, a1, a21123; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a01124; RV64XTHEADCONDMOV-NEXT: mv a0, a11125; RV64XTHEADCONDMOV-NEXT: ret1126;1127; RV32ZICOND-LABEL: and2:1128; RV32ZICOND: # %bb.0:1129; RV32ZICOND-NEXT: and a2, a2, a41130; RV32ZICOND-NEXT: and a1, a1, a31131; RV32ZICOND-NEXT: czero.nez a3, a3, a01132; RV32ZICOND-NEXT: czero.nez a4, a4, a01133; RV32ZICOND-NEXT: or a0, a1, a31134; RV32ZICOND-NEXT: or a1, a2, a41135; RV32ZICOND-NEXT: ret1136;1137; RV64ZICOND-LABEL: and2:1138; RV64ZICOND: # %bb.0:1139; RV64ZICOND-NEXT: and a1, a1, a21140; RV64ZICOND-NEXT: czero.nez a0, a2, a01141; RV64ZICOND-NEXT: or a0, a1, a01142; RV64ZICOND-NEXT: ret1143 %and = and i64 %rs1, %rs21144 %sel = select i1 %rc, i64 %and, i64 %rs21145 ret i64 %sel1146}1147 1148define i64 @and3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {1149; RV32I-LABEL: and3:1150; RV32I: # %bb.0:1151; RV32I-NEXT: bnez a0, .LBB20_21152; RV32I-NEXT: # %bb.1:1153; RV32I-NEXT: and a2, a2, a41154; RV32I-NEXT: and a1, a1, a31155; RV32I-NEXT: .LBB20_2:1156; RV32I-NEXT: mv a0, a11157; RV32I-NEXT: mv a1, a21158; RV32I-NEXT: ret1159;1160; RV64I-LABEL: and3:1161; RV64I: # %bb.0:1162; RV64I-NEXT: bnez a0, .LBB20_21163; RV64I-NEXT: # %bb.1:1164; RV64I-NEXT: and a1, a1, a21165; RV64I-NEXT: .LBB20_2:1166; RV64I-NEXT: mv a0, a11167; RV64I-NEXT: ret1168;1169; RV32XVENTANACONDOPS-LABEL: and3:1170; RV32XVENTANACONDOPS: # %bb.0:1171; RV32XVENTANACONDOPS-NEXT: and a4, a2, a41172; RV32XVENTANACONDOPS-NEXT: and a3, a1, a31173; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a01174; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a01175; RV32XVENTANACONDOPS-NEXT: or a0, a3, a11176; RV32XVENTANACONDOPS-NEXT: or a1, a4, a21177; RV32XVENTANACONDOPS-NEXT: ret1178;1179; RV64XVENTANACONDOPS-LABEL: and3:1180; RV64XVENTANACONDOPS: # %bb.0:1181; RV64XVENTANACONDOPS-NEXT: and a2, a1, a21182; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a01183; RV64XVENTANACONDOPS-NEXT: or a0, a2, a01184; RV64XVENTANACONDOPS-NEXT: ret1185;1186; RV64XTHEADCONDMOV-LABEL: and3:1187; RV64XTHEADCONDMOV: # %bb.0:1188; RV64XTHEADCONDMOV-NEXT: and a2, a1, a21189; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a1, a01190; RV64XTHEADCONDMOV-NEXT: mv a0, a21191; RV64XTHEADCONDMOV-NEXT: ret1192;1193; RV32ZICOND-LABEL: and3:1194; RV32ZICOND: # %bb.0:1195; RV32ZICOND-NEXT: and a4, a2, a41196; RV32ZICOND-NEXT: and a3, a1, a31197; RV32ZICOND-NEXT: czero.eqz a1, a1, a01198; RV32ZICOND-NEXT: czero.eqz a2, a2, a01199; RV32ZICOND-NEXT: or a0, a3, a11200; RV32ZICOND-NEXT: or a1, a4, a21201; RV32ZICOND-NEXT: ret1202;1203; RV64ZICOND-LABEL: and3:1204; RV64ZICOND: # %bb.0:1205; RV64ZICOND-NEXT: and a2, a1, a21206; RV64ZICOND-NEXT: czero.eqz a0, a1, a01207; RV64ZICOND-NEXT: or a0, a2, a01208; RV64ZICOND-NEXT: ret1209 %and = and i64 %rs1, %rs21210 %sel = select i1 %rc, i64 %rs1, i64 %and1211 ret i64 %sel1212}1213 1214define i64 @and4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {1215; RV32I-LABEL: and4:1216; RV32I: # %bb.0:1217; RV32I-NEXT: bnez a0, .LBB21_21218; RV32I-NEXT: # %bb.1:1219; RV32I-NEXT: and a4, a2, a41220; RV32I-NEXT: and a3, a1, a31221; RV32I-NEXT: .LBB21_2:1222; RV32I-NEXT: mv a0, a31223; RV32I-NEXT: mv a1, a41224; RV32I-NEXT: ret1225;1226; RV64I-LABEL: and4:1227; RV64I: # %bb.0:1228; RV64I-NEXT: bnez a0, .LBB21_21229; RV64I-NEXT: # %bb.1:1230; RV64I-NEXT: and a2, a1, a21231; RV64I-NEXT: .LBB21_2:1232; RV64I-NEXT: mv a0, a21233; RV64I-NEXT: ret1234;1235; RV32XVENTANACONDOPS-LABEL: and4:1236; RV32XVENTANACONDOPS: # %bb.0:1237; RV32XVENTANACONDOPS-NEXT: and a2, a2, a41238; RV32XVENTANACONDOPS-NEXT: and a1, a1, a31239; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a01240; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a01241; RV32XVENTANACONDOPS-NEXT: or a0, a1, a31242; RV32XVENTANACONDOPS-NEXT: or a1, a2, a41243; RV32XVENTANACONDOPS-NEXT: ret1244;1245; RV64XVENTANACONDOPS-LABEL: and4:1246; RV64XVENTANACONDOPS: # %bb.0:1247; RV64XVENTANACONDOPS-NEXT: and a1, a1, a21248; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a01249; RV64XVENTANACONDOPS-NEXT: or a0, a1, a01250; RV64XVENTANACONDOPS-NEXT: ret1251;1252; RV64XTHEADCONDMOV-LABEL: and4:1253; RV64XTHEADCONDMOV: # %bb.0:1254; RV64XTHEADCONDMOV-NEXT: and a1, a1, a21255; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a01256; RV64XTHEADCONDMOV-NEXT: mv a0, a11257; RV64XTHEADCONDMOV-NEXT: ret1258;1259; RV32ZICOND-LABEL: and4:1260; RV32ZICOND: # %bb.0:1261; RV32ZICOND-NEXT: and a2, a2, a41262; RV32ZICOND-NEXT: and a1, a1, a31263; RV32ZICOND-NEXT: czero.eqz a3, a3, a01264; RV32ZICOND-NEXT: czero.eqz a4, a4, a01265; RV32ZICOND-NEXT: or a0, a1, a31266; RV32ZICOND-NEXT: or a1, a2, a41267; RV32ZICOND-NEXT: ret1268;1269; RV64ZICOND-LABEL: and4:1270; RV64ZICOND: # %bb.0:1271; RV64ZICOND-NEXT: and a1, a1, a21272; RV64ZICOND-NEXT: czero.eqz a0, a2, a01273; RV64ZICOND-NEXT: or a0, a1, a01274; RV64ZICOND-NEXT: ret1275 %and = and i64 %rs1, %rs21276 %sel = select i1 %rc, i64 %rs2, i64 %and1277 ret i64 %sel1278}1279 1280define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) {1281; RV32I-LABEL: basic:1282; RV32I: # %bb.0:1283; RV32I-NEXT: bnez a0, .LBB22_21284; RV32I-NEXT: # %bb.1:1285; RV32I-NEXT: mv a1, a31286; RV32I-NEXT: mv a2, a41287; RV32I-NEXT: .LBB22_2:1288; RV32I-NEXT: mv a0, a11289; RV32I-NEXT: mv a1, a21290; RV32I-NEXT: ret1291;1292; RV64I-LABEL: basic:1293; RV64I: # %bb.0:1294; RV64I-NEXT: bnez a0, .LBB22_21295; RV64I-NEXT: # %bb.1:1296; RV64I-NEXT: mv a1, a21297; RV64I-NEXT: .LBB22_2:1298; RV64I-NEXT: mv a0, a11299; RV64I-NEXT: ret1300;1301; RV32XVENTANACONDOPS-LABEL: basic:1302; RV32XVENTANACONDOPS: # %bb.0:1303; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a01304; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a01305; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a01306; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a01307; RV32XVENTANACONDOPS-NEXT: or a0, a1, a31308; RV32XVENTANACONDOPS-NEXT: or a1, a2, a41309; RV32XVENTANACONDOPS-NEXT: ret1310;1311; RV64XVENTANACONDOPS-LABEL: basic:1312; RV64XVENTANACONDOPS: # %bb.0:1313; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a01314; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a01315; RV64XVENTANACONDOPS-NEXT: or a0, a0, a21316; RV64XVENTANACONDOPS-NEXT: ret1317;1318; RV64XTHEADCONDMOV-LABEL: basic:1319; RV64XTHEADCONDMOV: # %bb.0:1320; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a01321; RV64XTHEADCONDMOV-NEXT: mv a0, a11322; RV64XTHEADCONDMOV-NEXT: ret1323;1324; RV32ZICOND-LABEL: basic:1325; RV32ZICOND: # %bb.0:1326; RV32ZICOND-NEXT: czero.nez a3, a3, a01327; RV32ZICOND-NEXT: czero.eqz a1, a1, a01328; RV32ZICOND-NEXT: czero.nez a4, a4, a01329; RV32ZICOND-NEXT: czero.eqz a2, a2, a01330; RV32ZICOND-NEXT: or a0, a1, a31331; RV32ZICOND-NEXT: or a1, a2, a41332; RV32ZICOND-NEXT: ret1333;1334; RV64ZICOND-LABEL: basic:1335; RV64ZICOND: # %bb.0:1336; RV64ZICOND-NEXT: czero.nez a2, a2, a01337; RV64ZICOND-NEXT: czero.eqz a0, a1, a01338; RV64ZICOND-NEXT: or a0, a0, a21339; RV64ZICOND-NEXT: ret1340 %sel = select i1 %rc, i64 %rs1, i64 %rs21341 ret i64 %sel1342}1343 1344define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {1345; RV32I-LABEL: seteq:1346; RV32I: # %bb.0:1347; RV32I-NEXT: xor a1, a1, a31348; RV32I-NEXT: xor a0, a0, a21349; RV32I-NEXT: or a1, a0, a11350; RV32I-NEXT: mv a0, a41351; RV32I-NEXT: beqz a1, .LBB23_21352; RV32I-NEXT: # %bb.1:1353; RV32I-NEXT: mv a0, a61354; RV32I-NEXT: mv a5, a71355; RV32I-NEXT: .LBB23_2:1356; RV32I-NEXT: mv a1, a51357; RV32I-NEXT: ret1358;1359; RV64I-LABEL: seteq:1360; RV64I: # %bb.0:1361; RV64I-NEXT: beq a0, a1, .LBB23_21362; RV64I-NEXT: # %bb.1:1363; RV64I-NEXT: mv a2, a31364; RV64I-NEXT: .LBB23_2:1365; RV64I-NEXT: mv a0, a21366; RV64I-NEXT: ret1367;1368; RV32XVENTANACONDOPS-LABEL: seteq:1369; RV32XVENTANACONDOPS: # %bb.0:1370; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a31371; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a21372; RV32XVENTANACONDOPS-NEXT: or a0, a0, a11373; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a01374; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a01375; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a01376; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a01377; RV32XVENTANACONDOPS-NEXT: or a0, a2, a11378; RV32XVENTANACONDOPS-NEXT: or a1, a4, a31379; RV32XVENTANACONDOPS-NEXT: ret1380;1381; RV64XVENTANACONDOPS-LABEL: seteq:1382; RV64XVENTANACONDOPS: # %bb.0:1383; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a11384; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a01385; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a01386; RV64XVENTANACONDOPS-NEXT: or a0, a0, a11387; RV64XVENTANACONDOPS-NEXT: ret1388;1389; RV64XTHEADCONDMOV-LABEL: seteq:1390; RV64XTHEADCONDMOV: # %bb.0:1391; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a11392; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a01393; RV64XTHEADCONDMOV-NEXT: mv a0, a21394; RV64XTHEADCONDMOV-NEXT: ret1395;1396; RV32ZICOND-LABEL: seteq:1397; RV32ZICOND: # %bb.0:1398; RV32ZICOND-NEXT: xor a1, a1, a31399; RV32ZICOND-NEXT: xor a0, a0, a21400; RV32ZICOND-NEXT: or a0, a0, a11401; RV32ZICOND-NEXT: czero.eqz a1, a6, a01402; RV32ZICOND-NEXT: czero.nez a2, a4, a01403; RV32ZICOND-NEXT: czero.eqz a3, a7, a01404; RV32ZICOND-NEXT: czero.nez a4, a5, a01405; RV32ZICOND-NEXT: or a0, a2, a11406; RV32ZICOND-NEXT: or a1, a4, a31407; RV32ZICOND-NEXT: ret1408;1409; RV64ZICOND-LABEL: seteq:1410; RV64ZICOND: # %bb.0:1411; RV64ZICOND-NEXT: xor a0, a0, a11412; RV64ZICOND-NEXT: czero.eqz a1, a3, a01413; RV64ZICOND-NEXT: czero.nez a0, a2, a01414; RV64ZICOND-NEXT: or a0, a0, a11415; RV64ZICOND-NEXT: ret1416 %rc = icmp eq i64 %a, %b1417 %sel = select i1 %rc, i64 %rs1, i64 %rs21418 ret i64 %sel1419}1420 1421define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {1422; RV32I-LABEL: setne:1423; RV32I: # %bb.0:1424; RV32I-NEXT: xor a1, a1, a31425; RV32I-NEXT: xor a0, a0, a21426; RV32I-NEXT: or a1, a0, a11427; RV32I-NEXT: mv a0, a41428; RV32I-NEXT: bnez a1, .LBB24_21429; RV32I-NEXT: # %bb.1:1430; RV32I-NEXT: mv a0, a61431; RV32I-NEXT: mv a5, a71432; RV32I-NEXT: .LBB24_2:1433; RV32I-NEXT: mv a1, a51434; RV32I-NEXT: ret1435;1436; RV64I-LABEL: setne:1437; RV64I: # %bb.0:1438; RV64I-NEXT: bne a0, a1, .LBB24_21439; RV64I-NEXT: # %bb.1:1440; RV64I-NEXT: mv a2, a31441; RV64I-NEXT: .LBB24_2:1442; RV64I-NEXT: mv a0, a21443; RV64I-NEXT: ret1444;1445; RV32XVENTANACONDOPS-LABEL: setne:1446; RV32XVENTANACONDOPS: # %bb.0:1447; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a31448; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a21449; RV32XVENTANACONDOPS-NEXT: or a0, a0, a11450; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a01451; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a01452; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a01453; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a01454; RV32XVENTANACONDOPS-NEXT: or a0, a2, a11455; RV32XVENTANACONDOPS-NEXT: or a1, a4, a31456; RV32XVENTANACONDOPS-NEXT: ret1457;1458; RV64XVENTANACONDOPS-LABEL: setne:1459; RV64XVENTANACONDOPS: # %bb.0:1460; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a11461; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a01462; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a01463; RV64XVENTANACONDOPS-NEXT: or a0, a0, a11464; RV64XVENTANACONDOPS-NEXT: ret1465;1466; RV64XTHEADCONDMOV-LABEL: setne:1467; RV64XTHEADCONDMOV: # %bb.0:1468; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a11469; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a01470; RV64XTHEADCONDMOV-NEXT: mv a0, a21471; RV64XTHEADCONDMOV-NEXT: ret1472;1473; RV32ZICOND-LABEL: setne:1474; RV32ZICOND: # %bb.0:1475; RV32ZICOND-NEXT: xor a1, a1, a31476; RV32ZICOND-NEXT: xor a0, a0, a21477; RV32ZICOND-NEXT: or a0, a0, a11478; RV32ZICOND-NEXT: czero.nez a1, a6, a01479; RV32ZICOND-NEXT: czero.eqz a2, a4, a01480; RV32ZICOND-NEXT: czero.nez a3, a7, a01481; RV32ZICOND-NEXT: czero.eqz a4, a5, a01482; RV32ZICOND-NEXT: or a0, a2, a11483; RV32ZICOND-NEXT: or a1, a4, a31484; RV32ZICOND-NEXT: ret1485;1486; RV64ZICOND-LABEL: setne:1487; RV64ZICOND: # %bb.0:1488; RV64ZICOND-NEXT: xor a0, a0, a11489; RV64ZICOND-NEXT: czero.nez a1, a3, a01490; RV64ZICOND-NEXT: czero.eqz a0, a2, a01491; RV64ZICOND-NEXT: or a0, a0, a11492; RV64ZICOND-NEXT: ret1493 %rc = icmp ne i64 %a, %b1494 %sel = select i1 %rc, i64 %rs1, i64 %rs21495 ret i64 %sel1496}1497 1498define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {1499; RV32I-LABEL: setgt:1500; RV32I: # %bb.0:1501; RV32I-NEXT: beq a1, a3, .LBB25_21502; RV32I-NEXT: # %bb.1:1503; RV32I-NEXT: slt a0, a3, a11504; RV32I-NEXT: beqz a0, .LBB25_31505; RV32I-NEXT: j .LBB25_41506; RV32I-NEXT: .LBB25_2:1507; RV32I-NEXT: sltu a0, a2, a01508; RV32I-NEXT: bnez a0, .LBB25_41509; RV32I-NEXT: .LBB25_3:1510; RV32I-NEXT: mv a4, a61511; RV32I-NEXT: mv a5, a71512; RV32I-NEXT: .LBB25_4:1513; RV32I-NEXT: mv a0, a41514; RV32I-NEXT: mv a1, a51515; RV32I-NEXT: ret1516;1517; RV64I-LABEL: setgt:1518; RV64I: # %bb.0:1519; RV64I-NEXT: blt a1, a0, .LBB25_21520; RV64I-NEXT: # %bb.1:1521; RV64I-NEXT: mv a2, a31522; RV64I-NEXT: .LBB25_2:1523; RV64I-NEXT: mv a0, a21524; RV64I-NEXT: ret1525;1526; RV32XVENTANACONDOPS-LABEL: setgt:1527; RV32XVENTANACONDOPS: # %bb.0:1528; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a31529; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a11530; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a01531; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t01532; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t01533; RV32XVENTANACONDOPS-NEXT: or a0, a0, a11534; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a01535; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a01536; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a01537; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a01538; RV32XVENTANACONDOPS-NEXT: or a0, a2, a11539; RV32XVENTANACONDOPS-NEXT: or a1, a4, a31540; RV32XVENTANACONDOPS-NEXT: ret1541;1542; RV64XVENTANACONDOPS-LABEL: setgt:1543; RV64XVENTANACONDOPS: # %bb.0:1544; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a01545; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a01546; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a01547; RV64XVENTANACONDOPS-NEXT: or a0, a0, a11548; RV64XVENTANACONDOPS-NEXT: ret1549;1550; RV64XTHEADCONDMOV-LABEL: setgt:1551; RV64XTHEADCONDMOV: # %bb.0:1552; RV64XTHEADCONDMOV-NEXT: slt a0, a1, a01553; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a01554; RV64XTHEADCONDMOV-NEXT: mv a0, a21555; RV64XTHEADCONDMOV-NEXT: ret1556;1557; RV32ZICOND-LABEL: setgt:1558; RV32ZICOND: # %bb.0:1559; RV32ZICOND-NEXT: xor t0, a1, a31560; RV32ZICOND-NEXT: slt a1, a3, a11561; RV32ZICOND-NEXT: sltu a0, a2, a01562; RV32ZICOND-NEXT: czero.eqz a1, a1, t01563; RV32ZICOND-NEXT: czero.nez a0, a0, t01564; RV32ZICOND-NEXT: or a0, a0, a11565; RV32ZICOND-NEXT: czero.nez a1, a6, a01566; RV32ZICOND-NEXT: czero.eqz a2, a4, a01567; RV32ZICOND-NEXT: czero.nez a3, a7, a01568; RV32ZICOND-NEXT: czero.eqz a4, a5, a01569; RV32ZICOND-NEXT: or a0, a2, a11570; RV32ZICOND-NEXT: or a1, a4, a31571; RV32ZICOND-NEXT: ret1572;1573; RV64ZICOND-LABEL: setgt:1574; RV64ZICOND: # %bb.0:1575; RV64ZICOND-NEXT: slt a0, a1, a01576; RV64ZICOND-NEXT: czero.nez a1, a3, a01577; RV64ZICOND-NEXT: czero.eqz a0, a2, a01578; RV64ZICOND-NEXT: or a0, a0, a11579; RV64ZICOND-NEXT: ret1580 %rc = icmp sgt i64 %a, %b1581 %sel = select i1 %rc, i64 %rs1, i64 %rs21582 ret i64 %sel1583}1584 1585define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {1586; RV32I-LABEL: setge:1587; RV32I: # %bb.0:1588; RV32I-NEXT: beq a1, a3, .LBB26_21589; RV32I-NEXT: # %bb.1:1590; RV32I-NEXT: slt a0, a1, a31591; RV32I-NEXT: bnez a0, .LBB26_31592; RV32I-NEXT: j .LBB26_41593; RV32I-NEXT: .LBB26_2:1594; RV32I-NEXT: sltu a0, a0, a21595; RV32I-NEXT: beqz a0, .LBB26_41596; RV32I-NEXT: .LBB26_3:1597; RV32I-NEXT: mv a4, a61598; RV32I-NEXT: mv a5, a71599; RV32I-NEXT: .LBB26_4:1600; RV32I-NEXT: mv a0, a41601; RV32I-NEXT: mv a1, a51602; RV32I-NEXT: ret1603;1604; RV64I-LABEL: setge:1605; RV64I: # %bb.0:1606; RV64I-NEXT: bge a0, a1, .LBB26_21607; RV64I-NEXT: # %bb.1:1608; RV64I-NEXT: mv a2, a31609; RV64I-NEXT: .LBB26_2:1610; RV64I-NEXT: mv a0, a21611; RV64I-NEXT: ret1612;1613; RV32XVENTANACONDOPS-LABEL: setge:1614; RV32XVENTANACONDOPS: # %bb.0:1615; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a31616; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a31617; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a21618; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t01619; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t01620; RV32XVENTANACONDOPS-NEXT: or a0, a0, a11621; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a01622; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a01623; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a01624; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a01625; RV32XVENTANACONDOPS-NEXT: or a0, a2, a11626; RV32XVENTANACONDOPS-NEXT: or a1, a4, a31627; RV32XVENTANACONDOPS-NEXT: ret1628;1629; RV64XVENTANACONDOPS-LABEL: setge:1630; RV64XVENTANACONDOPS: # %bb.0:1631; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a11632; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a01633; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a01634; RV64XVENTANACONDOPS-NEXT: or a0, a0, a11635; RV64XVENTANACONDOPS-NEXT: ret1636;1637; RV64XTHEADCONDMOV-LABEL: setge:1638; RV64XTHEADCONDMOV: # %bb.0:1639; RV64XTHEADCONDMOV-NEXT: slt a0, a0, a11640; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a01641; RV64XTHEADCONDMOV-NEXT: mv a0, a21642; RV64XTHEADCONDMOV-NEXT: ret1643;1644; RV32ZICOND-LABEL: setge:1645; RV32ZICOND: # %bb.0:1646; RV32ZICOND-NEXT: xor t0, a1, a31647; RV32ZICOND-NEXT: slt a1, a1, a31648; RV32ZICOND-NEXT: sltu a0, a0, a21649; RV32ZICOND-NEXT: czero.eqz a1, a1, t01650; RV32ZICOND-NEXT: czero.nez a0, a0, t01651; RV32ZICOND-NEXT: or a0, a0, a11652; RV32ZICOND-NEXT: czero.eqz a1, a6, a01653; RV32ZICOND-NEXT: czero.nez a2, a4, a01654; RV32ZICOND-NEXT: czero.eqz a3, a7, a01655; RV32ZICOND-NEXT: czero.nez a4, a5, a01656; RV32ZICOND-NEXT: or a0, a2, a11657; RV32ZICOND-NEXT: or a1, a4, a31658; RV32ZICOND-NEXT: ret1659;1660; RV64ZICOND-LABEL: setge:1661; RV64ZICOND: # %bb.0:1662; RV64ZICOND-NEXT: slt a0, a0, a11663; RV64ZICOND-NEXT: czero.eqz a1, a3, a01664; RV64ZICOND-NEXT: czero.nez a0, a2, a01665; RV64ZICOND-NEXT: or a0, a0, a11666; RV64ZICOND-NEXT: ret1667 %rc = icmp sge i64 %a, %b1668 %sel = select i1 %rc, i64 %rs1, i64 %rs21669 ret i64 %sel1670}1671 1672define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {1673; RV32I-LABEL: setlt:1674; RV32I: # %bb.0:1675; RV32I-NEXT: beq a1, a3, .LBB27_21676; RV32I-NEXT: # %bb.1:1677; RV32I-NEXT: slt a0, a1, a31678; RV32I-NEXT: beqz a0, .LBB27_31679; RV32I-NEXT: j .LBB27_41680; RV32I-NEXT: .LBB27_2:1681; RV32I-NEXT: sltu a0, a0, a21682; RV32I-NEXT: bnez a0, .LBB27_41683; RV32I-NEXT: .LBB27_3:1684; RV32I-NEXT: mv a4, a61685; RV32I-NEXT: mv a5, a71686; RV32I-NEXT: .LBB27_4:1687; RV32I-NEXT: mv a0, a41688; RV32I-NEXT: mv a1, a51689; RV32I-NEXT: ret1690;1691; RV64I-LABEL: setlt:1692; RV64I: # %bb.0:1693; RV64I-NEXT: blt a0, a1, .LBB27_21694; RV64I-NEXT: # %bb.1:1695; RV64I-NEXT: mv a2, a31696; RV64I-NEXT: .LBB27_2:1697; RV64I-NEXT: mv a0, a21698; RV64I-NEXT: ret1699;1700; RV32XVENTANACONDOPS-LABEL: setlt:1701; RV32XVENTANACONDOPS: # %bb.0:1702; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a31703; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a31704; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a21705; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t01706; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t01707; RV32XVENTANACONDOPS-NEXT: or a0, a0, a11708; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a01709; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a01710; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a01711; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a01712; RV32XVENTANACONDOPS-NEXT: or a0, a2, a11713; RV32XVENTANACONDOPS-NEXT: or a1, a4, a31714; RV32XVENTANACONDOPS-NEXT: ret1715;1716; RV64XVENTANACONDOPS-LABEL: setlt:1717; RV64XVENTANACONDOPS: # %bb.0:1718; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a11719; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a01720; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a01721; RV64XVENTANACONDOPS-NEXT: or a0, a0, a11722; RV64XVENTANACONDOPS-NEXT: ret1723;1724; RV64XTHEADCONDMOV-LABEL: setlt:1725; RV64XTHEADCONDMOV: # %bb.0:1726; RV64XTHEADCONDMOV-NEXT: slt a0, a0, a11727; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a01728; RV64XTHEADCONDMOV-NEXT: mv a0, a21729; RV64XTHEADCONDMOV-NEXT: ret1730;1731; RV32ZICOND-LABEL: setlt:1732; RV32ZICOND: # %bb.0:1733; RV32ZICOND-NEXT: xor t0, a1, a31734; RV32ZICOND-NEXT: slt a1, a1, a31735; RV32ZICOND-NEXT: sltu a0, a0, a21736; RV32ZICOND-NEXT: czero.eqz a1, a1, t01737; RV32ZICOND-NEXT: czero.nez a0, a0, t01738; RV32ZICOND-NEXT: or a0, a0, a11739; RV32ZICOND-NEXT: czero.nez a1, a6, a01740; RV32ZICOND-NEXT: czero.eqz a2, a4, a01741; RV32ZICOND-NEXT: czero.nez a3, a7, a01742; RV32ZICOND-NEXT: czero.eqz a4, a5, a01743; RV32ZICOND-NEXT: or a0, a2, a11744; RV32ZICOND-NEXT: or a1, a4, a31745; RV32ZICOND-NEXT: ret1746;1747; RV64ZICOND-LABEL: setlt:1748; RV64ZICOND: # %bb.0:1749; RV64ZICOND-NEXT: slt a0, a0, a11750; RV64ZICOND-NEXT: czero.nez a1, a3, a01751; RV64ZICOND-NEXT: czero.eqz a0, a2, a01752; RV64ZICOND-NEXT: or a0, a0, a11753; RV64ZICOND-NEXT: ret1754 %rc = icmp slt i64 %a, %b1755 %sel = select i1 %rc, i64 %rs1, i64 %rs21756 ret i64 %sel1757}1758 1759define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {1760; RV32I-LABEL: setle:1761; RV32I: # %bb.0:1762; RV32I-NEXT: beq a1, a3, .LBB28_21763; RV32I-NEXT: # %bb.1:1764; RV32I-NEXT: slt a0, a3, a11765; RV32I-NEXT: bnez a0, .LBB28_31766; RV32I-NEXT: j .LBB28_41767; RV32I-NEXT: .LBB28_2:1768; RV32I-NEXT: sltu a0, a2, a01769; RV32I-NEXT: beqz a0, .LBB28_41770; RV32I-NEXT: .LBB28_3:1771; RV32I-NEXT: mv a4, a61772; RV32I-NEXT: mv a5, a71773; RV32I-NEXT: .LBB28_4:1774; RV32I-NEXT: mv a0, a41775; RV32I-NEXT: mv a1, a51776; RV32I-NEXT: ret1777;1778; RV64I-LABEL: setle:1779; RV64I: # %bb.0:1780; RV64I-NEXT: bge a1, a0, .LBB28_21781; RV64I-NEXT: # %bb.1:1782; RV64I-NEXT: mv a2, a31783; RV64I-NEXT: .LBB28_2:1784; RV64I-NEXT: mv a0, a21785; RV64I-NEXT: ret1786;1787; RV32XVENTANACONDOPS-LABEL: setle:1788; RV32XVENTANACONDOPS: # %bb.0:1789; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a31790; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a11791; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a01792; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t01793; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t01794; RV32XVENTANACONDOPS-NEXT: or a0, a0, a11795; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a01796; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a01797; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a01798; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a01799; RV32XVENTANACONDOPS-NEXT: or a0, a2, a11800; RV32XVENTANACONDOPS-NEXT: or a1, a4, a31801; RV32XVENTANACONDOPS-NEXT: ret1802;1803; RV64XVENTANACONDOPS-LABEL: setle:1804; RV64XVENTANACONDOPS: # %bb.0:1805; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a01806; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a01807; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a01808; RV64XVENTANACONDOPS-NEXT: or a0, a0, a11809; RV64XVENTANACONDOPS-NEXT: ret1810;1811; RV64XTHEADCONDMOV-LABEL: setle:1812; RV64XTHEADCONDMOV: # %bb.0:1813; RV64XTHEADCONDMOV-NEXT: slt a0, a1, a01814; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a01815; RV64XTHEADCONDMOV-NEXT: mv a0, a21816; RV64XTHEADCONDMOV-NEXT: ret1817;1818; RV32ZICOND-LABEL: setle:1819; RV32ZICOND: # %bb.0:1820; RV32ZICOND-NEXT: xor t0, a1, a31821; RV32ZICOND-NEXT: slt a1, a3, a11822; RV32ZICOND-NEXT: sltu a0, a2, a01823; RV32ZICOND-NEXT: czero.eqz a1, a1, t01824; RV32ZICOND-NEXT: czero.nez a0, a0, t01825; RV32ZICOND-NEXT: or a0, a0, a11826; RV32ZICOND-NEXT: czero.eqz a1, a6, a01827; RV32ZICOND-NEXT: czero.nez a2, a4, a01828; RV32ZICOND-NEXT: czero.eqz a3, a7, a01829; RV32ZICOND-NEXT: czero.nez a4, a5, a01830; RV32ZICOND-NEXT: or a0, a2, a11831; RV32ZICOND-NEXT: or a1, a4, a31832; RV32ZICOND-NEXT: ret1833;1834; RV64ZICOND-LABEL: setle:1835; RV64ZICOND: # %bb.0:1836; RV64ZICOND-NEXT: slt a0, a1, a01837; RV64ZICOND-NEXT: czero.eqz a1, a3, a01838; RV64ZICOND-NEXT: czero.nez a0, a2, a01839; RV64ZICOND-NEXT: or a0, a0, a11840; RV64ZICOND-NEXT: ret1841 %rc = icmp sle i64 %a, %b1842 %sel = select i1 %rc, i64 %rs1, i64 %rs21843 ret i64 %sel1844}1845 1846define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {1847; RV32I-LABEL: setugt:1848; RV32I: # %bb.0:1849; RV32I-NEXT: beq a1, a3, .LBB29_21850; RV32I-NEXT: # %bb.1:1851; RV32I-NEXT: sltu a0, a3, a11852; RV32I-NEXT: beqz a0, .LBB29_31853; RV32I-NEXT: j .LBB29_41854; RV32I-NEXT: .LBB29_2:1855; RV32I-NEXT: sltu a0, a2, a01856; RV32I-NEXT: bnez a0, .LBB29_41857; RV32I-NEXT: .LBB29_3:1858; RV32I-NEXT: mv a4, a61859; RV32I-NEXT: mv a5, a71860; RV32I-NEXT: .LBB29_4:1861; RV32I-NEXT: mv a0, a41862; RV32I-NEXT: mv a1, a51863; RV32I-NEXT: ret1864;1865; RV64I-LABEL: setugt:1866; RV64I: # %bb.0:1867; RV64I-NEXT: bltu a1, a0, .LBB29_21868; RV64I-NEXT: # %bb.1:1869; RV64I-NEXT: mv a2, a31870; RV64I-NEXT: .LBB29_2:1871; RV64I-NEXT: mv a0, a21872; RV64I-NEXT: ret1873;1874; RV32XVENTANACONDOPS-LABEL: setugt:1875; RV32XVENTANACONDOPS: # %bb.0:1876; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a31877; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a11878; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a01879; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t01880; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t01881; RV32XVENTANACONDOPS-NEXT: or a0, a0, a11882; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a01883; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a01884; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a01885; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a01886; RV32XVENTANACONDOPS-NEXT: or a0, a2, a11887; RV32XVENTANACONDOPS-NEXT: or a1, a4, a31888; RV32XVENTANACONDOPS-NEXT: ret1889;1890; RV64XVENTANACONDOPS-LABEL: setugt:1891; RV64XVENTANACONDOPS: # %bb.0:1892; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a01893; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a01894; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a01895; RV64XVENTANACONDOPS-NEXT: or a0, a0, a11896; RV64XVENTANACONDOPS-NEXT: ret1897;1898; RV64XTHEADCONDMOV-LABEL: setugt:1899; RV64XTHEADCONDMOV: # %bb.0:1900; RV64XTHEADCONDMOV-NEXT: sltu a0, a1, a01901; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a01902; RV64XTHEADCONDMOV-NEXT: mv a0, a21903; RV64XTHEADCONDMOV-NEXT: ret1904;1905; RV32ZICOND-LABEL: setugt:1906; RV32ZICOND: # %bb.0:1907; RV32ZICOND-NEXT: xor t0, a1, a31908; RV32ZICOND-NEXT: sltu a1, a3, a11909; RV32ZICOND-NEXT: sltu a0, a2, a01910; RV32ZICOND-NEXT: czero.eqz a1, a1, t01911; RV32ZICOND-NEXT: czero.nez a0, a0, t01912; RV32ZICOND-NEXT: or a0, a0, a11913; RV32ZICOND-NEXT: czero.nez a1, a6, a01914; RV32ZICOND-NEXT: czero.eqz a2, a4, a01915; RV32ZICOND-NEXT: czero.nez a3, a7, a01916; RV32ZICOND-NEXT: czero.eqz a4, a5, a01917; RV32ZICOND-NEXT: or a0, a2, a11918; RV32ZICOND-NEXT: or a1, a4, a31919; RV32ZICOND-NEXT: ret1920;1921; RV64ZICOND-LABEL: setugt:1922; RV64ZICOND: # %bb.0:1923; RV64ZICOND-NEXT: sltu a0, a1, a01924; RV64ZICOND-NEXT: czero.nez a1, a3, a01925; RV64ZICOND-NEXT: czero.eqz a0, a2, a01926; RV64ZICOND-NEXT: or a0, a0, a11927; RV64ZICOND-NEXT: ret1928 %rc = icmp ugt i64 %a, %b1929 %sel = select i1 %rc, i64 %rs1, i64 %rs21930 ret i64 %sel1931}1932 1933define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {1934; RV32I-LABEL: setuge:1935; RV32I: # %bb.0:1936; RV32I-NEXT: beq a1, a3, .LBB30_21937; RV32I-NEXT: # %bb.1:1938; RV32I-NEXT: sltu a0, a1, a31939; RV32I-NEXT: bnez a0, .LBB30_31940; RV32I-NEXT: j .LBB30_41941; RV32I-NEXT: .LBB30_2:1942; RV32I-NEXT: sltu a0, a0, a21943; RV32I-NEXT: beqz a0, .LBB30_41944; RV32I-NEXT: .LBB30_3:1945; RV32I-NEXT: mv a4, a61946; RV32I-NEXT: mv a5, a71947; RV32I-NEXT: .LBB30_4:1948; RV32I-NEXT: mv a0, a41949; RV32I-NEXT: mv a1, a51950; RV32I-NEXT: ret1951;1952; RV64I-LABEL: setuge:1953; RV64I: # %bb.0:1954; RV64I-NEXT: bgeu a0, a1, .LBB30_21955; RV64I-NEXT: # %bb.1:1956; RV64I-NEXT: mv a2, a31957; RV64I-NEXT: .LBB30_2:1958; RV64I-NEXT: mv a0, a21959; RV64I-NEXT: ret1960;1961; RV32XVENTANACONDOPS-LABEL: setuge:1962; RV32XVENTANACONDOPS: # %bb.0:1963; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a31964; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a31965; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a21966; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t01967; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t01968; RV32XVENTANACONDOPS-NEXT: or a0, a0, a11969; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a01970; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a01971; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a01972; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a01973; RV32XVENTANACONDOPS-NEXT: or a0, a2, a11974; RV32XVENTANACONDOPS-NEXT: or a1, a4, a31975; RV32XVENTANACONDOPS-NEXT: ret1976;1977; RV64XVENTANACONDOPS-LABEL: setuge:1978; RV64XVENTANACONDOPS: # %bb.0:1979; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a11980; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a01981; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a01982; RV64XVENTANACONDOPS-NEXT: or a0, a0, a11983; RV64XVENTANACONDOPS-NEXT: ret1984;1985; RV64XTHEADCONDMOV-LABEL: setuge:1986; RV64XTHEADCONDMOV: # %bb.0:1987; RV64XTHEADCONDMOV-NEXT: sltu a0, a0, a11988; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a01989; RV64XTHEADCONDMOV-NEXT: mv a0, a21990; RV64XTHEADCONDMOV-NEXT: ret1991;1992; RV32ZICOND-LABEL: setuge:1993; RV32ZICOND: # %bb.0:1994; RV32ZICOND-NEXT: xor t0, a1, a31995; RV32ZICOND-NEXT: sltu a1, a1, a31996; RV32ZICOND-NEXT: sltu a0, a0, a21997; RV32ZICOND-NEXT: czero.eqz a1, a1, t01998; RV32ZICOND-NEXT: czero.nez a0, a0, t01999; RV32ZICOND-NEXT: or a0, a0, a12000; RV32ZICOND-NEXT: czero.eqz a1, a6, a02001; RV32ZICOND-NEXT: czero.nez a2, a4, a02002; RV32ZICOND-NEXT: czero.eqz a3, a7, a02003; RV32ZICOND-NEXT: czero.nez a4, a5, a02004; RV32ZICOND-NEXT: or a0, a2, a12005; RV32ZICOND-NEXT: or a1, a4, a32006; RV32ZICOND-NEXT: ret2007;2008; RV64ZICOND-LABEL: setuge:2009; RV64ZICOND: # %bb.0:2010; RV64ZICOND-NEXT: sltu a0, a0, a12011; RV64ZICOND-NEXT: czero.eqz a1, a3, a02012; RV64ZICOND-NEXT: czero.nez a0, a2, a02013; RV64ZICOND-NEXT: or a0, a0, a12014; RV64ZICOND-NEXT: ret2015 %rc = icmp uge i64 %a, %b2016 %sel = select i1 %rc, i64 %rs1, i64 %rs22017 ret i64 %sel2018}2019 2020define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {2021; RV32I-LABEL: setult:2022; RV32I: # %bb.0:2023; RV32I-NEXT: beq a1, a3, .LBB31_22024; RV32I-NEXT: # %bb.1:2025; RV32I-NEXT: sltu a0, a1, a32026; RV32I-NEXT: beqz a0, .LBB31_32027; RV32I-NEXT: j .LBB31_42028; RV32I-NEXT: .LBB31_2:2029; RV32I-NEXT: sltu a0, a0, a22030; RV32I-NEXT: bnez a0, .LBB31_42031; RV32I-NEXT: .LBB31_3:2032; RV32I-NEXT: mv a4, a62033; RV32I-NEXT: mv a5, a72034; RV32I-NEXT: .LBB31_4:2035; RV32I-NEXT: mv a0, a42036; RV32I-NEXT: mv a1, a52037; RV32I-NEXT: ret2038;2039; RV64I-LABEL: setult:2040; RV64I: # %bb.0:2041; RV64I-NEXT: bltu a0, a1, .LBB31_22042; RV64I-NEXT: # %bb.1:2043; RV64I-NEXT: mv a2, a32044; RV64I-NEXT: .LBB31_2:2045; RV64I-NEXT: mv a0, a22046; RV64I-NEXT: ret2047;2048; RV32XVENTANACONDOPS-LABEL: setult:2049; RV32XVENTANACONDOPS: # %bb.0:2050; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a32051; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a32052; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a22053; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t02054; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t02055; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12056; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a02057; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a02058; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a02059; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a02060; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12061; RV32XVENTANACONDOPS-NEXT: or a1, a4, a32062; RV32XVENTANACONDOPS-NEXT: ret2063;2064; RV64XVENTANACONDOPS-LABEL: setult:2065; RV64XVENTANACONDOPS: # %bb.0:2066; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a12067; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a02068; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a02069; RV64XVENTANACONDOPS-NEXT: or a0, a0, a12070; RV64XVENTANACONDOPS-NEXT: ret2071;2072; RV64XTHEADCONDMOV-LABEL: setult:2073; RV64XTHEADCONDMOV: # %bb.0:2074; RV64XTHEADCONDMOV-NEXT: sltu a0, a0, a12075; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, a3, a02076; RV64XTHEADCONDMOV-NEXT: mv a0, a22077; RV64XTHEADCONDMOV-NEXT: ret2078;2079; RV32ZICOND-LABEL: setult:2080; RV32ZICOND: # %bb.0:2081; RV32ZICOND-NEXT: xor t0, a1, a32082; RV32ZICOND-NEXT: sltu a1, a1, a32083; RV32ZICOND-NEXT: sltu a0, a0, a22084; RV32ZICOND-NEXT: czero.eqz a1, a1, t02085; RV32ZICOND-NEXT: czero.nez a0, a0, t02086; RV32ZICOND-NEXT: or a0, a0, a12087; RV32ZICOND-NEXT: czero.nez a1, a6, a02088; RV32ZICOND-NEXT: czero.eqz a2, a4, a02089; RV32ZICOND-NEXT: czero.nez a3, a7, a02090; RV32ZICOND-NEXT: czero.eqz a4, a5, a02091; RV32ZICOND-NEXT: or a0, a2, a12092; RV32ZICOND-NEXT: or a1, a4, a32093; RV32ZICOND-NEXT: ret2094;2095; RV64ZICOND-LABEL: setult:2096; RV64ZICOND: # %bb.0:2097; RV64ZICOND-NEXT: sltu a0, a0, a12098; RV64ZICOND-NEXT: czero.nez a1, a3, a02099; RV64ZICOND-NEXT: czero.eqz a0, a2, a02100; RV64ZICOND-NEXT: or a0, a0, a12101; RV64ZICOND-NEXT: ret2102 %rc = icmp ult i64 %a, %b2103 %sel = select i1 %rc, i64 %rs1, i64 %rs22104 ret i64 %sel2105}2106 2107define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {2108; RV32I-LABEL: setule:2109; RV32I: # %bb.0:2110; RV32I-NEXT: beq a1, a3, .LBB32_22111; RV32I-NEXT: # %bb.1:2112; RV32I-NEXT: sltu a0, a3, a12113; RV32I-NEXT: bnez a0, .LBB32_32114; RV32I-NEXT: j .LBB32_42115; RV32I-NEXT: .LBB32_2:2116; RV32I-NEXT: sltu a0, a2, a02117; RV32I-NEXT: beqz a0, .LBB32_42118; RV32I-NEXT: .LBB32_3:2119; RV32I-NEXT: mv a4, a62120; RV32I-NEXT: mv a5, a72121; RV32I-NEXT: .LBB32_4:2122; RV32I-NEXT: mv a0, a42123; RV32I-NEXT: mv a1, a52124; RV32I-NEXT: ret2125;2126; RV64I-LABEL: setule:2127; RV64I: # %bb.0:2128; RV64I-NEXT: bgeu a1, a0, .LBB32_22129; RV64I-NEXT: # %bb.1:2130; RV64I-NEXT: mv a2, a32131; RV64I-NEXT: .LBB32_2:2132; RV64I-NEXT: mv a0, a22133; RV64I-NEXT: ret2134;2135; RV32XVENTANACONDOPS-LABEL: setule:2136; RV32XVENTANACONDOPS: # %bb.0:2137; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a32138; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a12139; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a02140; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t02141; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t02142; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12143; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a02144; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a02145; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a02146; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a02147; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12148; RV32XVENTANACONDOPS-NEXT: or a1, a4, a32149; RV32XVENTANACONDOPS-NEXT: ret2150;2151; RV64XVENTANACONDOPS-LABEL: setule:2152; RV64XVENTANACONDOPS: # %bb.0:2153; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a02154; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a02155; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a02156; RV64XVENTANACONDOPS-NEXT: or a0, a0, a12157; RV64XVENTANACONDOPS-NEXT: ret2158;2159; RV64XTHEADCONDMOV-LABEL: setule:2160; RV64XTHEADCONDMOV: # %bb.0:2161; RV64XTHEADCONDMOV-NEXT: sltu a0, a1, a02162; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a02163; RV64XTHEADCONDMOV-NEXT: mv a0, a22164; RV64XTHEADCONDMOV-NEXT: ret2165;2166; RV32ZICOND-LABEL: setule:2167; RV32ZICOND: # %bb.0:2168; RV32ZICOND-NEXT: xor t0, a1, a32169; RV32ZICOND-NEXT: sltu a1, a3, a12170; RV32ZICOND-NEXT: sltu a0, a2, a02171; RV32ZICOND-NEXT: czero.eqz a1, a1, t02172; RV32ZICOND-NEXT: czero.nez a0, a0, t02173; RV32ZICOND-NEXT: or a0, a0, a12174; RV32ZICOND-NEXT: czero.eqz a1, a6, a02175; RV32ZICOND-NEXT: czero.nez a2, a4, a02176; RV32ZICOND-NEXT: czero.eqz a3, a7, a02177; RV32ZICOND-NEXT: czero.nez a4, a5, a02178; RV32ZICOND-NEXT: or a0, a2, a12179; RV32ZICOND-NEXT: or a1, a4, a32180; RV32ZICOND-NEXT: ret2181;2182; RV64ZICOND-LABEL: setule:2183; RV64ZICOND: # %bb.0:2184; RV64ZICOND-NEXT: sltu a0, a1, a02185; RV64ZICOND-NEXT: czero.eqz a1, a3, a02186; RV64ZICOND-NEXT: czero.nez a0, a2, a02187; RV64ZICOND-NEXT: or a0, a0, a12188; RV64ZICOND-NEXT: ret2189 %rc = icmp ule i64 %a, %b2190 %sel = select i1 %rc, i64 %rs1, i64 %rs22191 ret i64 %sel2192}2193 2194define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {2195; RV32I-LABEL: seteq_zero:2196; RV32I: # %bb.0:2197; RV32I-NEXT: or a1, a0, a12198; RV32I-NEXT: mv a0, a22199; RV32I-NEXT: beqz a1, .LBB33_22200; RV32I-NEXT: # %bb.1:2201; RV32I-NEXT: mv a0, a42202; RV32I-NEXT: mv a3, a52203; RV32I-NEXT: .LBB33_2:2204; RV32I-NEXT: mv a1, a32205; RV32I-NEXT: ret2206;2207; RV64I-LABEL: seteq_zero:2208; RV64I: # %bb.0:2209; RV64I-NEXT: beqz a0, .LBB33_22210; RV64I-NEXT: # %bb.1:2211; RV64I-NEXT: mv a1, a22212; RV64I-NEXT: .LBB33_2:2213; RV64I-NEXT: mv a0, a12214; RV64I-NEXT: ret2215;2216; RV32XVENTANACONDOPS-LABEL: seteq_zero:2217; RV32XVENTANACONDOPS: # %bb.0:2218; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12219; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a02220; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a02221; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a02222; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a02223; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12224; RV32XVENTANACONDOPS-NEXT: or a1, a3, a42225; RV32XVENTANACONDOPS-NEXT: ret2226;2227; RV64XVENTANACONDOPS-LABEL: seteq_zero:2228; RV64XVENTANACONDOPS: # %bb.0:2229; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a02230; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a02231; RV64XVENTANACONDOPS-NEXT: or a0, a0, a22232; RV64XVENTANACONDOPS-NEXT: ret2233;2234; RV64XTHEADCONDMOV-LABEL: seteq_zero:2235; RV64XTHEADCONDMOV: # %bb.0:2236; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a02237; RV64XTHEADCONDMOV-NEXT: mv a0, a12238; RV64XTHEADCONDMOV-NEXT: ret2239;2240; RV32ZICOND-LABEL: seteq_zero:2241; RV32ZICOND: # %bb.0:2242; RV32ZICOND-NEXT: or a0, a0, a12243; RV32ZICOND-NEXT: czero.eqz a1, a4, a02244; RV32ZICOND-NEXT: czero.nez a2, a2, a02245; RV32ZICOND-NEXT: czero.eqz a4, a5, a02246; RV32ZICOND-NEXT: czero.nez a3, a3, a02247; RV32ZICOND-NEXT: or a0, a2, a12248; RV32ZICOND-NEXT: or a1, a3, a42249; RV32ZICOND-NEXT: ret2250;2251; RV64ZICOND-LABEL: seteq_zero:2252; RV64ZICOND: # %bb.0:2253; RV64ZICOND-NEXT: czero.eqz a2, a2, a02254; RV64ZICOND-NEXT: czero.nez a0, a1, a02255; RV64ZICOND-NEXT: or a0, a0, a22256; RV64ZICOND-NEXT: ret2257 %rc = icmp eq i64 %a, 02258 %sel = select i1 %rc, i64 %rs1, i64 %rs22259 ret i64 %sel2260}2261 2262define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) {2263; RV32I-LABEL: setne_zero:2264; RV32I: # %bb.0:2265; RV32I-NEXT: or a1, a0, a12266; RV32I-NEXT: mv a0, a22267; RV32I-NEXT: bnez a1, .LBB34_22268; RV32I-NEXT: # %bb.1:2269; RV32I-NEXT: mv a0, a42270; RV32I-NEXT: mv a3, a52271; RV32I-NEXT: .LBB34_2:2272; RV32I-NEXT: mv a1, a32273; RV32I-NEXT: ret2274;2275; RV64I-LABEL: setne_zero:2276; RV64I: # %bb.0:2277; RV64I-NEXT: bnez a0, .LBB34_22278; RV64I-NEXT: # %bb.1:2279; RV64I-NEXT: mv a1, a22280; RV64I-NEXT: .LBB34_2:2281; RV64I-NEXT: mv a0, a12282; RV64I-NEXT: ret2283;2284; RV32XVENTANACONDOPS-LABEL: setne_zero:2285; RV32XVENTANACONDOPS: # %bb.0:2286; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12287; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a02288; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a02289; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a02290; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a02291; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12292; RV32XVENTANACONDOPS-NEXT: or a1, a3, a42293; RV32XVENTANACONDOPS-NEXT: ret2294;2295; RV64XVENTANACONDOPS-LABEL: setne_zero:2296; RV64XVENTANACONDOPS: # %bb.0:2297; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a02298; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a02299; RV64XVENTANACONDOPS-NEXT: or a0, a0, a22300; RV64XVENTANACONDOPS-NEXT: ret2301;2302; RV64XTHEADCONDMOV-LABEL: setne_zero:2303; RV64XTHEADCONDMOV: # %bb.0:2304; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a02305; RV64XTHEADCONDMOV-NEXT: mv a0, a12306; RV64XTHEADCONDMOV-NEXT: ret2307;2308; RV32ZICOND-LABEL: setne_zero:2309; RV32ZICOND: # %bb.0:2310; RV32ZICOND-NEXT: or a0, a0, a12311; RV32ZICOND-NEXT: czero.nez a1, a4, a02312; RV32ZICOND-NEXT: czero.eqz a2, a2, a02313; RV32ZICOND-NEXT: czero.nez a4, a5, a02314; RV32ZICOND-NEXT: czero.eqz a3, a3, a02315; RV32ZICOND-NEXT: or a0, a2, a12316; RV32ZICOND-NEXT: or a1, a3, a42317; RV32ZICOND-NEXT: ret2318;2319; RV64ZICOND-LABEL: setne_zero:2320; RV64ZICOND: # %bb.0:2321; RV64ZICOND-NEXT: czero.nez a2, a2, a02322; RV64ZICOND-NEXT: czero.eqz a0, a1, a02323; RV64ZICOND-NEXT: or a0, a0, a22324; RV64ZICOND-NEXT: ret2325 %rc = icmp ne i64 %a, 02326 %sel = select i1 %rc, i64 %rs1, i64 %rs22327 ret i64 %sel2328}2329 2330define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) {2331; RV32I-LABEL: seteq_constant:2332; RV32I: # %bb.0:2333; RV32I-NEXT: xori a0, a0, 1232334; RV32I-NEXT: or a1, a0, a12335; RV32I-NEXT: mv a0, a22336; RV32I-NEXT: beqz a1, .LBB35_22337; RV32I-NEXT: # %bb.1:2338; RV32I-NEXT: mv a0, a42339; RV32I-NEXT: mv a3, a52340; RV32I-NEXT: .LBB35_2:2341; RV32I-NEXT: mv a1, a32342; RV32I-NEXT: ret2343;2344; RV64I-LABEL: seteq_constant:2345; RV64I: # %bb.0:2346; RV64I-NEXT: li a3, 1232347; RV64I-NEXT: beq a0, a3, .LBB35_22348; RV64I-NEXT: # %bb.1:2349; RV64I-NEXT: mv a1, a22350; RV64I-NEXT: .LBB35_2:2351; RV64I-NEXT: mv a0, a12352; RV64I-NEXT: ret2353;2354; RV32XVENTANACONDOPS-LABEL: seteq_constant:2355; RV32XVENTANACONDOPS: # %bb.0:2356; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 1232357; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12358; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a02359; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a02360; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a02361; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a02362; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12363; RV32XVENTANACONDOPS-NEXT: or a1, a3, a42364; RV32XVENTANACONDOPS-NEXT: ret2365;2366; RV64XVENTANACONDOPS-LABEL: seteq_constant:2367; RV64XVENTANACONDOPS: # %bb.0:2368; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -1232369; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a02370; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a02371; RV64XVENTANACONDOPS-NEXT: or a0, a0, a22372; RV64XVENTANACONDOPS-NEXT: ret2373;2374; RV64XTHEADCONDMOV-LABEL: seteq_constant:2375; RV64XTHEADCONDMOV: # %bb.0:2376; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -1232377; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a02378; RV64XTHEADCONDMOV-NEXT: mv a0, a12379; RV64XTHEADCONDMOV-NEXT: ret2380;2381; RV32ZICOND-LABEL: seteq_constant:2382; RV32ZICOND: # %bb.0:2383; RV32ZICOND-NEXT: xori a0, a0, 1232384; RV32ZICOND-NEXT: or a0, a0, a12385; RV32ZICOND-NEXT: czero.eqz a1, a4, a02386; RV32ZICOND-NEXT: czero.nez a2, a2, a02387; RV32ZICOND-NEXT: czero.eqz a4, a5, a02388; RV32ZICOND-NEXT: czero.nez a3, a3, a02389; RV32ZICOND-NEXT: or a0, a2, a12390; RV32ZICOND-NEXT: or a1, a3, a42391; RV32ZICOND-NEXT: ret2392;2393; RV64ZICOND-LABEL: seteq_constant:2394; RV64ZICOND: # %bb.0:2395; RV64ZICOND-NEXT: addi a0, a0, -1232396; RV64ZICOND-NEXT: czero.eqz a2, a2, a02397; RV64ZICOND-NEXT: czero.nez a0, a1, a02398; RV64ZICOND-NEXT: or a0, a0, a22399; RV64ZICOND-NEXT: ret2400 %rc = icmp eq i64 %a, 1232401 %sel = select i1 %rc, i64 %rs1, i64 %rs22402 ret i64 %sel2403}2404 2405define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) {2406; RV32I-LABEL: setne_constant:2407; RV32I: # %bb.0:2408; RV32I-NEXT: xori a0, a0, 4562409; RV32I-NEXT: or a1, a0, a12410; RV32I-NEXT: mv a0, a22411; RV32I-NEXT: bnez a1, .LBB36_22412; RV32I-NEXT: # %bb.1:2413; RV32I-NEXT: mv a0, a42414; RV32I-NEXT: mv a3, a52415; RV32I-NEXT: .LBB36_2:2416; RV32I-NEXT: mv a1, a32417; RV32I-NEXT: ret2418;2419; RV64I-LABEL: setne_constant:2420; RV64I: # %bb.0:2421; RV64I-NEXT: li a3, 4562422; RV64I-NEXT: bne a0, a3, .LBB36_22423; RV64I-NEXT: # %bb.1:2424; RV64I-NEXT: mv a1, a22425; RV64I-NEXT: .LBB36_2:2426; RV64I-NEXT: mv a0, a12427; RV64I-NEXT: ret2428;2429; RV32XVENTANACONDOPS-LABEL: setne_constant:2430; RV32XVENTANACONDOPS: # %bb.0:2431; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 4562432; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12433; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a02434; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a02435; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a02436; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a02437; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12438; RV32XVENTANACONDOPS-NEXT: or a1, a3, a42439; RV32XVENTANACONDOPS-NEXT: ret2440;2441; RV64XVENTANACONDOPS-LABEL: setne_constant:2442; RV64XVENTANACONDOPS: # %bb.0:2443; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -4562444; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a02445; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a02446; RV64XVENTANACONDOPS-NEXT: or a0, a0, a22447; RV64XVENTANACONDOPS-NEXT: ret2448;2449; RV64XTHEADCONDMOV-LABEL: setne_constant:2450; RV64XTHEADCONDMOV: # %bb.0:2451; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -4562452; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a02453; RV64XTHEADCONDMOV-NEXT: mv a0, a12454; RV64XTHEADCONDMOV-NEXT: ret2455;2456; RV32ZICOND-LABEL: setne_constant:2457; RV32ZICOND: # %bb.0:2458; RV32ZICOND-NEXT: xori a0, a0, 4562459; RV32ZICOND-NEXT: or a0, a0, a12460; RV32ZICOND-NEXT: czero.nez a1, a4, a02461; RV32ZICOND-NEXT: czero.eqz a2, a2, a02462; RV32ZICOND-NEXT: czero.nez a4, a5, a02463; RV32ZICOND-NEXT: czero.eqz a3, a3, a02464; RV32ZICOND-NEXT: or a0, a2, a12465; RV32ZICOND-NEXT: or a1, a3, a42466; RV32ZICOND-NEXT: ret2467;2468; RV64ZICOND-LABEL: setne_constant:2469; RV64ZICOND: # %bb.0:2470; RV64ZICOND-NEXT: addi a0, a0, -4562471; RV64ZICOND-NEXT: czero.nez a2, a2, a02472; RV64ZICOND-NEXT: czero.eqz a0, a1, a02473; RV64ZICOND-NEXT: or a0, a0, a22474; RV64ZICOND-NEXT: ret2475 %rc = icmp ne i64 %a, 4562476 %sel = select i1 %rc, i64 %rs1, i64 %rs22477 ret i64 %sel2478}2479 2480define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) {2481; RV32I-LABEL: seteq_2048:2482; RV32I: # %bb.0:2483; RV32I-NEXT: binvi a0, a0, 112484; RV32I-NEXT: or a1, a0, a12485; RV32I-NEXT: mv a0, a22486; RV32I-NEXT: beqz a1, .LBB37_22487; RV32I-NEXT: # %bb.1:2488; RV32I-NEXT: mv a0, a42489; RV32I-NEXT: mv a3, a52490; RV32I-NEXT: .LBB37_2:2491; RV32I-NEXT: mv a1, a32492; RV32I-NEXT: ret2493;2494; RV64I-LABEL: seteq_2048:2495; RV64I: # %bb.0:2496; RV64I-NEXT: bseti a3, zero, 112497; RV64I-NEXT: beq a0, a3, .LBB37_22498; RV64I-NEXT: # %bb.1:2499; RV64I-NEXT: mv a1, a22500; RV64I-NEXT: .LBB37_2:2501; RV64I-NEXT: mv a0, a12502; RV64I-NEXT: ret2503;2504; RV32XVENTANACONDOPS-LABEL: seteq_2048:2505; RV32XVENTANACONDOPS: # %bb.0:2506; RV32XVENTANACONDOPS-NEXT: binvi a0, a0, 112507; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12508; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a02509; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a02510; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a02511; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a02512; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12513; RV32XVENTANACONDOPS-NEXT: or a1, a3, a42514; RV32XVENTANACONDOPS-NEXT: ret2515;2516; RV64XVENTANACONDOPS-LABEL: seteq_2048:2517; RV64XVENTANACONDOPS: # %bb.0:2518; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -20482519; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a02520; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a02521; RV64XVENTANACONDOPS-NEXT: or a0, a0, a22522; RV64XVENTANACONDOPS-NEXT: ret2523;2524; RV64XTHEADCONDMOV-LABEL: seteq_2048:2525; RV64XTHEADCONDMOV: # %bb.0:2526; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -20482527; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a02528; RV64XTHEADCONDMOV-NEXT: mv a0, a12529; RV64XTHEADCONDMOV-NEXT: ret2530;2531; RV32ZICOND-LABEL: seteq_2048:2532; RV32ZICOND: # %bb.0:2533; RV32ZICOND-NEXT: binvi a0, a0, 112534; RV32ZICOND-NEXT: or a0, a0, a12535; RV32ZICOND-NEXT: czero.eqz a1, a4, a02536; RV32ZICOND-NEXT: czero.nez a2, a2, a02537; RV32ZICOND-NEXT: czero.eqz a4, a5, a02538; RV32ZICOND-NEXT: czero.nez a3, a3, a02539; RV32ZICOND-NEXT: or a0, a2, a12540; RV32ZICOND-NEXT: or a1, a3, a42541; RV32ZICOND-NEXT: ret2542;2543; RV64ZICOND-LABEL: seteq_2048:2544; RV64ZICOND: # %bb.0:2545; RV64ZICOND-NEXT: addi a0, a0, -20482546; RV64ZICOND-NEXT: czero.eqz a2, a2, a02547; RV64ZICOND-NEXT: czero.nez a0, a1, a02548; RV64ZICOND-NEXT: or a0, a0, a22549; RV64ZICOND-NEXT: ret2550 %rc = icmp eq i64 %a, 20482551 %sel = select i1 %rc, i64 %rs1, i64 %rs22552 ret i64 %sel2553}2554 2555define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) {2556; RV32I-LABEL: seteq_neg2048:2557; RV32I: # %bb.0:2558; RV32I-NEXT: not a1, a12559; RV32I-NEXT: xori a0, a0, -20482560; RV32I-NEXT: or a1, a0, a12561; RV32I-NEXT: mv a0, a22562; RV32I-NEXT: beqz a1, .LBB38_22563; RV32I-NEXT: # %bb.1:2564; RV32I-NEXT: mv a0, a42565; RV32I-NEXT: mv a3, a52566; RV32I-NEXT: .LBB38_2:2567; RV32I-NEXT: mv a1, a32568; RV32I-NEXT: ret2569;2570; RV64I-LABEL: seteq_neg2048:2571; RV64I: # %bb.0:2572; RV64I-NEXT: li a3, -20482573; RV64I-NEXT: beq a0, a3, .LBB38_22574; RV64I-NEXT: # %bb.1:2575; RV64I-NEXT: mv a1, a22576; RV64I-NEXT: .LBB38_2:2577; RV64I-NEXT: mv a0, a12578; RV64I-NEXT: ret2579;2580; RV32XVENTANACONDOPS-LABEL: seteq_neg2048:2581; RV32XVENTANACONDOPS: # %bb.0:2582; RV32XVENTANACONDOPS-NEXT: not a1, a12583; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -20482584; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12585; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a02586; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a02587; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a02588; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a02589; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12590; RV32XVENTANACONDOPS-NEXT: or a1, a3, a42591; RV32XVENTANACONDOPS-NEXT: ret2592;2593; RV64XVENTANACONDOPS-LABEL: seteq_neg2048:2594; RV64XVENTANACONDOPS: # %bb.0:2595; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -20482596; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a02597; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a02598; RV64XVENTANACONDOPS-NEXT: or a0, a0, a22599; RV64XVENTANACONDOPS-NEXT: ret2600;2601; RV64XTHEADCONDMOV-LABEL: seteq_neg2048:2602; RV64XTHEADCONDMOV: # %bb.0:2603; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -20482604; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, a2, a02605; RV64XTHEADCONDMOV-NEXT: mv a0, a12606; RV64XTHEADCONDMOV-NEXT: ret2607;2608; RV32ZICOND-LABEL: seteq_neg2048:2609; RV32ZICOND: # %bb.0:2610; RV32ZICOND-NEXT: not a1, a12611; RV32ZICOND-NEXT: xori a0, a0, -20482612; RV32ZICOND-NEXT: or a0, a0, a12613; RV32ZICOND-NEXT: czero.eqz a1, a4, a02614; RV32ZICOND-NEXT: czero.nez a2, a2, a02615; RV32ZICOND-NEXT: czero.eqz a4, a5, a02616; RV32ZICOND-NEXT: czero.nez a3, a3, a02617; RV32ZICOND-NEXT: or a0, a2, a12618; RV32ZICOND-NEXT: or a1, a3, a42619; RV32ZICOND-NEXT: ret2620;2621; RV64ZICOND-LABEL: seteq_neg2048:2622; RV64ZICOND: # %bb.0:2623; RV64ZICOND-NEXT: xori a0, a0, -20482624; RV64ZICOND-NEXT: czero.eqz a2, a2, a02625; RV64ZICOND-NEXT: czero.nez a0, a1, a02626; RV64ZICOND-NEXT: or a0, a0, a22627; RV64ZICOND-NEXT: ret2628 %rc = icmp eq i64 %a, -20482629 %sel = select i1 %rc, i64 %rs1, i64 %rs22630 ret i64 %sel2631}2632 2633define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) {2634; RV32I-LABEL: setne_neg2048:2635; RV32I: # %bb.0:2636; RV32I-NEXT: not a1, a12637; RV32I-NEXT: xori a0, a0, -20482638; RV32I-NEXT: or a1, a0, a12639; RV32I-NEXT: mv a0, a22640; RV32I-NEXT: bnez a1, .LBB39_22641; RV32I-NEXT: # %bb.1:2642; RV32I-NEXT: mv a0, a42643; RV32I-NEXT: mv a3, a52644; RV32I-NEXT: .LBB39_2:2645; RV32I-NEXT: mv a1, a32646; RV32I-NEXT: ret2647;2648; RV64I-LABEL: setne_neg2048:2649; RV64I: # %bb.0:2650; RV64I-NEXT: li a3, -20482651; RV64I-NEXT: bne a0, a3, .LBB39_22652; RV64I-NEXT: # %bb.1:2653; RV64I-NEXT: mv a1, a22654; RV64I-NEXT: .LBB39_2:2655; RV64I-NEXT: mv a0, a12656; RV64I-NEXT: ret2657;2658; RV32XVENTANACONDOPS-LABEL: setne_neg2048:2659; RV32XVENTANACONDOPS: # %bb.0:2660; RV32XVENTANACONDOPS-NEXT: not a1, a12661; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -20482662; RV32XVENTANACONDOPS-NEXT: or a0, a0, a12663; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a02664; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a02665; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a02666; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a02667; RV32XVENTANACONDOPS-NEXT: or a0, a2, a12668; RV32XVENTANACONDOPS-NEXT: or a1, a3, a42669; RV32XVENTANACONDOPS-NEXT: ret2670;2671; RV64XVENTANACONDOPS-LABEL: setne_neg2048:2672; RV64XVENTANACONDOPS: # %bb.0:2673; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -20482674; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a02675; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a02676; RV64XVENTANACONDOPS-NEXT: or a0, a0, a22677; RV64XVENTANACONDOPS-NEXT: ret2678;2679; RV64XTHEADCONDMOV-LABEL: setne_neg2048:2680; RV64XTHEADCONDMOV: # %bb.0:2681; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -20482682; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, a2, a02683; RV64XTHEADCONDMOV-NEXT: mv a0, a12684; RV64XTHEADCONDMOV-NEXT: ret2685;2686; RV32ZICOND-LABEL: setne_neg2048:2687; RV32ZICOND: # %bb.0:2688; RV32ZICOND-NEXT: not a1, a12689; RV32ZICOND-NEXT: xori a0, a0, -20482690; RV32ZICOND-NEXT: or a0, a0, a12691; RV32ZICOND-NEXT: czero.nez a1, a4, a02692; RV32ZICOND-NEXT: czero.eqz a2, a2, a02693; RV32ZICOND-NEXT: czero.nez a4, a5, a02694; RV32ZICOND-NEXT: czero.eqz a3, a3, a02695; RV32ZICOND-NEXT: or a0, a2, a12696; RV32ZICOND-NEXT: or a1, a3, a42697; RV32ZICOND-NEXT: ret2698;2699; RV64ZICOND-LABEL: setne_neg2048:2700; RV64ZICOND: # %bb.0:2701; RV64ZICOND-NEXT: xori a0, a0, -20482702; RV64ZICOND-NEXT: czero.nez a2, a2, a02703; RV64ZICOND-NEXT: czero.eqz a0, a1, a02704; RV64ZICOND-NEXT: or a0, a0, a22705; RV64ZICOND-NEXT: ret2706 %rc = icmp ne i64 %a, -20482707 %sel = select i1 %rc, i64 %rs1, i64 %rs22708 ret i64 %sel2709}2710 2711define i64 @zero1_seteq(i64 %a, i64 %b, i64 %rs1) {2712; RV32I-LABEL: zero1_seteq:2713; RV32I: # %bb.0:2714; RV32I-NEXT: xor a1, a1, a32715; RV32I-NEXT: xor a0, a0, a22716; RV32I-NEXT: or a0, a0, a12717; RV32I-NEXT: snez a0, a02718; RV32I-NEXT: addi a1, a0, -12719; RV32I-NEXT: and a0, a1, a42720; RV32I-NEXT: and a1, a1, a52721; RV32I-NEXT: ret2722;2723; RV64I-LABEL: zero1_seteq:2724; RV64I: # %bb.0:2725; RV64I-NEXT: xor a0, a0, a12726; RV64I-NEXT: snez a0, a02727; RV64I-NEXT: addi a0, a0, -12728; RV64I-NEXT: and a0, a0, a22729; RV64I-NEXT: ret2730;2731; RV32XVENTANACONDOPS-LABEL: zero1_seteq:2732; RV32XVENTANACONDOPS: # %bb.0:2733; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a32734; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a22735; RV32XVENTANACONDOPS-NEXT: or a1, a0, a12736; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a12737; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a12738; RV32XVENTANACONDOPS-NEXT: ret2739;2740; RV64XVENTANACONDOPS-LABEL: zero1_seteq:2741; RV64XVENTANACONDOPS: # %bb.0:2742; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a12743; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a02744; RV64XVENTANACONDOPS-NEXT: ret2745;2746; RV64XTHEADCONDMOV-LABEL: zero1_seteq:2747; RV64XTHEADCONDMOV: # %bb.0:2748; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a12749; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a02750; RV64XTHEADCONDMOV-NEXT: mv a0, a22751; RV64XTHEADCONDMOV-NEXT: ret2752;2753; RV32ZICOND-LABEL: zero1_seteq:2754; RV32ZICOND: # %bb.0:2755; RV32ZICOND-NEXT: xor a1, a1, a32756; RV32ZICOND-NEXT: xor a0, a0, a22757; RV32ZICOND-NEXT: or a1, a0, a12758; RV32ZICOND-NEXT: czero.nez a0, a4, a12759; RV32ZICOND-NEXT: czero.nez a1, a5, a12760; RV32ZICOND-NEXT: ret2761;2762; RV64ZICOND-LABEL: zero1_seteq:2763; RV64ZICOND: # %bb.0:2764; RV64ZICOND-NEXT: xor a0, a0, a12765; RV64ZICOND-NEXT: czero.nez a0, a2, a02766; RV64ZICOND-NEXT: ret2767 %rc = icmp eq i64 %a, %b2768 %sel = select i1 %rc, i64 %rs1, i64 02769 ret i64 %sel2770}2771 2772define i64 @zero2_seteq(i64 %a, i64 %b, i64 %rs1) {2773; RV32I-LABEL: zero2_seteq:2774; RV32I: # %bb.0:2775; RV32I-NEXT: xor a1, a1, a32776; RV32I-NEXT: xor a0, a0, a22777; RV32I-NEXT: or a0, a0, a12778; RV32I-NEXT: seqz a0, a02779; RV32I-NEXT: addi a1, a0, -12780; RV32I-NEXT: and a0, a1, a42781; RV32I-NEXT: and a1, a1, a52782; RV32I-NEXT: ret2783;2784; RV64I-LABEL: zero2_seteq:2785; RV64I: # %bb.0:2786; RV64I-NEXT: xor a0, a0, a12787; RV64I-NEXT: seqz a0, a02788; RV64I-NEXT: addi a0, a0, -12789; RV64I-NEXT: and a0, a0, a22790; RV64I-NEXT: ret2791;2792; RV32XVENTANACONDOPS-LABEL: zero2_seteq:2793; RV32XVENTANACONDOPS: # %bb.0:2794; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a32795; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a22796; RV32XVENTANACONDOPS-NEXT: or a1, a0, a12797; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a12798; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a12799; RV32XVENTANACONDOPS-NEXT: ret2800;2801; RV64XVENTANACONDOPS-LABEL: zero2_seteq:2802; RV64XVENTANACONDOPS: # %bb.0:2803; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a12804; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a02805; RV64XVENTANACONDOPS-NEXT: ret2806;2807; RV64XTHEADCONDMOV-LABEL: zero2_seteq:2808; RV64XTHEADCONDMOV: # %bb.0:2809; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a12810; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a02811; RV64XTHEADCONDMOV-NEXT: mv a0, a22812; RV64XTHEADCONDMOV-NEXT: ret2813;2814; RV32ZICOND-LABEL: zero2_seteq:2815; RV32ZICOND: # %bb.0:2816; RV32ZICOND-NEXT: xor a1, a1, a32817; RV32ZICOND-NEXT: xor a0, a0, a22818; RV32ZICOND-NEXT: or a1, a0, a12819; RV32ZICOND-NEXT: czero.eqz a0, a4, a12820; RV32ZICOND-NEXT: czero.eqz a1, a5, a12821; RV32ZICOND-NEXT: ret2822;2823; RV64ZICOND-LABEL: zero2_seteq:2824; RV64ZICOND: # %bb.0:2825; RV64ZICOND-NEXT: xor a0, a0, a12826; RV64ZICOND-NEXT: czero.eqz a0, a2, a02827; RV64ZICOND-NEXT: ret2828 %rc = icmp eq i64 %a, %b2829 %sel = select i1 %rc, i64 0, i64 %rs12830 ret i64 %sel2831}2832 2833define i64 @zero1_setne(i64 %a, i64 %b, i64 %rs1) {2834; RV32I-LABEL: zero1_setne:2835; RV32I: # %bb.0:2836; RV32I-NEXT: xor a1, a1, a32837; RV32I-NEXT: xor a0, a0, a22838; RV32I-NEXT: or a0, a0, a12839; RV32I-NEXT: seqz a0, a02840; RV32I-NEXT: addi a1, a0, -12841; RV32I-NEXT: and a0, a1, a42842; RV32I-NEXT: and a1, a1, a52843; RV32I-NEXT: ret2844;2845; RV64I-LABEL: zero1_setne:2846; RV64I: # %bb.0:2847; RV64I-NEXT: xor a0, a0, a12848; RV64I-NEXT: seqz a0, a02849; RV64I-NEXT: addi a0, a0, -12850; RV64I-NEXT: and a0, a0, a22851; RV64I-NEXT: ret2852;2853; RV32XVENTANACONDOPS-LABEL: zero1_setne:2854; RV32XVENTANACONDOPS: # %bb.0:2855; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a32856; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a22857; RV32XVENTANACONDOPS-NEXT: or a1, a0, a12858; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a12859; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a12860; RV32XVENTANACONDOPS-NEXT: ret2861;2862; RV64XVENTANACONDOPS-LABEL: zero1_setne:2863; RV64XVENTANACONDOPS: # %bb.0:2864; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a12865; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a02866; RV64XVENTANACONDOPS-NEXT: ret2867;2868; RV64XTHEADCONDMOV-LABEL: zero1_setne:2869; RV64XTHEADCONDMOV: # %bb.0:2870; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a12871; RV64XTHEADCONDMOV-NEXT: th.mveqz a2, zero, a02872; RV64XTHEADCONDMOV-NEXT: mv a0, a22873; RV64XTHEADCONDMOV-NEXT: ret2874;2875; RV32ZICOND-LABEL: zero1_setne:2876; RV32ZICOND: # %bb.0:2877; RV32ZICOND-NEXT: xor a1, a1, a32878; RV32ZICOND-NEXT: xor a0, a0, a22879; RV32ZICOND-NEXT: or a1, a0, a12880; RV32ZICOND-NEXT: czero.eqz a0, a4, a12881; RV32ZICOND-NEXT: czero.eqz a1, a5, a12882; RV32ZICOND-NEXT: ret2883;2884; RV64ZICOND-LABEL: zero1_setne:2885; RV64ZICOND: # %bb.0:2886; RV64ZICOND-NEXT: xor a0, a0, a12887; RV64ZICOND-NEXT: czero.eqz a0, a2, a02888; RV64ZICOND-NEXT: ret2889 %rc = icmp ne i64 %a, %b2890 %sel = select i1 %rc, i64 %rs1, i64 02891 ret i64 %sel2892}2893 2894define i64 @zero2_setne(i64 %a, i64 %b, i64 %rs1) {2895; RV32I-LABEL: zero2_setne:2896; RV32I: # %bb.0:2897; RV32I-NEXT: xor a1, a1, a32898; RV32I-NEXT: xor a0, a0, a22899; RV32I-NEXT: or a0, a0, a12900; RV32I-NEXT: snez a0, a02901; RV32I-NEXT: addi a1, a0, -12902; RV32I-NEXT: and a0, a1, a42903; RV32I-NEXT: and a1, a1, a52904; RV32I-NEXT: ret2905;2906; RV64I-LABEL: zero2_setne:2907; RV64I: # %bb.0:2908; RV64I-NEXT: xor a0, a0, a12909; RV64I-NEXT: snez a0, a02910; RV64I-NEXT: addi a0, a0, -12911; RV64I-NEXT: and a0, a0, a22912; RV64I-NEXT: ret2913;2914; RV32XVENTANACONDOPS-LABEL: zero2_setne:2915; RV32XVENTANACONDOPS: # %bb.0:2916; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a32917; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a22918; RV32XVENTANACONDOPS-NEXT: or a1, a0, a12919; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a12920; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a12921; RV32XVENTANACONDOPS-NEXT: ret2922;2923; RV64XVENTANACONDOPS-LABEL: zero2_setne:2924; RV64XVENTANACONDOPS: # %bb.0:2925; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a12926; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a02927; RV64XVENTANACONDOPS-NEXT: ret2928;2929; RV64XTHEADCONDMOV-LABEL: zero2_setne:2930; RV64XTHEADCONDMOV: # %bb.0:2931; RV64XTHEADCONDMOV-NEXT: xor a0, a0, a12932; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, zero, a02933; RV64XTHEADCONDMOV-NEXT: mv a0, a22934; RV64XTHEADCONDMOV-NEXT: ret2935;2936; RV32ZICOND-LABEL: zero2_setne:2937; RV32ZICOND: # %bb.0:2938; RV32ZICOND-NEXT: xor a1, a1, a32939; RV32ZICOND-NEXT: xor a0, a0, a22940; RV32ZICOND-NEXT: or a1, a0, a12941; RV32ZICOND-NEXT: czero.nez a0, a4, a12942; RV32ZICOND-NEXT: czero.nez a1, a5, a12943; RV32ZICOND-NEXT: ret2944;2945; RV64ZICOND-LABEL: zero2_setne:2946; RV64ZICOND: # %bb.0:2947; RV64ZICOND-NEXT: xor a0, a0, a12948; RV64ZICOND-NEXT: czero.nez a0, a2, a02949; RV64ZICOND-NEXT: ret2950 %rc = icmp ne i64 %a, %b2951 %sel = select i1 %rc, i64 0, i64 %rs12952 ret i64 %sel2953}2954 2955define i64 @zero1_seteq_zero(i64 %a, i64 %rs1) {2956; RV32I-LABEL: zero1_seteq_zero:2957; RV32I: # %bb.0:2958; RV32I-NEXT: or a0, a0, a12959; RV32I-NEXT: snez a0, a02960; RV32I-NEXT: addi a1, a0, -12961; RV32I-NEXT: and a0, a1, a22962; RV32I-NEXT: and a1, a1, a32963; RV32I-NEXT: ret2964;2965; RV64I-LABEL: zero1_seteq_zero:2966; RV64I: # %bb.0:2967; RV64I-NEXT: snez a0, a02968; RV64I-NEXT: addi a0, a0, -12969; RV64I-NEXT: and a0, a0, a12970; RV64I-NEXT: ret2971;2972; RV32XVENTANACONDOPS-LABEL: zero1_seteq_zero:2973; RV32XVENTANACONDOPS: # %bb.0:2974; RV32XVENTANACONDOPS-NEXT: or a1, a0, a12975; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a12976; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a12977; RV32XVENTANACONDOPS-NEXT: ret2978;2979; RV64XVENTANACONDOPS-LABEL: zero1_seteq_zero:2980; RV64XVENTANACONDOPS: # %bb.0:2981; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a02982; RV64XVENTANACONDOPS-NEXT: ret2983;2984; RV64XTHEADCONDMOV-LABEL: zero1_seteq_zero:2985; RV64XTHEADCONDMOV: # %bb.0:2986; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a02987; RV64XTHEADCONDMOV-NEXT: mv a0, a12988; RV64XTHEADCONDMOV-NEXT: ret2989;2990; RV32ZICOND-LABEL: zero1_seteq_zero:2991; RV32ZICOND: # %bb.0:2992; RV32ZICOND-NEXT: or a1, a0, a12993; RV32ZICOND-NEXT: czero.nez a0, a2, a12994; RV32ZICOND-NEXT: czero.nez a1, a3, a12995; RV32ZICOND-NEXT: ret2996;2997; RV64ZICOND-LABEL: zero1_seteq_zero:2998; RV64ZICOND: # %bb.0:2999; RV64ZICOND-NEXT: czero.nez a0, a1, a03000; RV64ZICOND-NEXT: ret3001 %rc = icmp eq i64 %a, 03002 %sel = select i1 %rc, i64 %rs1, i64 03003 ret i64 %sel3004}3005 3006define i64 @zero2_seteq_zero(i64 %a, i64 %rs1) {3007; RV32I-LABEL: zero2_seteq_zero:3008; RV32I: # %bb.0:3009; RV32I-NEXT: or a0, a0, a13010; RV32I-NEXT: seqz a0, a03011; RV32I-NEXT: addi a1, a0, -13012; RV32I-NEXT: and a0, a1, a23013; RV32I-NEXT: and a1, a1, a33014; RV32I-NEXT: ret3015;3016; RV64I-LABEL: zero2_seteq_zero:3017; RV64I: # %bb.0:3018; RV64I-NEXT: seqz a0, a03019; RV64I-NEXT: addi a0, a0, -13020; RV64I-NEXT: and a0, a0, a13021; RV64I-NEXT: ret3022;3023; RV32XVENTANACONDOPS-LABEL: zero2_seteq_zero:3024; RV32XVENTANACONDOPS: # %bb.0:3025; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13026; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a13027; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a13028; RV32XVENTANACONDOPS-NEXT: ret3029;3030; RV64XVENTANACONDOPS-LABEL: zero2_seteq_zero:3031; RV64XVENTANACONDOPS: # %bb.0:3032; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a03033; RV64XVENTANACONDOPS-NEXT: ret3034;3035; RV64XTHEADCONDMOV-LABEL: zero2_seteq_zero:3036; RV64XTHEADCONDMOV: # %bb.0:3037; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a03038; RV64XTHEADCONDMOV-NEXT: mv a0, a13039; RV64XTHEADCONDMOV-NEXT: ret3040;3041; RV32ZICOND-LABEL: zero2_seteq_zero:3042; RV32ZICOND: # %bb.0:3043; RV32ZICOND-NEXT: or a1, a0, a13044; RV32ZICOND-NEXT: czero.eqz a0, a2, a13045; RV32ZICOND-NEXT: czero.eqz a1, a3, a13046; RV32ZICOND-NEXT: ret3047;3048; RV64ZICOND-LABEL: zero2_seteq_zero:3049; RV64ZICOND: # %bb.0:3050; RV64ZICOND-NEXT: czero.eqz a0, a1, a03051; RV64ZICOND-NEXT: ret3052 %rc = icmp eq i64 %a, 03053 %sel = select i1 %rc, i64 0, i64 %rs13054 ret i64 %sel3055}3056 3057define i64 @zero1_setne_zero(i64 %a, i64 %rs1) {3058; RV32I-LABEL: zero1_setne_zero:3059; RV32I: # %bb.0:3060; RV32I-NEXT: or a0, a0, a13061; RV32I-NEXT: seqz a0, a03062; RV32I-NEXT: addi a1, a0, -13063; RV32I-NEXT: and a0, a1, a23064; RV32I-NEXT: and a1, a1, a33065; RV32I-NEXT: ret3066;3067; RV64I-LABEL: zero1_setne_zero:3068; RV64I: # %bb.0:3069; RV64I-NEXT: seqz a0, a03070; RV64I-NEXT: addi a0, a0, -13071; RV64I-NEXT: and a0, a0, a13072; RV64I-NEXT: ret3073;3074; RV32XVENTANACONDOPS-LABEL: zero1_setne_zero:3075; RV32XVENTANACONDOPS: # %bb.0:3076; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13077; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a13078; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a13079; RV32XVENTANACONDOPS-NEXT: ret3080;3081; RV64XVENTANACONDOPS-LABEL: zero1_setne_zero:3082; RV64XVENTANACONDOPS: # %bb.0:3083; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a03084; RV64XVENTANACONDOPS-NEXT: ret3085;3086; RV64XTHEADCONDMOV-LABEL: zero1_setne_zero:3087; RV64XTHEADCONDMOV: # %bb.0:3088; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a03089; RV64XTHEADCONDMOV-NEXT: mv a0, a13090; RV64XTHEADCONDMOV-NEXT: ret3091;3092; RV32ZICOND-LABEL: zero1_setne_zero:3093; RV32ZICOND: # %bb.0:3094; RV32ZICOND-NEXT: or a1, a0, a13095; RV32ZICOND-NEXT: czero.eqz a0, a2, a13096; RV32ZICOND-NEXT: czero.eqz a1, a3, a13097; RV32ZICOND-NEXT: ret3098;3099; RV64ZICOND-LABEL: zero1_setne_zero:3100; RV64ZICOND: # %bb.0:3101; RV64ZICOND-NEXT: czero.eqz a0, a1, a03102; RV64ZICOND-NEXT: ret3103 %rc = icmp ne i64 %a, 03104 %sel = select i1 %rc, i64 %rs1, i64 03105 ret i64 %sel3106}3107 3108define i64 @zero2_setne_zero(i64 %a, i64 %rs1) {3109; RV32I-LABEL: zero2_setne_zero:3110; RV32I: # %bb.0:3111; RV32I-NEXT: or a0, a0, a13112; RV32I-NEXT: snez a0, a03113; RV32I-NEXT: addi a1, a0, -13114; RV32I-NEXT: and a0, a1, a23115; RV32I-NEXT: and a1, a1, a33116; RV32I-NEXT: ret3117;3118; RV64I-LABEL: zero2_setne_zero:3119; RV64I: # %bb.0:3120; RV64I-NEXT: snez a0, a03121; RV64I-NEXT: addi a0, a0, -13122; RV64I-NEXT: and a0, a0, a13123; RV64I-NEXT: ret3124;3125; RV32XVENTANACONDOPS-LABEL: zero2_setne_zero:3126; RV32XVENTANACONDOPS: # %bb.0:3127; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13128; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a13129; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a13130; RV32XVENTANACONDOPS-NEXT: ret3131;3132; RV64XVENTANACONDOPS-LABEL: zero2_setne_zero:3133; RV64XVENTANACONDOPS: # %bb.0:3134; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a03135; RV64XVENTANACONDOPS-NEXT: ret3136;3137; RV64XTHEADCONDMOV-LABEL: zero2_setne_zero:3138; RV64XTHEADCONDMOV: # %bb.0:3139; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a03140; RV64XTHEADCONDMOV-NEXT: mv a0, a13141; RV64XTHEADCONDMOV-NEXT: ret3142;3143; RV32ZICOND-LABEL: zero2_setne_zero:3144; RV32ZICOND: # %bb.0:3145; RV32ZICOND-NEXT: or a1, a0, a13146; RV32ZICOND-NEXT: czero.nez a0, a2, a13147; RV32ZICOND-NEXT: czero.nez a1, a3, a13148; RV32ZICOND-NEXT: ret3149;3150; RV64ZICOND-LABEL: zero2_setne_zero:3151; RV64ZICOND: # %bb.0:3152; RV64ZICOND-NEXT: czero.nez a0, a1, a03153; RV64ZICOND-NEXT: ret3154 %rc = icmp ne i64 %a, 03155 %sel = select i1 %rc, i64 0, i64 %rs13156 ret i64 %sel3157}3158 3159define i64 @zero1_seteq_constant(i64 %a, i64 %rs1) {3160; RV32I-LABEL: zero1_seteq_constant:3161; RV32I: # %bb.0:3162; RV32I-NEXT: not a1, a13163; RV32I-NEXT: xori a0, a0, -2313164; RV32I-NEXT: or a0, a0, a13165; RV32I-NEXT: snez a0, a03166; RV32I-NEXT: addi a1, a0, -13167; RV32I-NEXT: and a0, a1, a23168; RV32I-NEXT: and a1, a1, a33169; RV32I-NEXT: ret3170;3171; RV64I-LABEL: zero1_seteq_constant:3172; RV64I: # %bb.0:3173; RV64I-NEXT: addi a0, a0, 2313174; RV64I-NEXT: snez a0, a03175; RV64I-NEXT: addi a0, a0, -13176; RV64I-NEXT: and a0, a0, a13177; RV64I-NEXT: ret3178;3179; RV32XVENTANACONDOPS-LABEL: zero1_seteq_constant:3180; RV32XVENTANACONDOPS: # %bb.0:3181; RV32XVENTANACONDOPS-NEXT: not a1, a13182; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2313183; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13184; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a13185; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a13186; RV32XVENTANACONDOPS-NEXT: ret3187;3188; RV64XVENTANACONDOPS-LABEL: zero1_seteq_constant:3189; RV64XVENTANACONDOPS: # %bb.0:3190; RV64XVENTANACONDOPS-NEXT: addi a0, a0, 2313191; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a03192; RV64XVENTANACONDOPS-NEXT: ret3193;3194; RV64XTHEADCONDMOV-LABEL: zero1_seteq_constant:3195; RV64XTHEADCONDMOV: # %bb.0:3196; RV64XTHEADCONDMOV-NEXT: addi a0, a0, 2313197; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a03198; RV64XTHEADCONDMOV-NEXT: mv a0, a13199; RV64XTHEADCONDMOV-NEXT: ret3200;3201; RV32ZICOND-LABEL: zero1_seteq_constant:3202; RV32ZICOND: # %bb.0:3203; RV32ZICOND-NEXT: not a1, a13204; RV32ZICOND-NEXT: xori a0, a0, -2313205; RV32ZICOND-NEXT: or a1, a0, a13206; RV32ZICOND-NEXT: czero.nez a0, a2, a13207; RV32ZICOND-NEXT: czero.nez a1, a3, a13208; RV32ZICOND-NEXT: ret3209;3210; RV64ZICOND-LABEL: zero1_seteq_constant:3211; RV64ZICOND: # %bb.0:3212; RV64ZICOND-NEXT: addi a0, a0, 2313213; RV64ZICOND-NEXT: czero.nez a0, a1, a03214; RV64ZICOND-NEXT: ret3215 %rc = icmp eq i64 %a, -2313216 %sel = select i1 %rc, i64 %rs1, i64 03217 ret i64 %sel3218}3219 3220define i64 @zero2_seteq_constant(i64 %a, i64 %rs1) {3221; RV32I-LABEL: zero2_seteq_constant:3222; RV32I: # %bb.0:3223; RV32I-NEXT: xori a0, a0, 5463224; RV32I-NEXT: or a0, a0, a13225; RV32I-NEXT: seqz a0, a03226; RV32I-NEXT: addi a1, a0, -13227; RV32I-NEXT: and a0, a1, a23228; RV32I-NEXT: and a1, a1, a33229; RV32I-NEXT: ret3230;3231; RV64I-LABEL: zero2_seteq_constant:3232; RV64I: # %bb.0:3233; RV64I-NEXT: addi a0, a0, -5463234; RV64I-NEXT: seqz a0, a03235; RV64I-NEXT: addi a0, a0, -13236; RV64I-NEXT: and a0, a0, a13237; RV64I-NEXT: ret3238;3239; RV32XVENTANACONDOPS-LABEL: zero2_seteq_constant:3240; RV32XVENTANACONDOPS: # %bb.0:3241; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 5463242; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13243; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a13244; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a13245; RV32XVENTANACONDOPS-NEXT: ret3246;3247; RV64XVENTANACONDOPS-LABEL: zero2_seteq_constant:3248; RV64XVENTANACONDOPS: # %bb.0:3249; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -5463250; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a03251; RV64XVENTANACONDOPS-NEXT: ret3252;3253; RV64XTHEADCONDMOV-LABEL: zero2_seteq_constant:3254; RV64XTHEADCONDMOV: # %bb.0:3255; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -5463256; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a03257; RV64XTHEADCONDMOV-NEXT: mv a0, a13258; RV64XTHEADCONDMOV-NEXT: ret3259;3260; RV32ZICOND-LABEL: zero2_seteq_constant:3261; RV32ZICOND: # %bb.0:3262; RV32ZICOND-NEXT: xori a0, a0, 5463263; RV32ZICOND-NEXT: or a1, a0, a13264; RV32ZICOND-NEXT: czero.eqz a0, a2, a13265; RV32ZICOND-NEXT: czero.eqz a1, a3, a13266; RV32ZICOND-NEXT: ret3267;3268; RV64ZICOND-LABEL: zero2_seteq_constant:3269; RV64ZICOND: # %bb.0:3270; RV64ZICOND-NEXT: addi a0, a0, -5463271; RV64ZICOND-NEXT: czero.eqz a0, a1, a03272; RV64ZICOND-NEXT: ret3273 %rc = icmp eq i64 %a, 5463274 %sel = select i1 %rc, i64 0, i64 %rs13275 ret i64 %sel3276}3277 3278define i64 @zero1_setne_constant(i64 %a, i64 %rs1) {3279; RV32I-LABEL: zero1_setne_constant:3280; RV32I: # %bb.0:3281; RV32I-NEXT: xori a0, a0, 3213282; RV32I-NEXT: or a0, a0, a13283; RV32I-NEXT: seqz a0, a03284; RV32I-NEXT: addi a1, a0, -13285; RV32I-NEXT: and a0, a1, a23286; RV32I-NEXT: and a1, a1, a33287; RV32I-NEXT: ret3288;3289; RV64I-LABEL: zero1_setne_constant:3290; RV64I: # %bb.0:3291; RV64I-NEXT: addi a0, a0, -3213292; RV64I-NEXT: seqz a0, a03293; RV64I-NEXT: addi a0, a0, -13294; RV64I-NEXT: and a0, a0, a13295; RV64I-NEXT: ret3296;3297; RV32XVENTANACONDOPS-LABEL: zero1_setne_constant:3298; RV32XVENTANACONDOPS: # %bb.0:3299; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 3213300; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13301; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a13302; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a13303; RV32XVENTANACONDOPS-NEXT: ret3304;3305; RV64XVENTANACONDOPS-LABEL: zero1_setne_constant:3306; RV64XVENTANACONDOPS: # %bb.0:3307; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -3213308; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a03309; RV64XVENTANACONDOPS-NEXT: ret3310;3311; RV64XTHEADCONDMOV-LABEL: zero1_setne_constant:3312; RV64XTHEADCONDMOV: # %bb.0:3313; RV64XTHEADCONDMOV-NEXT: addi a0, a0, -3213314; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a03315; RV64XTHEADCONDMOV-NEXT: mv a0, a13316; RV64XTHEADCONDMOV-NEXT: ret3317;3318; RV32ZICOND-LABEL: zero1_setne_constant:3319; RV32ZICOND: # %bb.0:3320; RV32ZICOND-NEXT: xori a0, a0, 3213321; RV32ZICOND-NEXT: or a1, a0, a13322; RV32ZICOND-NEXT: czero.eqz a0, a2, a13323; RV32ZICOND-NEXT: czero.eqz a1, a3, a13324; RV32ZICOND-NEXT: ret3325;3326; RV64ZICOND-LABEL: zero1_setne_constant:3327; RV64ZICOND: # %bb.0:3328; RV64ZICOND-NEXT: addi a0, a0, -3213329; RV64ZICOND-NEXT: czero.eqz a0, a1, a03330; RV64ZICOND-NEXT: ret3331 %rc = icmp ne i64 %a, 3213332 %sel = select i1 %rc, i64 %rs1, i64 03333 ret i64 %sel3334}3335 3336define i64 @zero2_setne_constant(i64 %a, i64 %rs1) {3337; RV32I-LABEL: zero2_setne_constant:3338; RV32I: # %bb.0:3339; RV32I-NEXT: not a1, a13340; RV32I-NEXT: xori a0, a0, -6543341; RV32I-NEXT: or a0, a0, a13342; RV32I-NEXT: snez a0, a03343; RV32I-NEXT: addi a1, a0, -13344; RV32I-NEXT: and a0, a1, a23345; RV32I-NEXT: and a1, a1, a33346; RV32I-NEXT: ret3347;3348; RV64I-LABEL: zero2_setne_constant:3349; RV64I: # %bb.0:3350; RV64I-NEXT: addi a0, a0, 6543351; RV64I-NEXT: snez a0, a03352; RV64I-NEXT: addi a0, a0, -13353; RV64I-NEXT: and a0, a0, a13354; RV64I-NEXT: ret3355;3356; RV32XVENTANACONDOPS-LABEL: zero2_setne_constant:3357; RV32XVENTANACONDOPS: # %bb.0:3358; RV32XVENTANACONDOPS-NEXT: not a1, a13359; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -6543360; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13361; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a13362; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a13363; RV32XVENTANACONDOPS-NEXT: ret3364;3365; RV64XVENTANACONDOPS-LABEL: zero2_setne_constant:3366; RV64XVENTANACONDOPS: # %bb.0:3367; RV64XVENTANACONDOPS-NEXT: addi a0, a0, 6543368; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a03369; RV64XVENTANACONDOPS-NEXT: ret3370;3371; RV64XTHEADCONDMOV-LABEL: zero2_setne_constant:3372; RV64XTHEADCONDMOV: # %bb.0:3373; RV64XTHEADCONDMOV-NEXT: addi a0, a0, 6543374; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a03375; RV64XTHEADCONDMOV-NEXT: mv a0, a13376; RV64XTHEADCONDMOV-NEXT: ret3377;3378; RV32ZICOND-LABEL: zero2_setne_constant:3379; RV32ZICOND: # %bb.0:3380; RV32ZICOND-NEXT: not a1, a13381; RV32ZICOND-NEXT: xori a0, a0, -6543382; RV32ZICOND-NEXT: or a1, a0, a13383; RV32ZICOND-NEXT: czero.nez a0, a2, a13384; RV32ZICOND-NEXT: czero.nez a1, a3, a13385; RV32ZICOND-NEXT: ret3386;3387; RV64ZICOND-LABEL: zero2_setne_constant:3388; RV64ZICOND: # %bb.0:3389; RV64ZICOND-NEXT: addi a0, a0, 6543390; RV64ZICOND-NEXT: czero.nez a0, a1, a03391; RV64ZICOND-NEXT: ret3392 %rc = icmp ne i64 %a, -6543393 %sel = select i1 %rc, i64 0, i64 %rs13394 ret i64 %sel3395}3396 3397define i64 @zero1_seteq_neg2048(i64 %a, i64 %rs1) {3398; RV32I-LABEL: zero1_seteq_neg2048:3399; RV32I: # %bb.0:3400; RV32I-NEXT: not a1, a13401; RV32I-NEXT: xori a0, a0, -20483402; RV32I-NEXT: or a0, a0, a13403; RV32I-NEXT: snez a0, a03404; RV32I-NEXT: addi a1, a0, -13405; RV32I-NEXT: and a0, a1, a23406; RV32I-NEXT: and a1, a1, a33407; RV32I-NEXT: ret3408;3409; RV64I-LABEL: zero1_seteq_neg2048:3410; RV64I: # %bb.0:3411; RV64I-NEXT: xori a0, a0, -20483412; RV64I-NEXT: snez a0, a03413; RV64I-NEXT: addi a0, a0, -13414; RV64I-NEXT: and a0, a0, a13415; RV64I-NEXT: ret3416;3417; RV32XVENTANACONDOPS-LABEL: zero1_seteq_neg2048:3418; RV32XVENTANACONDOPS: # %bb.0:3419; RV32XVENTANACONDOPS-NEXT: not a1, a13420; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -20483421; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13422; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a13423; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a13424; RV32XVENTANACONDOPS-NEXT: ret3425;3426; RV64XVENTANACONDOPS-LABEL: zero1_seteq_neg2048:3427; RV64XVENTANACONDOPS: # %bb.0:3428; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -20483429; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a03430; RV64XVENTANACONDOPS-NEXT: ret3431;3432; RV64XTHEADCONDMOV-LABEL: zero1_seteq_neg2048:3433; RV64XTHEADCONDMOV: # %bb.0:3434; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -20483435; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a03436; RV64XTHEADCONDMOV-NEXT: mv a0, a13437; RV64XTHEADCONDMOV-NEXT: ret3438;3439; RV32ZICOND-LABEL: zero1_seteq_neg2048:3440; RV32ZICOND: # %bb.0:3441; RV32ZICOND-NEXT: not a1, a13442; RV32ZICOND-NEXT: xori a0, a0, -20483443; RV32ZICOND-NEXT: or a1, a0, a13444; RV32ZICOND-NEXT: czero.nez a0, a2, a13445; RV32ZICOND-NEXT: czero.nez a1, a3, a13446; RV32ZICOND-NEXT: ret3447;3448; RV64ZICOND-LABEL: zero1_seteq_neg2048:3449; RV64ZICOND: # %bb.0:3450; RV64ZICOND-NEXT: xori a0, a0, -20483451; RV64ZICOND-NEXT: czero.nez a0, a1, a03452; RV64ZICOND-NEXT: ret3453 %rc = icmp eq i64 %a, -20483454 %sel = select i1 %rc, i64 %rs1, i64 03455 ret i64 %sel3456}3457 3458define i64 @zero2_seteq_neg2048(i64 %a, i64 %rs1) {3459; RV32I-LABEL: zero2_seteq_neg2048:3460; RV32I: # %bb.0:3461; RV32I-NEXT: not a1, a13462; RV32I-NEXT: xori a0, a0, -20483463; RV32I-NEXT: or a0, a0, a13464; RV32I-NEXT: seqz a0, a03465; RV32I-NEXT: addi a1, a0, -13466; RV32I-NEXT: and a0, a1, a23467; RV32I-NEXT: and a1, a1, a33468; RV32I-NEXT: ret3469;3470; RV64I-LABEL: zero2_seteq_neg2048:3471; RV64I: # %bb.0:3472; RV64I-NEXT: xori a0, a0, -20483473; RV64I-NEXT: seqz a0, a03474; RV64I-NEXT: addi a0, a0, -13475; RV64I-NEXT: and a0, a0, a13476; RV64I-NEXT: ret3477;3478; RV32XVENTANACONDOPS-LABEL: zero2_seteq_neg2048:3479; RV32XVENTANACONDOPS: # %bb.0:3480; RV32XVENTANACONDOPS-NEXT: not a1, a13481; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -20483482; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13483; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a13484; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a13485; RV32XVENTANACONDOPS-NEXT: ret3486;3487; RV64XVENTANACONDOPS-LABEL: zero2_seteq_neg2048:3488; RV64XVENTANACONDOPS: # %bb.0:3489; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -20483490; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a03491; RV64XVENTANACONDOPS-NEXT: ret3492;3493; RV64XTHEADCONDMOV-LABEL: zero2_seteq_neg2048:3494; RV64XTHEADCONDMOV: # %bb.0:3495; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -20483496; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a03497; RV64XTHEADCONDMOV-NEXT: mv a0, a13498; RV64XTHEADCONDMOV-NEXT: ret3499;3500; RV32ZICOND-LABEL: zero2_seteq_neg2048:3501; RV32ZICOND: # %bb.0:3502; RV32ZICOND-NEXT: not a1, a13503; RV32ZICOND-NEXT: xori a0, a0, -20483504; RV32ZICOND-NEXT: or a1, a0, a13505; RV32ZICOND-NEXT: czero.eqz a0, a2, a13506; RV32ZICOND-NEXT: czero.eqz a1, a3, a13507; RV32ZICOND-NEXT: ret3508;3509; RV64ZICOND-LABEL: zero2_seteq_neg2048:3510; RV64ZICOND: # %bb.0:3511; RV64ZICOND-NEXT: xori a0, a0, -20483512; RV64ZICOND-NEXT: czero.eqz a0, a1, a03513; RV64ZICOND-NEXT: ret3514 %rc = icmp eq i64 %a, -20483515 %sel = select i1 %rc, i64 0, i64 %rs13516 ret i64 %sel3517}3518 3519define i64 @zero1_setne_neg2048(i64 %a, i64 %rs1) {3520; RV32I-LABEL: zero1_setne_neg2048:3521; RV32I: # %bb.0:3522; RV32I-NEXT: not a1, a13523; RV32I-NEXT: xori a0, a0, -20483524; RV32I-NEXT: or a0, a0, a13525; RV32I-NEXT: seqz a0, a03526; RV32I-NEXT: addi a1, a0, -13527; RV32I-NEXT: and a0, a1, a23528; RV32I-NEXT: and a1, a1, a33529; RV32I-NEXT: ret3530;3531; RV64I-LABEL: zero1_setne_neg2048:3532; RV64I: # %bb.0:3533; RV64I-NEXT: xori a0, a0, -20483534; RV64I-NEXT: seqz a0, a03535; RV64I-NEXT: addi a0, a0, -13536; RV64I-NEXT: and a0, a0, a13537; RV64I-NEXT: ret3538;3539; RV32XVENTANACONDOPS-LABEL: zero1_setne_neg2048:3540; RV32XVENTANACONDOPS: # %bb.0:3541; RV32XVENTANACONDOPS-NEXT: not a1, a13542; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -20483543; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13544; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a13545; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a13546; RV32XVENTANACONDOPS-NEXT: ret3547;3548; RV64XVENTANACONDOPS-LABEL: zero1_setne_neg2048:3549; RV64XVENTANACONDOPS: # %bb.0:3550; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -20483551; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a03552; RV64XVENTANACONDOPS-NEXT: ret3553;3554; RV64XTHEADCONDMOV-LABEL: zero1_setne_neg2048:3555; RV64XTHEADCONDMOV: # %bb.0:3556; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -20483557; RV64XTHEADCONDMOV-NEXT: th.mveqz a1, zero, a03558; RV64XTHEADCONDMOV-NEXT: mv a0, a13559; RV64XTHEADCONDMOV-NEXT: ret3560;3561; RV32ZICOND-LABEL: zero1_setne_neg2048:3562; RV32ZICOND: # %bb.0:3563; RV32ZICOND-NEXT: not a1, a13564; RV32ZICOND-NEXT: xori a0, a0, -20483565; RV32ZICOND-NEXT: or a1, a0, a13566; RV32ZICOND-NEXT: czero.eqz a0, a2, a13567; RV32ZICOND-NEXT: czero.eqz a1, a3, a13568; RV32ZICOND-NEXT: ret3569;3570; RV64ZICOND-LABEL: zero1_setne_neg2048:3571; RV64ZICOND: # %bb.0:3572; RV64ZICOND-NEXT: xori a0, a0, -20483573; RV64ZICOND-NEXT: czero.eqz a0, a1, a03574; RV64ZICOND-NEXT: ret3575 %rc = icmp ne i64 %a, -20483576 %sel = select i1 %rc, i64 %rs1, i64 03577 ret i64 %sel3578}3579 3580define i64 @zero2_setne_neg2048(i64 %a, i64 %rs1) {3581; RV32I-LABEL: zero2_setne_neg2048:3582; RV32I: # %bb.0:3583; RV32I-NEXT: not a1, a13584; RV32I-NEXT: xori a0, a0, -20483585; RV32I-NEXT: or a0, a0, a13586; RV32I-NEXT: snez a0, a03587; RV32I-NEXT: addi a1, a0, -13588; RV32I-NEXT: and a0, a1, a23589; RV32I-NEXT: and a1, a1, a33590; RV32I-NEXT: ret3591;3592; RV64I-LABEL: zero2_setne_neg2048:3593; RV64I: # %bb.0:3594; RV64I-NEXT: xori a0, a0, -20483595; RV64I-NEXT: snez a0, a03596; RV64I-NEXT: addi a0, a0, -13597; RV64I-NEXT: and a0, a0, a13598; RV64I-NEXT: ret3599;3600; RV32XVENTANACONDOPS-LABEL: zero2_setne_neg2048:3601; RV32XVENTANACONDOPS: # %bb.0:3602; RV32XVENTANACONDOPS-NEXT: not a1, a13603; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -20483604; RV32XVENTANACONDOPS-NEXT: or a1, a0, a13605; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a13606; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a13607; RV32XVENTANACONDOPS-NEXT: ret3608;3609; RV64XVENTANACONDOPS-LABEL: zero2_setne_neg2048:3610; RV64XVENTANACONDOPS: # %bb.0:3611; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -20483612; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a03613; RV64XVENTANACONDOPS-NEXT: ret3614;3615; RV64XTHEADCONDMOV-LABEL: zero2_setne_neg2048:3616; RV64XTHEADCONDMOV: # %bb.0:3617; RV64XTHEADCONDMOV-NEXT: xori a0, a0, -20483618; RV64XTHEADCONDMOV-NEXT: th.mvnez a1, zero, a03619; RV64XTHEADCONDMOV-NEXT: mv a0, a13620; RV64XTHEADCONDMOV-NEXT: ret3621;3622; RV32ZICOND-LABEL: zero2_setne_neg2048:3623; RV32ZICOND: # %bb.0:3624; RV32ZICOND-NEXT: not a1, a13625; RV32ZICOND-NEXT: xori a0, a0, -20483626; RV32ZICOND-NEXT: or a1, a0, a13627; RV32ZICOND-NEXT: czero.nez a0, a2, a13628; RV32ZICOND-NEXT: czero.nez a1, a3, a13629; RV32ZICOND-NEXT: ret3630;3631; RV64ZICOND-LABEL: zero2_setne_neg2048:3632; RV64ZICOND: # %bb.0:3633; RV64ZICOND-NEXT: xori a0, a0, -20483634; RV64ZICOND-NEXT: czero.nez a0, a1, a03635; RV64ZICOND-NEXT: ret3636 %rc = icmp ne i64 %a, -20483637 %sel = select i1 %rc, i64 0, i64 %rs13638 ret i64 %sel3639}3640 3641define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nounwind {3642; RV32I-LABEL: sextw_removal_maskc:3643; RV32I: # %bb.0: # %bb3644; RV32I-NEXT: addi sp, sp, -163645; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill3646; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill3647; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill3648; RV32I-NEXT: mv s0, a23649; RV32I-NEXT: slli a0, a0, 313650; RV32I-NEXT: srai a0, a0, 313651; RV32I-NEXT: and s1, a0, a13652; RV32I-NEXT: .LBB56_1: # %bb23653; RV32I-NEXT: # =>This Inner Loop Header: Depth=13654; RV32I-NEXT: mv a0, s13655; RV32I-NEXT: call bar3656; RV32I-NEXT: sll s1, s1, s03657; RV32I-NEXT: bnez a0, .LBB56_13658; RV32I-NEXT: # %bb.2: # %bb73659; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3660; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload3661; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload3662; RV32I-NEXT: addi sp, sp, 163663; RV32I-NEXT: ret3664;3665; RV64I-LABEL: sextw_removal_maskc:3666; RV64I: # %bb.0: # %bb3667; RV64I-NEXT: addi sp, sp, -323668; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill3669; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill3670; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill3671; RV64I-NEXT: mv s0, a23672; RV64I-NEXT: slli a0, a0, 633673; RV64I-NEXT: srai a0, a0, 633674; RV64I-NEXT: and s1, a0, a13675; RV64I-NEXT: .LBB56_1: # %bb23676; RV64I-NEXT: # =>This Inner Loop Header: Depth=13677; RV64I-NEXT: mv a0, s13678; RV64I-NEXT: call bar3679; RV64I-NEXT: sllw s1, s1, s03680; RV64I-NEXT: bnez a0, .LBB56_13681; RV64I-NEXT: # %bb.2: # %bb73682; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload3683; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload3684; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload3685; RV64I-NEXT: addi sp, sp, 323686; RV64I-NEXT: ret3687;3688; RV32XVENTANACONDOPS-LABEL: sextw_removal_maskc:3689; RV32XVENTANACONDOPS: # %bb.0: # %bb3690; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -163691; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill3692; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill3693; RV32XVENTANACONDOPS-NEXT: sw s1, 4(sp) # 4-byte Folded Spill3694; RV32XVENTANACONDOPS-NEXT: mv s0, a23695; RV32XVENTANACONDOPS-NEXT: andi a0, a0, 13696; RV32XVENTANACONDOPS-NEXT: vt.maskc s1, a1, a03697; RV32XVENTANACONDOPS-NEXT: .LBB56_1: # %bb23698; RV32XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=13699; RV32XVENTANACONDOPS-NEXT: mv a0, s13700; RV32XVENTANACONDOPS-NEXT: call bar3701; RV32XVENTANACONDOPS-NEXT: sll s1, s1, s03702; RV32XVENTANACONDOPS-NEXT: bnez a0, .LBB56_13703; RV32XVENTANACONDOPS-NEXT: # %bb.2: # %bb73704; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3705; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload3706; RV32XVENTANACONDOPS-NEXT: lw s1, 4(sp) # 4-byte Folded Reload3707; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 163708; RV32XVENTANACONDOPS-NEXT: ret3709;3710; RV64XVENTANACONDOPS-LABEL: sextw_removal_maskc:3711; RV64XVENTANACONDOPS: # %bb.0: # %bb3712; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -323713; RV64XVENTANACONDOPS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill3714; RV64XVENTANACONDOPS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill3715; RV64XVENTANACONDOPS-NEXT: sd s1, 8(sp) # 8-byte Folded Spill3716; RV64XVENTANACONDOPS-NEXT: mv s0, a23717; RV64XVENTANACONDOPS-NEXT: andi a0, a0, 13718; RV64XVENTANACONDOPS-NEXT: vt.maskc s1, a1, a03719; RV64XVENTANACONDOPS-NEXT: .LBB56_1: # %bb23720; RV64XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=13721; RV64XVENTANACONDOPS-NEXT: mv a0, s13722; RV64XVENTANACONDOPS-NEXT: call bar3723; RV64XVENTANACONDOPS-NEXT: sllw s1, s1, s03724; RV64XVENTANACONDOPS-NEXT: bnez a0, .LBB56_13725; RV64XVENTANACONDOPS-NEXT: # %bb.2: # %bb73726; RV64XVENTANACONDOPS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload3727; RV64XVENTANACONDOPS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload3728; RV64XVENTANACONDOPS-NEXT: ld s1, 8(sp) # 8-byte Folded Reload3729; RV64XVENTANACONDOPS-NEXT: addi sp, sp, 323730; RV64XVENTANACONDOPS-NEXT: ret3731;3732; RV64XTHEADCONDMOV-LABEL: sextw_removal_maskc:3733; RV64XTHEADCONDMOV: # %bb.0: # %bb3734; RV64XTHEADCONDMOV-NEXT: addi sp, sp, -323735; RV64XTHEADCONDMOV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill3736; RV64XTHEADCONDMOV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill3737; RV64XTHEADCONDMOV-NEXT: sd s1, 8(sp) # 8-byte Folded Spill3738; RV64XTHEADCONDMOV-NEXT: mv s0, a23739; RV64XTHEADCONDMOV-NEXT: mv s1, a13740; RV64XTHEADCONDMOV-NEXT: andi a0, a0, 13741; RV64XTHEADCONDMOV-NEXT: th.mveqz s1, zero, a03742; RV64XTHEADCONDMOV-NEXT: .LBB56_1: # %bb23743; RV64XTHEADCONDMOV-NEXT: # =>This Inner Loop Header: Depth=13744; RV64XTHEADCONDMOV-NEXT: sext.w a0, s13745; RV64XTHEADCONDMOV-NEXT: call bar3746; RV64XTHEADCONDMOV-NEXT: sllw s1, s1, s03747; RV64XTHEADCONDMOV-NEXT: bnez a0, .LBB56_13748; RV64XTHEADCONDMOV-NEXT: # %bb.2: # %bb73749; RV64XTHEADCONDMOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload3750; RV64XTHEADCONDMOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload3751; RV64XTHEADCONDMOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload3752; RV64XTHEADCONDMOV-NEXT: addi sp, sp, 323753; RV64XTHEADCONDMOV-NEXT: ret3754;3755; RV32ZICOND-LABEL: sextw_removal_maskc:3756; RV32ZICOND: # %bb.0: # %bb3757; RV32ZICOND-NEXT: addi sp, sp, -163758; RV32ZICOND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill3759; RV32ZICOND-NEXT: sw s0, 8(sp) # 4-byte Folded Spill3760; RV32ZICOND-NEXT: sw s1, 4(sp) # 4-byte Folded Spill3761; RV32ZICOND-NEXT: mv s0, a23762; RV32ZICOND-NEXT: andi a0, a0, 13763; RV32ZICOND-NEXT: czero.eqz s1, a1, a03764; RV32ZICOND-NEXT: .LBB56_1: # %bb23765; RV32ZICOND-NEXT: # =>This Inner Loop Header: Depth=13766; RV32ZICOND-NEXT: mv a0, s13767; RV32ZICOND-NEXT: call bar3768; RV32ZICOND-NEXT: sll s1, s1, s03769; RV32ZICOND-NEXT: bnez a0, .LBB56_13770; RV32ZICOND-NEXT: # %bb.2: # %bb73771; RV32ZICOND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3772; RV32ZICOND-NEXT: lw s0, 8(sp) # 4-byte Folded Reload3773; RV32ZICOND-NEXT: lw s1, 4(sp) # 4-byte Folded Reload3774; RV32ZICOND-NEXT: addi sp, sp, 163775; RV32ZICOND-NEXT: ret3776;3777; RV64ZICOND-LABEL: sextw_removal_maskc:3778; RV64ZICOND: # %bb.0: # %bb3779; RV64ZICOND-NEXT: addi sp, sp, -323780; RV64ZICOND-NEXT: sd ra, 24(sp) # 8-byte Folded Spill3781; RV64ZICOND-NEXT: sd s0, 16(sp) # 8-byte Folded Spill3782; RV64ZICOND-NEXT: sd s1, 8(sp) # 8-byte Folded Spill3783; RV64ZICOND-NEXT: mv s0, a23784; RV64ZICOND-NEXT: andi a0, a0, 13785; RV64ZICOND-NEXT: czero.eqz s1, a1, a03786; RV64ZICOND-NEXT: .LBB56_1: # %bb23787; RV64ZICOND-NEXT: # =>This Inner Loop Header: Depth=13788; RV64ZICOND-NEXT: mv a0, s13789; RV64ZICOND-NEXT: call bar3790; RV64ZICOND-NEXT: sllw s1, s1, s03791; RV64ZICOND-NEXT: bnez a0, .LBB56_13792; RV64ZICOND-NEXT: # %bb.2: # %bb73793; RV64ZICOND-NEXT: ld ra, 24(sp) # 8-byte Folded Reload3794; RV64ZICOND-NEXT: ld s0, 16(sp) # 8-byte Folded Reload3795; RV64ZICOND-NEXT: ld s1, 8(sp) # 8-byte Folded Reload3796; RV64ZICOND-NEXT: addi sp, sp, 323797; RV64ZICOND-NEXT: ret3798bb:3799 %i = select i1 %c, i32 %arg, i32 03800 br label %bb23801 3802bb2: ; preds = %bb2, %bb3803 %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]3804 %i4 = tail call signext i32 @bar(i32 signext %i3)3805 %i5 = shl i32 %i3, %arg13806 %i6 = icmp eq i32 %i4, 03807 br i1 %i6, label %bb7, label %bb23808 3809bb7: ; preds = %bb23810 ret void3811}3812declare signext i32 @bar(i32 signext)3813 3814define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) nounwind {3815; RV32I-LABEL: sextw_removal_maskcn:3816; RV32I: # %bb.0: # %bb3817; RV32I-NEXT: addi sp, sp, -163818; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill3819; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill3820; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill3821; RV32I-NEXT: mv s0, a23822; RV32I-NEXT: andi a0, a0, 13823; RV32I-NEXT: addi a0, a0, -13824; RV32I-NEXT: and s1, a0, a13825; RV32I-NEXT: .LBB57_1: # %bb23826; RV32I-NEXT: # =>This Inner Loop Header: Depth=13827; RV32I-NEXT: mv a0, s13828; RV32I-NEXT: call bar3829; RV32I-NEXT: sll s1, s1, s03830; RV32I-NEXT: bnez a0, .LBB57_13831; RV32I-NEXT: # %bb.2: # %bb73832; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3833; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload3834; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload3835; RV32I-NEXT: addi sp, sp, 163836; RV32I-NEXT: ret3837;3838; RV64I-LABEL: sextw_removal_maskcn:3839; RV64I: # %bb.0: # %bb3840; RV64I-NEXT: addi sp, sp, -323841; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill3842; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill3843; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill3844; RV64I-NEXT: mv s0, a23845; RV64I-NEXT: andi a0, a0, 13846; RV64I-NEXT: addiw a0, a0, -13847; RV64I-NEXT: and s1, a0, a13848; RV64I-NEXT: .LBB57_1: # %bb23849; RV64I-NEXT: # =>This Inner Loop Header: Depth=13850; RV64I-NEXT: mv a0, s13851; RV64I-NEXT: call bar3852; RV64I-NEXT: sllw s1, s1, s03853; RV64I-NEXT: bnez a0, .LBB57_13854; RV64I-NEXT: # %bb.2: # %bb73855; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload3856; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload3857; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload3858; RV64I-NEXT: addi sp, sp, 323859; RV64I-NEXT: ret3860;3861; RV32XVENTANACONDOPS-LABEL: sextw_removal_maskcn:3862; RV32XVENTANACONDOPS: # %bb.0: # %bb3863; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -163864; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill3865; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill3866; RV32XVENTANACONDOPS-NEXT: sw s1, 4(sp) # 4-byte Folded Spill3867; RV32XVENTANACONDOPS-NEXT: mv s0, a23868; RV32XVENTANACONDOPS-NEXT: andi a0, a0, 13869; RV32XVENTANACONDOPS-NEXT: vt.maskcn s1, a1, a03870; RV32XVENTANACONDOPS-NEXT: .LBB57_1: # %bb23871; RV32XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=13872; RV32XVENTANACONDOPS-NEXT: mv a0, s13873; RV32XVENTANACONDOPS-NEXT: call bar3874; RV32XVENTANACONDOPS-NEXT: sll s1, s1, s03875; RV32XVENTANACONDOPS-NEXT: bnez a0, .LBB57_13876; RV32XVENTANACONDOPS-NEXT: # %bb.2: # %bb73877; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3878; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload3879; RV32XVENTANACONDOPS-NEXT: lw s1, 4(sp) # 4-byte Folded Reload3880; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 163881; RV32XVENTANACONDOPS-NEXT: ret3882;3883; RV64XVENTANACONDOPS-LABEL: sextw_removal_maskcn:3884; RV64XVENTANACONDOPS: # %bb.0: # %bb3885; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -323886; RV64XVENTANACONDOPS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill3887; RV64XVENTANACONDOPS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill3888; RV64XVENTANACONDOPS-NEXT: sd s1, 8(sp) # 8-byte Folded Spill3889; RV64XVENTANACONDOPS-NEXT: mv s0, a23890; RV64XVENTANACONDOPS-NEXT: andi a0, a0, 13891; RV64XVENTANACONDOPS-NEXT: vt.maskcn s1, a1, a03892; RV64XVENTANACONDOPS-NEXT: .LBB57_1: # %bb23893; RV64XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=13894; RV64XVENTANACONDOPS-NEXT: mv a0, s13895; RV64XVENTANACONDOPS-NEXT: call bar3896; RV64XVENTANACONDOPS-NEXT: sllw s1, s1, s03897; RV64XVENTANACONDOPS-NEXT: bnez a0, .LBB57_13898; RV64XVENTANACONDOPS-NEXT: # %bb.2: # %bb73899; RV64XVENTANACONDOPS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload3900; RV64XVENTANACONDOPS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload3901; RV64XVENTANACONDOPS-NEXT: ld s1, 8(sp) # 8-byte Folded Reload3902; RV64XVENTANACONDOPS-NEXT: addi sp, sp, 323903; RV64XVENTANACONDOPS-NEXT: ret3904;3905; RV64XTHEADCONDMOV-LABEL: sextw_removal_maskcn:3906; RV64XTHEADCONDMOV: # %bb.0: # %bb3907; RV64XTHEADCONDMOV-NEXT: addi sp, sp, -323908; RV64XTHEADCONDMOV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill3909; RV64XTHEADCONDMOV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill3910; RV64XTHEADCONDMOV-NEXT: sd s1, 8(sp) # 8-byte Folded Spill3911; RV64XTHEADCONDMOV-NEXT: mv s0, a23912; RV64XTHEADCONDMOV-NEXT: mv s1, a13913; RV64XTHEADCONDMOV-NEXT: andi a0, a0, 13914; RV64XTHEADCONDMOV-NEXT: th.mvnez s1, zero, a03915; RV64XTHEADCONDMOV-NEXT: .LBB57_1: # %bb23916; RV64XTHEADCONDMOV-NEXT: # =>This Inner Loop Header: Depth=13917; RV64XTHEADCONDMOV-NEXT: sext.w a0, s13918; RV64XTHEADCONDMOV-NEXT: call bar3919; RV64XTHEADCONDMOV-NEXT: sllw s1, s1, s03920; RV64XTHEADCONDMOV-NEXT: bnez a0, .LBB57_13921; RV64XTHEADCONDMOV-NEXT: # %bb.2: # %bb73922; RV64XTHEADCONDMOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload3923; RV64XTHEADCONDMOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload3924; RV64XTHEADCONDMOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload3925; RV64XTHEADCONDMOV-NEXT: addi sp, sp, 323926; RV64XTHEADCONDMOV-NEXT: ret3927;3928; RV32ZICOND-LABEL: sextw_removal_maskcn:3929; RV32ZICOND: # %bb.0: # %bb3930; RV32ZICOND-NEXT: addi sp, sp, -163931; RV32ZICOND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill3932; RV32ZICOND-NEXT: sw s0, 8(sp) # 4-byte Folded Spill3933; RV32ZICOND-NEXT: sw s1, 4(sp) # 4-byte Folded Spill3934; RV32ZICOND-NEXT: mv s0, a23935; RV32ZICOND-NEXT: andi a0, a0, 13936; RV32ZICOND-NEXT: czero.nez s1, a1, a03937; RV32ZICOND-NEXT: .LBB57_1: # %bb23938; RV32ZICOND-NEXT: # =>This Inner Loop Header: Depth=13939; RV32ZICOND-NEXT: mv a0, s13940; RV32ZICOND-NEXT: call bar3941; RV32ZICOND-NEXT: sll s1, s1, s03942; RV32ZICOND-NEXT: bnez a0, .LBB57_13943; RV32ZICOND-NEXT: # %bb.2: # %bb73944; RV32ZICOND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload3945; RV32ZICOND-NEXT: lw s0, 8(sp) # 4-byte Folded Reload3946; RV32ZICOND-NEXT: lw s1, 4(sp) # 4-byte Folded Reload3947; RV32ZICOND-NEXT: addi sp, sp, 163948; RV32ZICOND-NEXT: ret3949;3950; RV64ZICOND-LABEL: sextw_removal_maskcn:3951; RV64ZICOND: # %bb.0: # %bb3952; RV64ZICOND-NEXT: addi sp, sp, -323953; RV64ZICOND-NEXT: sd ra, 24(sp) # 8-byte Folded Spill3954; RV64ZICOND-NEXT: sd s0, 16(sp) # 8-byte Folded Spill3955; RV64ZICOND-NEXT: sd s1, 8(sp) # 8-byte Folded Spill3956; RV64ZICOND-NEXT: mv s0, a23957; RV64ZICOND-NEXT: andi a0, a0, 13958; RV64ZICOND-NEXT: czero.nez s1, a1, a03959; RV64ZICOND-NEXT: .LBB57_1: # %bb23960; RV64ZICOND-NEXT: # =>This Inner Loop Header: Depth=13961; RV64ZICOND-NEXT: mv a0, s13962; RV64ZICOND-NEXT: call bar3963; RV64ZICOND-NEXT: sllw s1, s1, s03964; RV64ZICOND-NEXT: bnez a0, .LBB57_13965; RV64ZICOND-NEXT: # %bb.2: # %bb73966; RV64ZICOND-NEXT: ld ra, 24(sp) # 8-byte Folded Reload3967; RV64ZICOND-NEXT: ld s0, 16(sp) # 8-byte Folded Reload3968; RV64ZICOND-NEXT: ld s1, 8(sp) # 8-byte Folded Reload3969; RV64ZICOND-NEXT: addi sp, sp, 323970; RV64ZICOND-NEXT: ret3971bb:3972 %i = select i1 %c, i32 0, i32 %arg3973 br label %bb23974 3975bb2: ; preds = %bb2, %bb3976 %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]3977 %i4 = tail call signext i32 @bar(i32 signext %i3)3978 %i5 = shl i32 %i3, %arg13979 %i6 = icmp eq i32 %i4, 03980 br i1 %i6, label %bb7, label %bb23981 3982bb7: ; preds = %bb23983 ret void3984}3985 3986define i32 @setune_32(float %a, float %b, i32 %rs1, i32 %rs2) {3987; RV32I-LABEL: setune_32:3988; RV32I: # %bb.0:3989; RV32I-NEXT: feq.s a2, fa0, fa13990; RV32I-NEXT: beqz a2, .LBB58_23991; RV32I-NEXT: # %bb.1:3992; RV32I-NEXT: mv a0, a13993; RV32I-NEXT: .LBB58_2:3994; RV32I-NEXT: ret3995;3996; RV64I-LABEL: setune_32:3997; RV64I: # %bb.0:3998; RV64I-NEXT: feq.s a2, fa0, fa13999; RV64I-NEXT: beqz a2, .LBB58_24000; RV64I-NEXT: # %bb.1:4001; RV64I-NEXT: mv a0, a14002; RV64I-NEXT: .LBB58_2:4003; RV64I-NEXT: ret4004;4005; RV32XVENTANACONDOPS-LABEL: setune_32:4006; RV32XVENTANACONDOPS: # %bb.0:4007; RV32XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa14008; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a24009; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a24010; RV32XVENTANACONDOPS-NEXT: or a0, a0, a14011; RV32XVENTANACONDOPS-NEXT: ret4012;4013; RV64XVENTANACONDOPS-LABEL: setune_32:4014; RV64XVENTANACONDOPS: # %bb.0:4015; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa14016; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a24017; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a24018; RV64XVENTANACONDOPS-NEXT: or a0, a0, a14019; RV64XVENTANACONDOPS-NEXT: ret4020;4021; RV64XTHEADCONDMOV-LABEL: setune_32:4022; RV64XTHEADCONDMOV: # %bb.0:4023; RV64XTHEADCONDMOV-NEXT: feq.s a2, fa0, fa14024; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a24025; RV64XTHEADCONDMOV-NEXT: ret4026;4027; RV32ZICOND-LABEL: setune_32:4028; RV32ZICOND: # %bb.0:4029; RV32ZICOND-NEXT: feq.s a2, fa0, fa14030; RV32ZICOND-NEXT: czero.eqz a1, a1, a24031; RV32ZICOND-NEXT: czero.nez a0, a0, a24032; RV32ZICOND-NEXT: or a0, a0, a14033; RV32ZICOND-NEXT: ret4034;4035; RV64ZICOND-LABEL: setune_32:4036; RV64ZICOND: # %bb.0:4037; RV64ZICOND-NEXT: feq.s a2, fa0, fa14038; RV64ZICOND-NEXT: czero.eqz a1, a1, a24039; RV64ZICOND-NEXT: czero.nez a0, a0, a24040; RV64ZICOND-NEXT: or a0, a0, a14041; RV64ZICOND-NEXT: ret4042 %rc = fcmp une float %a, %b4043 %sel = select i1 %rc, i32 %rs1, i32 %rs24044 ret i32 %sel4045}4046 4047define i64 @setune_64(float %a, float %b, i64 %rs1, i64 %rs2) {4048; RV32I-LABEL: setune_64:4049; RV32I: # %bb.0:4050; RV32I-NEXT: feq.s a4, fa0, fa14051; RV32I-NEXT: beqz a4, .LBB59_24052; RV32I-NEXT: # %bb.1:4053; RV32I-NEXT: mv a0, a24054; RV32I-NEXT: mv a1, a34055; RV32I-NEXT: .LBB59_2:4056; RV32I-NEXT: ret4057;4058; RV64I-LABEL: setune_64:4059; RV64I: # %bb.0:4060; RV64I-NEXT: feq.s a2, fa0, fa14061; RV64I-NEXT: beqz a2, .LBB59_24062; RV64I-NEXT: # %bb.1:4063; RV64I-NEXT: mv a0, a14064; RV64I-NEXT: .LBB59_2:4065; RV64I-NEXT: ret4066;4067; RV32XVENTANACONDOPS-LABEL: setune_64:4068; RV32XVENTANACONDOPS: # %bb.0:4069; RV32XVENTANACONDOPS-NEXT: feq.s a4, fa0, fa14070; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a44071; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a44072; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a44073; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a44074; RV32XVENTANACONDOPS-NEXT: or a0, a0, a24075; RV32XVENTANACONDOPS-NEXT: or a1, a1, a34076; RV32XVENTANACONDOPS-NEXT: ret4077;4078; RV64XVENTANACONDOPS-LABEL: setune_64:4079; RV64XVENTANACONDOPS: # %bb.0:4080; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa14081; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a24082; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a24083; RV64XVENTANACONDOPS-NEXT: or a0, a0, a14084; RV64XVENTANACONDOPS-NEXT: ret4085;4086; RV64XTHEADCONDMOV-LABEL: setune_64:4087; RV64XTHEADCONDMOV: # %bb.0:4088; RV64XTHEADCONDMOV-NEXT: feq.s a2, fa0, fa14089; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a24090; RV64XTHEADCONDMOV-NEXT: ret4091;4092; RV32ZICOND-LABEL: setune_64:4093; RV32ZICOND: # %bb.0:4094; RV32ZICOND-NEXT: feq.s a4, fa0, fa14095; RV32ZICOND-NEXT: czero.eqz a2, a2, a44096; RV32ZICOND-NEXT: czero.nez a0, a0, a44097; RV32ZICOND-NEXT: czero.eqz a3, a3, a44098; RV32ZICOND-NEXT: czero.nez a1, a1, a44099; RV32ZICOND-NEXT: or a0, a0, a24100; RV32ZICOND-NEXT: or a1, a1, a34101; RV32ZICOND-NEXT: ret4102;4103; RV64ZICOND-LABEL: setune_64:4104; RV64ZICOND: # %bb.0:4105; RV64ZICOND-NEXT: feq.s a2, fa0, fa14106; RV64ZICOND-NEXT: czero.eqz a1, a1, a24107; RV64ZICOND-NEXT: czero.nez a0, a0, a24108; RV64ZICOND-NEXT: or a0, a0, a14109; RV64ZICOND-NEXT: ret4110 %rc = fcmp une float %a, %b4111 %sel = select i1 %rc, i64 %rs1, i64 %rs24112 ret i64 %sel4113}4114 4115; Test that we can ComputeNumSignBits across basic blocks when the live out is4116; RISCVISD::SELECT_CC. There should be no slli+srai or sext.h in the output.4117define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) nounwind {4118; RV32I-LABEL: numsignbits:4119; RV32I: # %bb.0:4120; RV32I-NEXT: addi sp, sp, -164121; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill4122; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill4123; RV32I-NEXT: mv s0, a34124; RV32I-NEXT: beqz a0, .LBB60_24125; RV32I-NEXT: # %bb.1:4126; RV32I-NEXT: mv s0, a24127; RV32I-NEXT: .LBB60_2:4128; RV32I-NEXT: beqz a1, .LBB60_44129; RV32I-NEXT: # %bb.3:4130; RV32I-NEXT: mv a0, s04131; RV32I-NEXT: call bat4132; RV32I-NEXT: .LBB60_4:4133; RV32I-NEXT: mv a0, s04134; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload4135; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload4136; RV32I-NEXT: addi sp, sp, 164137; RV32I-NEXT: ret4138;4139; RV64I-LABEL: numsignbits:4140; RV64I: # %bb.0:4141; RV64I-NEXT: addi sp, sp, -164142; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill4143; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill4144; RV64I-NEXT: mv s0, a34145; RV64I-NEXT: beqz a0, .LBB60_24146; RV64I-NEXT: # %bb.1:4147; RV64I-NEXT: mv s0, a24148; RV64I-NEXT: .LBB60_2:4149; RV64I-NEXT: beqz a1, .LBB60_44150; RV64I-NEXT: # %bb.3:4151; RV64I-NEXT: mv a0, s04152; RV64I-NEXT: call bat4153; RV64I-NEXT: .LBB60_4:4154; RV64I-NEXT: mv a0, s04155; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload4156; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload4157; RV64I-NEXT: addi sp, sp, 164158; RV64I-NEXT: ret4159;4160; RV32XVENTANACONDOPS-LABEL: numsignbits:4161; RV32XVENTANACONDOPS: # %bb.0:4162; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -164163; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill4164; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill4165; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a04166; RV32XVENTANACONDOPS-NEXT: vt.maskcn s0, a3, a04167; RV32XVENTANACONDOPS-NEXT: or s0, s0, a24168; RV32XVENTANACONDOPS-NEXT: beqz a1, .LBB60_24169; RV32XVENTANACONDOPS-NEXT: # %bb.1:4170; RV32XVENTANACONDOPS-NEXT: mv a0, s04171; RV32XVENTANACONDOPS-NEXT: call bat4172; RV32XVENTANACONDOPS-NEXT: .LBB60_2:4173; RV32XVENTANACONDOPS-NEXT: mv a0, s04174; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload4175; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload4176; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 164177; RV32XVENTANACONDOPS-NEXT: ret4178;4179; RV64XVENTANACONDOPS-LABEL: numsignbits:4180; RV64XVENTANACONDOPS: # %bb.0:4181; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -164182; RV64XVENTANACONDOPS-NEXT: sd ra, 8(sp) # 8-byte Folded Spill4183; RV64XVENTANACONDOPS-NEXT: sd s0, 0(sp) # 8-byte Folded Spill4184; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a04185; RV64XVENTANACONDOPS-NEXT: vt.maskcn s0, a3, a04186; RV64XVENTANACONDOPS-NEXT: or s0, s0, a24187; RV64XVENTANACONDOPS-NEXT: beqz a1, .LBB60_24188; RV64XVENTANACONDOPS-NEXT: # %bb.1:4189; RV64XVENTANACONDOPS-NEXT: mv a0, s04190; RV64XVENTANACONDOPS-NEXT: call bat4191; RV64XVENTANACONDOPS-NEXT: .LBB60_2:4192; RV64XVENTANACONDOPS-NEXT: mv a0, s04193; RV64XVENTANACONDOPS-NEXT: ld ra, 8(sp) # 8-byte Folded Reload4194; RV64XVENTANACONDOPS-NEXT: ld s0, 0(sp) # 8-byte Folded Reload4195; RV64XVENTANACONDOPS-NEXT: addi sp, sp, 164196; RV64XVENTANACONDOPS-NEXT: ret4197;4198; RV64XTHEADCONDMOV-LABEL: numsignbits:4199; RV64XTHEADCONDMOV: # %bb.0:4200; RV64XTHEADCONDMOV-NEXT: addi sp, sp, -164201; RV64XTHEADCONDMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill4202; RV64XTHEADCONDMOV-NEXT: sd s0, 0(sp) # 8-byte Folded Spill4203; RV64XTHEADCONDMOV-NEXT: mv s0, a24204; RV64XTHEADCONDMOV-NEXT: th.mveqz s0, a3, a04205; RV64XTHEADCONDMOV-NEXT: beqz a1, .LBB60_24206; RV64XTHEADCONDMOV-NEXT: # %bb.1:4207; RV64XTHEADCONDMOV-NEXT: mv a0, s04208; RV64XTHEADCONDMOV-NEXT: call bat4209; RV64XTHEADCONDMOV-NEXT: .LBB60_2:4210; RV64XTHEADCONDMOV-NEXT: mv a0, s04211; RV64XTHEADCONDMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload4212; RV64XTHEADCONDMOV-NEXT: ld s0, 0(sp) # 8-byte Folded Reload4213; RV64XTHEADCONDMOV-NEXT: addi sp, sp, 164214; RV64XTHEADCONDMOV-NEXT: ret4215;4216; RV32ZICOND-LABEL: numsignbits:4217; RV32ZICOND: # %bb.0:4218; RV32ZICOND-NEXT: addi sp, sp, -164219; RV32ZICOND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill4220; RV32ZICOND-NEXT: sw s0, 8(sp) # 4-byte Folded Spill4221; RV32ZICOND-NEXT: czero.eqz a2, a2, a04222; RV32ZICOND-NEXT: czero.nez s0, a3, a04223; RV32ZICOND-NEXT: or s0, s0, a24224; RV32ZICOND-NEXT: beqz a1, .LBB60_24225; RV32ZICOND-NEXT: # %bb.1:4226; RV32ZICOND-NEXT: mv a0, s04227; RV32ZICOND-NEXT: call bat4228; RV32ZICOND-NEXT: .LBB60_2:4229; RV32ZICOND-NEXT: mv a0, s04230; RV32ZICOND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload4231; RV32ZICOND-NEXT: lw s0, 8(sp) # 4-byte Folded Reload4232; RV32ZICOND-NEXT: addi sp, sp, 164233; RV32ZICOND-NEXT: ret4234;4235; RV64ZICOND-LABEL: numsignbits:4236; RV64ZICOND: # %bb.0:4237; RV64ZICOND-NEXT: addi sp, sp, -164238; RV64ZICOND-NEXT: sd ra, 8(sp) # 8-byte Folded Spill4239; RV64ZICOND-NEXT: sd s0, 0(sp) # 8-byte Folded Spill4240; RV64ZICOND-NEXT: czero.eqz a2, a2, a04241; RV64ZICOND-NEXT: czero.nez s0, a3, a04242; RV64ZICOND-NEXT: or s0, s0, a24243; RV64ZICOND-NEXT: beqz a1, .LBB60_24244; RV64ZICOND-NEXT: # %bb.1:4245; RV64ZICOND-NEXT: mv a0, s04246; RV64ZICOND-NEXT: call bat4247; RV64ZICOND-NEXT: .LBB60_2:4248; RV64ZICOND-NEXT: mv a0, s04249; RV64ZICOND-NEXT: ld ra, 8(sp) # 8-byte Folded Reload4250; RV64ZICOND-NEXT: ld s0, 0(sp) # 8-byte Folded Reload4251; RV64ZICOND-NEXT: addi sp, sp, 164252; RV64ZICOND-NEXT: ret4253 %5 = icmp eq i16 %0, 04254 %6 = select i1 %5, i16 %3, i16 %24255 %7 = icmp eq i16 %1, 04256 br i1 %7, label %9, label %84257 42588: ; preds = %44259 tail call void @bat(i16 signext %6)4260 br label %94261 42629: ; preds = %8, %44263 ret i16 %64264}4265 4266declare void @bat(i16 signext)4267 4268define i64 @single_bit(i64 %x) {4269; RV32I-LABEL: single_bit:4270; RV32I: # %bb.0: # %entry4271; RV32I-NEXT: slli a2, a0, 214272; RV32I-NEXT: srai a2, a2, 314273; RV32I-NEXT: and a0, a2, a04274; RV32I-NEXT: and a1, a2, a14275; RV32I-NEXT: ret4276;4277; RV64I-LABEL: single_bit:4278; RV64I: # %bb.0: # %entry4279; RV64I-NEXT: slli a1, a0, 534280; RV64I-NEXT: srai a1, a1, 634281; RV64I-NEXT: and a0, a1, a04282; RV64I-NEXT: ret4283;4284; RV32XVENTANACONDOPS-LABEL: single_bit:4285; RV32XVENTANACONDOPS: # %bb.0: # %entry4286; RV32XVENTANACONDOPS-NEXT: andi a2, a0, 10244287; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a24288; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a24289; RV32XVENTANACONDOPS-NEXT: ret4290;4291; RV64XVENTANACONDOPS-LABEL: single_bit:4292; RV64XVENTANACONDOPS: # %bb.0: # %entry4293; RV64XVENTANACONDOPS-NEXT: andi a1, a0, 10244294; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a14295; RV64XVENTANACONDOPS-NEXT: ret4296;4297; RV64XTHEADCONDMOV-LABEL: single_bit:4298; RV64XTHEADCONDMOV: # %bb.0: # %entry4299; RV64XTHEADCONDMOV-NEXT: andi a1, a0, 10244300; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a14301; RV64XTHEADCONDMOV-NEXT: ret4302;4303; RV32ZICOND-LABEL: single_bit:4304; RV32ZICOND: # %bb.0: # %entry4305; RV32ZICOND-NEXT: andi a2, a0, 10244306; RV32ZICOND-NEXT: czero.eqz a0, a0, a24307; RV32ZICOND-NEXT: czero.eqz a1, a1, a24308; RV32ZICOND-NEXT: ret4309;4310; RV64ZICOND-LABEL: single_bit:4311; RV64ZICOND: # %bb.0: # %entry4312; RV64ZICOND-NEXT: andi a1, a0, 10244313; RV64ZICOND-NEXT: czero.eqz a0, a0, a14314; RV64ZICOND-NEXT: ret4315entry:4316 %and = and i64 %x, 10244317 %tobool.not = icmp eq i64 %and, 04318 %cond = select i1 %tobool.not, i64 0, i64 %x4319 ret i64 %cond4320}4321 4322; Test to fold select with single bit check to (and (sra (shl x))).4323define i64 @single_bit2(i64 %x) {4324; RV32I-LABEL: single_bit2:4325; RV32I: # %bb.0: # %entry4326; RV32I-NEXT: slli a2, a0, 204327; RV32I-NEXT: srai a2, a2, 314328; RV32I-NEXT: and a0, a2, a04329; RV32I-NEXT: and a1, a2, a14330; RV32I-NEXT: ret4331;4332; RV64I-LABEL: single_bit2:4333; RV64I: # %bb.0: # %entry4334; RV64I-NEXT: slli a1, a0, 524335; RV64I-NEXT: srai a1, a1, 634336; RV64I-NEXT: and a0, a1, a04337; RV64I-NEXT: ret4338;4339; RV32XVENTANACONDOPS-LABEL: single_bit2:4340; RV32XVENTANACONDOPS: # %bb.0: # %entry4341; RV32XVENTANACONDOPS-NEXT: bexti a2, a0, 114342; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a24343; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a24344; RV32XVENTANACONDOPS-NEXT: ret4345;4346; RV64XVENTANACONDOPS-LABEL: single_bit2:4347; RV64XVENTANACONDOPS: # %bb.0: # %entry4348; RV64XVENTANACONDOPS-NEXT: bexti a1, a0, 114349; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a14350; RV64XVENTANACONDOPS-NEXT: ret4351;4352; RV64XTHEADCONDMOV-LABEL: single_bit2:4353; RV64XTHEADCONDMOV: # %bb.0: # %entry4354; RV64XTHEADCONDMOV-NEXT: th.tst a1, a0, 114355; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a14356; RV64XTHEADCONDMOV-NEXT: ret4357;4358; RV32ZICOND-LABEL: single_bit2:4359; RV32ZICOND: # %bb.0: # %entry4360; RV32ZICOND-NEXT: bexti a2, a0, 114361; RV32ZICOND-NEXT: czero.eqz a0, a0, a24362; RV32ZICOND-NEXT: czero.eqz a1, a1, a24363; RV32ZICOND-NEXT: ret4364;4365; RV64ZICOND-LABEL: single_bit2:4366; RV64ZICOND: # %bb.0: # %entry4367; RV64ZICOND-NEXT: bexti a1, a0, 114368; RV64ZICOND-NEXT: czero.eqz a0, a0, a14369; RV64ZICOND-NEXT: ret4370entry:4371 %and = and i64 %x, 20484372 %tobool.not = icmp eq i64 %and, 04373 %cond = select i1 %tobool.not, i64 0, i64 %x4374 ret i64 %cond4375}4376 4377; Test that we don't crash on types larger than 64 bits.4378define i64 @single_bit3(i80 %x, i64 %y) {4379; RV32I-LABEL: single_bit3:4380; RV32I: # %bb.0: # %entry4381; RV32I-NEXT: lw a0, 8(a0)4382; RV32I-NEXT: slli a0, a0, 314383; RV32I-NEXT: srai a3, a0, 314384; RV32I-NEXT: and a0, a3, a14385; RV32I-NEXT: and a1, a3, a24386; RV32I-NEXT: ret4387;4388; RV64I-LABEL: single_bit3:4389; RV64I: # %bb.0: # %entry4390; RV64I-NEXT: slli a1, a1, 634391; RV64I-NEXT: srai a0, a1, 634392; RV64I-NEXT: and a0, a0, a24393; RV64I-NEXT: ret4394;4395; RV32XVENTANACONDOPS-LABEL: single_bit3:4396; RV32XVENTANACONDOPS: # %bb.0: # %entry4397; RV32XVENTANACONDOPS-NEXT: lw a0, 8(a0)4398; RV32XVENTANACONDOPS-NEXT: andi a3, a0, 14399; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a34400; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a2, a34401; RV32XVENTANACONDOPS-NEXT: ret4402;4403; RV64XVENTANACONDOPS-LABEL: single_bit3:4404; RV64XVENTANACONDOPS: # %bb.0: # %entry4405; RV64XVENTANACONDOPS-NEXT: andi a1, a1, 14406; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a14407; RV64XVENTANACONDOPS-NEXT: ret4408;4409; RV64XTHEADCONDMOV-LABEL: single_bit3:4410; RV64XTHEADCONDMOV: # %bb.0: # %entry4411; RV64XTHEADCONDMOV-NEXT: mv a0, a24412; RV64XTHEADCONDMOV-NEXT: andi a1, a1, 14413; RV64XTHEADCONDMOV-NEXT: th.mveqz a0, zero, a14414; RV64XTHEADCONDMOV-NEXT: ret4415;4416; RV32ZICOND-LABEL: single_bit3:4417; RV32ZICOND: # %bb.0: # %entry4418; RV32ZICOND-NEXT: lw a0, 8(a0)4419; RV32ZICOND-NEXT: andi a3, a0, 14420; RV32ZICOND-NEXT: czero.eqz a0, a1, a34421; RV32ZICOND-NEXT: czero.eqz a1, a2, a34422; RV32ZICOND-NEXT: ret4423;4424; RV64ZICOND-LABEL: single_bit3:4425; RV64ZICOND: # %bb.0: # %entry4426; RV64ZICOND-NEXT: andi a1, a1, 14427; RV64ZICOND-NEXT: czero.eqz a0, a2, a14428; RV64ZICOND-NEXT: ret4429entry:4430 %and = and i80 %x, 18446744073709551616 ; 1 << 644431 %tobool.not = icmp eq i80 %and, 04432 %cond = select i1 %tobool.not, i64 0, i64 %y4433 ret i64 %cond4434}4435