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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -O0 -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=NOPIC3; RUN: llc < %s -O0 -mtriple=riscv64 -mattr=+m -relocation-model=pic | FileCheck %s --check-prefix=PIC4 5define i64 @test(i32 noundef signext %c, i32 noundef signext %d) {6; NOPIC-LABEL: test:7; NOPIC: # %bb.0: # %entry8; NOPIC-NEXT: # kill: def $x11 killed $x109; NOPIC-NEXT: slli a0, a0, 3210; NOPIC-NEXT: srli a1, a0, 3211; NOPIC-NEXT: lui a0, %hi(.LCPI0_0)12; NOPIC-NEXT: ld a0, %lo(.LCPI0_0)(a0)13; NOPIC-NEXT: mul a0, a1, a014; NOPIC-NEXT: addi a0, a0, 12715; NOPIC-NEXT: mul a0, a1, a016; NOPIC-NEXT: lui a2, %hi(.LCPI0_1)17; NOPIC-NEXT: ld a2, %lo(.LCPI0_1)(a2)18; NOPIC-NEXT: mul a0, a0, a219; NOPIC-NEXT: add a0, a0, a120; NOPIC-NEXT: lui a1, 101592021; NOPIC-NEXT: addi a1, a1, 154122; NOPIC-NEXT: slli a1, a1, 1623; NOPIC-NEXT: addi a1, a1, 102724; NOPIC-NEXT: slli a1, a1, 2025; NOPIC-NEXT: add a0, a0, a126; NOPIC-NEXT: ret27;28; PIC-LABEL: test:29; PIC: # %bb.0: # %entry30; PIC-NEXT: # kill: def $x11 killed $x1031; PIC-NEXT: slli a0, a0, 3232; PIC-NEXT: srli a1, a0, 3233; PIC-NEXT: .Lpcrel_hi0:34; PIC-NEXT: auipc a0, %pcrel_hi(.LCPI0_0)35; PIC-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)36; PIC-NEXT: ld a0, 0(a0)37; PIC-NEXT: mul a0, a1, a038; PIC-NEXT: addi a0, a0, 12739; PIC-NEXT: mul a0, a1, a040; PIC-NEXT: .Lpcrel_hi1:41; PIC-NEXT: auipc a2, %pcrel_hi(.LCPI0_1)42; PIC-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi1)43; PIC-NEXT: ld a2, 0(a2)44; PIC-NEXT: mul a0, a0, a245; PIC-NEXT: add a0, a0, a146; PIC-NEXT: lui a1, 101592047; PIC-NEXT: addi a1, a1, 154148; PIC-NEXT: slli a1, a1, 1649; PIC-NEXT: addi a1, a1, 102750; PIC-NEXT: slli a1, a1, 2051; PIC-NEXT: add a0, a0, a152; PIC-NEXT: ret53entry:54 %or1 = or i64 -9191740941672644608, 409655 %or2 = or i64 -9191740941672644608, 819256 %or3 = or i64 -9191740941672644608, 1638457 %conv = zext i32 %c to i6458 %donv = zext i32 %d to i6459 %3 = mul i64 %or1, %conv60 %4 = mul i64 %or2, %donv61 %5 = mul i64 %or3, %conv62 %6 = add i64 %3, %463 %7 = add i64 %6, %564 %8 = or i64 %5, 12765 %9 = mul i64 %3, %866 %add = add i64 -9191740941672644608, %967 %add2 = add i64 %add, %conv68 ret i64 %add269}70