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1; REQUIRES: asserts2; RUN: llc -mtriple=riscv32 -debug-only=machine-scheduler < %s \3; RUN: -o /dev/null 2>&1 | FileCheck %s4; RUN: llc -mtriple=riscv64 -debug-only=machine-scheduler < %s \5; RUN: -o /dev/null 2>&1 | FileCheck %s6 7; This test exercises the areMemAccessesTriviallyDisjoint hook.8; Test that the two stores are disjoint memory accesses. If the corresponding9; store machine instructions don't depend on each other, the second store should10; not appear in the successors list of the first one and the first one should11; not appear on the predecessors list of the second one.12define i32 @test_disjoint(ptr %P, i32 %v) {13entry:14; CHECK: ********** MI Scheduling **********15; CHECK-LABEL: test_disjoint:%bb.016; CHECK:SU(2): SW %1:gpr, %0:gpr, 12 :: (store (s32) into %ir.arrayidx)17; CHECK-NOT: Successors:18; CHECK:SU(3): SW %1:gpr, %0:gpr, 8 :: (store (s32) into %ir.arrayidx1)19; CHECK: Predecessors:20; CHECK-NOT: SU(2): Ord Latency=0 Memory21 %arrayidx = getelementptr inbounds i32, ptr %P, i32 322 store i32 %v, ptr %arrayidx23 %arrayidx1 = getelementptr inbounds i32, ptr %P, i32 224 store i32 %v, ptr %arrayidx125 ret i32 %v26}27