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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefixes=RV32,RV32IM %s4; RUN: llc -mtriple=riscv32 -mattr=+m,+zba,+zbb \5; RUN: -verify-machineinstrs < %s \6; RUN: | FileCheck -check-prefixes=RV32,RV32IMZB %s7; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \8; RUN: | FileCheck -check-prefixes=RV64,RV64IM %s9; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb \10; RUN: -verify-machineinstrs < %s \11; RUN: | FileCheck -check-prefixes=RV64,RV64IMZB %s12 13; Test that there is a single shift after the mul and no addition.14define i32 @udiv_constant_no_add(i32 %a) nounwind {15; RV32-LABEL: udiv_constant_no_add:16; RV32: # %bb.0:17; RV32-NEXT: lui a1, 83886118; RV32-NEXT: addi a1, a1, -81919; RV32-NEXT: mulhu a0, a0, a120; RV32-NEXT: srli a0, a0, 221; RV32-NEXT: ret22;23; RV64-LABEL: udiv_constant_no_add:24; RV64: # %bb.0:25; RV64-NEXT: slli a0, a0, 3226; RV64-NEXT: lui a1, 83886127; RV64-NEXT: addi a1, a1, -81928; RV64-NEXT: slli a1, a1, 3229; RV64-NEXT: mulhu a0, a0, a130; RV64-NEXT: srli a0, a0, 3431; RV64-NEXT: ret32 %1 = udiv i32 %a, 533 ret i32 %134}35 36; This constant requires a sub, shrli, add sequence after the mul.37define i32 @udiv_constant_add(i32 %a) nounwind {38; RV32-LABEL: udiv_constant_add:39; RV32: # %bb.0:40; RV32-NEXT: lui a1, 14979741; RV32-NEXT: addi a1, a1, -175542; RV32-NEXT: mulhu a1, a0, a143; RV32-NEXT: sub a0, a0, a144; RV32-NEXT: srli a0, a0, 145; RV32-NEXT: add a0, a0, a146; RV32-NEXT: srli a0, a0, 247; RV32-NEXT: ret48;49; RV64IM-LABEL: udiv_constant_add:50; RV64IM: # %bb.0:51; RV64IM-NEXT: slli a1, a0, 3252; RV64IM-NEXT: lui a2, 14979753; RV64IM-NEXT: addi a2, a2, -175554; RV64IM-NEXT: slli a2, a2, 3255; RV64IM-NEXT: mulhu a1, a1, a256; RV64IM-NEXT: srli a1, a1, 3257; RV64IM-NEXT: sub a0, a0, a158; RV64IM-NEXT: srliw a0, a0, 159; RV64IM-NEXT: add a0, a0, a160; RV64IM-NEXT: srli a0, a0, 261; RV64IM-NEXT: ret62;63; RV64IMZB-LABEL: udiv_constant_add:64; RV64IMZB: # %bb.0:65; RV64IMZB-NEXT: zext.w a1, a066; RV64IMZB-NEXT: lui a2, 14979767; RV64IMZB-NEXT: addi a2, a2, -175568; RV64IMZB-NEXT: mul a1, a1, a269; RV64IMZB-NEXT: srli a1, a1, 3270; RV64IMZB-NEXT: sub a0, a0, a171; RV64IMZB-NEXT: srliw a0, a0, 172; RV64IMZB-NEXT: add a0, a0, a173; RV64IMZB-NEXT: srli a0, a0, 274; RV64IMZB-NEXT: ret75 %1 = udiv i32 %a, 776 ret i32 %177}78 79define i64 @udiv64_constant_no_add(i64 %a) nounwind {80; RV32-LABEL: udiv64_constant_no_add:81; RV32: # %bb.0:82; RV32-NEXT: add a2, a0, a183; RV32-NEXT: lui a3, 83886184; RV32-NEXT: sltu a4, a2, a085; RV32-NEXT: addi a5, a3, -81986; RV32-NEXT: addi a3, a3, -82087; RV32-NEXT: add a2, a2, a488; RV32-NEXT: mulhu a4, a2, a589; RV32-NEXT: srli a6, a4, 290; RV32-NEXT: andi a4, a4, -491; RV32-NEXT: add a4, a4, a692; RV32-NEXT: sub a2, a2, a493; RV32-NEXT: sub a4, a0, a294; RV32-NEXT: sltu a0, a0, a295; RV32-NEXT: mul a2, a4, a396; RV32-NEXT: mulhu a3, a4, a597; RV32-NEXT: sub a1, a1, a098; RV32-NEXT: add a2, a3, a299; RV32-NEXT: mul a1, a1, a5100; RV32-NEXT: add a1, a2, a1101; RV32-NEXT: mul a0, a4, a5102; RV32-NEXT: ret103;104; RV64-LABEL: udiv64_constant_no_add:105; RV64: # %bb.0:106; RV64-NEXT: lui a1, 838861107; RV64-NEXT: addi a1, a1, -819108; RV64-NEXT: slli a2, a1, 32109; RV64-NEXT: add a1, a1, a2110; RV64-NEXT: mulhu a0, a0, a1111; RV64-NEXT: srli a0, a0, 2112; RV64-NEXT: ret113 %1 = udiv i64 %a, 5114 ret i64 %1115}116 117define i64 @udiv64_constant_add(i64 %a) nounwind {118; RV32-LABEL: udiv64_constant_add:119; RV32: # %bb.0:120; RV32-NEXT: addi sp, sp, -16121; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill122; RV32-NEXT: li a2, 7123; RV32-NEXT: li a3, 0124; RV32-NEXT: call __udivdi3125; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload126; RV32-NEXT: addi sp, sp, 16127; RV32-NEXT: ret128;129; RV64-LABEL: udiv64_constant_add:130; RV64: # %bb.0:131; RV64-NEXT: lui a1, %hi(.LCPI3_0)132; RV64-NEXT: ld a1, %lo(.LCPI3_0)(a1)133; RV64-NEXT: mulhu a1, a0, a1134; RV64-NEXT: sub a0, a0, a1135; RV64-NEXT: srli a0, a0, 1136; RV64-NEXT: add a0, a0, a1137; RV64-NEXT: srli a0, a0, 2138; RV64-NEXT: ret139 %1 = udiv i64 %a, 7140 ret i64 %1141}142 143define i8 @udiv8_constant_no_add(i8 %a) nounwind {144; RV32-LABEL: udiv8_constant_no_add:145; RV32: # %bb.0:146; RV32-NEXT: zext.b a0, a0147; RV32-NEXT: li a1, 205148; RV32-NEXT: mul a0, a0, a1149; RV32-NEXT: srli a0, a0, 10150; RV32-NEXT: ret151;152; RV64-LABEL: udiv8_constant_no_add:153; RV64: # %bb.0:154; RV64-NEXT: zext.b a0, a0155; RV64-NEXT: li a1, 205156; RV64-NEXT: mul a0, a0, a1157; RV64-NEXT: srli a0, a0, 10158; RV64-NEXT: ret159 %1 = udiv i8 %a, 5160 ret i8 %1161}162 163define i8 @udiv8_constant_add(i8 %a) nounwind {164; RV32IM-LABEL: udiv8_constant_add:165; RV32IM: # %bb.0:166; RV32IM-NEXT: zext.b a1, a0167; RV32IM-NEXT: li a2, 37168; RV32IM-NEXT: mul a1, a1, a2169; RV32IM-NEXT: srli a1, a1, 8170; RV32IM-NEXT: sub a0, a0, a1171; RV32IM-NEXT: slli a0, a0, 24172; RV32IM-NEXT: srli a0, a0, 25173; RV32IM-NEXT: add a0, a0, a1174; RV32IM-NEXT: srli a0, a0, 2175; RV32IM-NEXT: ret176;177; RV32IMZB-LABEL: udiv8_constant_add:178; RV32IMZB: # %bb.0:179; RV32IMZB-NEXT: zext.b a1, a0180; RV32IMZB-NEXT: sh3add a2, a1, a1181; RV32IMZB-NEXT: sh2add a1, a2, a1182; RV32IMZB-NEXT: srli a1, a1, 8183; RV32IMZB-NEXT: sub a0, a0, a1184; RV32IMZB-NEXT: slli a0, a0, 24185; RV32IMZB-NEXT: srli a0, a0, 25186; RV32IMZB-NEXT: add a0, a0, a1187; RV32IMZB-NEXT: srli a0, a0, 2188; RV32IMZB-NEXT: ret189;190; RV64IM-LABEL: udiv8_constant_add:191; RV64IM: # %bb.0:192; RV64IM-NEXT: zext.b a1, a0193; RV64IM-NEXT: li a2, 37194; RV64IM-NEXT: mul a1, a1, a2195; RV64IM-NEXT: srli a1, a1, 8196; RV64IM-NEXT: sub a0, a0, a1197; RV64IM-NEXT: slli a0, a0, 56198; RV64IM-NEXT: srli a0, a0, 57199; RV64IM-NEXT: add a0, a0, a1200; RV64IM-NEXT: srli a0, a0, 2201; RV64IM-NEXT: ret202;203; RV64IMZB-LABEL: udiv8_constant_add:204; RV64IMZB: # %bb.0:205; RV64IMZB-NEXT: zext.b a1, a0206; RV64IMZB-NEXT: sh3add a2, a1, a1207; RV64IMZB-NEXT: sh2add a1, a2, a1208; RV64IMZB-NEXT: srli a1, a1, 8209; RV64IMZB-NEXT: sub a0, a0, a1210; RV64IMZB-NEXT: slli a0, a0, 56211; RV64IMZB-NEXT: srli a0, a0, 57212; RV64IMZB-NEXT: add a0, a0, a1213; RV64IMZB-NEXT: srli a0, a0, 2214; RV64IMZB-NEXT: ret215 %1 = udiv i8 %a, 7216 ret i8 %1217}218 219define i16 @udiv16_constant_no_add(i16 %a) nounwind {220; RV32-LABEL: udiv16_constant_no_add:221; RV32: # %bb.0:222; RV32-NEXT: slli a0, a0, 16223; RV32-NEXT: lui a1, 838864224; RV32-NEXT: mulhu a0, a0, a1225; RV32-NEXT: srli a0, a0, 18226; RV32-NEXT: ret227;228; RV64-LABEL: udiv16_constant_no_add:229; RV64: # %bb.0:230; RV64-NEXT: lui a1, 52429231; RV64-NEXT: slli a1, a1, 4232; RV64-NEXT: slli a0, a0, 48233; RV64-NEXT: mulhu a0, a0, a1234; RV64-NEXT: srli a0, a0, 18235; RV64-NEXT: ret236 %1 = udiv i16 %a, 5237 ret i16 %1238}239 240define i16 @udiv16_constant_add(i16 %a) nounwind {241; RV32-LABEL: udiv16_constant_add:242; RV32: # %bb.0:243; RV32-NEXT: slli a1, a0, 16244; RV32-NEXT: lui a2, 149808245; RV32-NEXT: mulhu a1, a1, a2246; RV32-NEXT: srli a1, a1, 16247; RV32-NEXT: sub a0, a0, a1248; RV32-NEXT: slli a0, a0, 16249; RV32-NEXT: srli a0, a0, 17250; RV32-NEXT: add a0, a0, a1251; RV32-NEXT: srli a0, a0, 2252; RV32-NEXT: ret253;254; RV64-LABEL: udiv16_constant_add:255; RV64: # %bb.0:256; RV64-NEXT: slli a1, a0, 48257; RV64-NEXT: lui a2, 149808258; RV64-NEXT: mulhu a1, a1, a2259; RV64-NEXT: srli a1, a1, 16260; RV64-NEXT: sub a0, a0, a1261; RV64-NEXT: slli a0, a0, 48262; RV64-NEXT: srli a0, a0, 49263; RV64-NEXT: add a0, a0, a1264; RV64-NEXT: srli a0, a0, 2265; RV64-NEXT: ret266 %1 = udiv i16 %a, 7267 ret i16 %1268}269 270; Test the simplest case a srli and an add after the mul. No srai.271define i32 @sdiv_constant_no_srai(i32 %a) nounwind {272; RV32-LABEL: sdiv_constant_no_srai:273; RV32: # %bb.0:274; RV32-NEXT: lui a1, 349525275; RV32-NEXT: addi a1, a1, 1366276; RV32-NEXT: mulh a0, a0, a1277; RV32-NEXT: srli a1, a0, 31278; RV32-NEXT: add a0, a0, a1279; RV32-NEXT: ret280;281; RV64-LABEL: sdiv_constant_no_srai:282; RV64: # %bb.0:283; RV64-NEXT: sext.w a0, a0284; RV64-NEXT: lui a1, 349525285; RV64-NEXT: addi a1, a1, 1366286; RV64-NEXT: mul a0, a0, a1287; RV64-NEXT: srli a1, a0, 63288; RV64-NEXT: srli a0, a0, 32289; RV64-NEXT: addw a0, a0, a1290; RV64-NEXT: ret291 %1 = sdiv i32 %a, 3292 ret i32 %1293}294 295; This constant requires an srai between the mul and the add.296define i32 @sdiv_constant_srai(i32 %a) nounwind {297; RV32-LABEL: sdiv_constant_srai:298; RV32: # %bb.0:299; RV32-NEXT: lui a1, 419430300; RV32-NEXT: addi a1, a1, 1639301; RV32-NEXT: mulh a0, a0, a1302; RV32-NEXT: srli a1, a0, 31303; RV32-NEXT: srai a0, a0, 1304; RV32-NEXT: add a0, a0, a1305; RV32-NEXT: ret306;307; RV64-LABEL: sdiv_constant_srai:308; RV64: # %bb.0:309; RV64-NEXT: sext.w a0, a0310; RV64-NEXT: lui a1, 419430311; RV64-NEXT: addi a1, a1, 1639312; RV64-NEXT: mul a0, a0, a1313; RV64-NEXT: srli a1, a0, 63314; RV64-NEXT: srai a0, a0, 33315; RV64-NEXT: add a0, a0, a1316; RV64-NEXT: ret317 %1 = sdiv i32 %a, 5318 ret i32 %1319}320 321; This constant requires an add and an srai after the mul.322define i32 @sdiv_constant_add_srai(i32 %a) nounwind {323; RV32-LABEL: sdiv_constant_add_srai:324; RV32: # %bb.0:325; RV32-NEXT: lui a1, 599186326; RV32-NEXT: addi a1, a1, 1171327; RV32-NEXT: mulh a1, a0, a1328; RV32-NEXT: add a0, a1, a0329; RV32-NEXT: srli a1, a0, 31330; RV32-NEXT: srai a0, a0, 2331; RV32-NEXT: add a0, a0, a1332; RV32-NEXT: ret333;334; RV64-LABEL: sdiv_constant_add_srai:335; RV64: # %bb.0:336; RV64-NEXT: sext.w a1, a0337; RV64-NEXT: lui a2, 599186338; RV64-NEXT: addi a2, a2, 1171339; RV64-NEXT: mul a1, a1, a2340; RV64-NEXT: srli a1, a1, 32341; RV64-NEXT: add a0, a1, a0342; RV64-NEXT: srliw a1, a0, 31343; RV64-NEXT: sraiw a0, a0, 2344; RV64-NEXT: add a0, a0, a1345; RV64-NEXT: ret346 %1 = sdiv i32 %a, 7347 ret i32 %1348}349 350; This constant requires a sub and an srai after the mul.351define i32 @sdiv_constant_sub_srai(i32 %a) nounwind {352; RV32-LABEL: sdiv_constant_sub_srai:353; RV32: # %bb.0:354; RV32-NEXT: lui a1, 449390355; RV32-NEXT: addi a1, a1, -1171356; RV32-NEXT: mulh a1, a0, a1357; RV32-NEXT: sub a1, a1, a0358; RV32-NEXT: srli a0, a1, 31359; RV32-NEXT: srai a1, a1, 2360; RV32-NEXT: add a0, a1, a0361; RV32-NEXT: ret362;363; RV64-LABEL: sdiv_constant_sub_srai:364; RV64: # %bb.0:365; RV64-NEXT: sext.w a1, a0366; RV64-NEXT: lui a2, 449390367; RV64-NEXT: addi a2, a2, -1171368; RV64-NEXT: mul a1, a1, a2369; RV64-NEXT: srli a1, a1, 32370; RV64-NEXT: sub a1, a1, a0371; RV64-NEXT: srliw a0, a1, 31372; RV64-NEXT: sraiw a1, a1, 2373; RV64-NEXT: add a0, a1, a0374; RV64-NEXT: ret375 %1 = sdiv i32 %a, -7376 ret i32 %1377}378 379define i64 @sdiv64_constant_no_srai(i64 %a) nounwind {380; RV32-LABEL: sdiv64_constant_no_srai:381; RV32: # %bb.0:382; RV32-NEXT: addi sp, sp, -16383; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill384; RV32-NEXT: li a2, 3385; RV32-NEXT: li a3, 0386; RV32-NEXT: call __divdi3387; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload388; RV32-NEXT: addi sp, sp, 16389; RV32-NEXT: ret390;391; RV64-LABEL: sdiv64_constant_no_srai:392; RV64: # %bb.0:393; RV64-NEXT: lui a1, %hi(.LCPI12_0)394; RV64-NEXT: ld a1, %lo(.LCPI12_0)(a1)395; RV64-NEXT: mulh a0, a0, a1396; RV64-NEXT: srli a1, a0, 63397; RV64-NEXT: add a0, a0, a1398; RV64-NEXT: ret399 %1 = sdiv i64 %a, 3400 ret i64 %1401}402 403define i64 @sdiv64_constant_srai(i64 %a) nounwind {404; RV32-LABEL: sdiv64_constant_srai:405; RV32: # %bb.0:406; RV32-NEXT: addi sp, sp, -16407; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill408; RV32-NEXT: li a2, 5409; RV32-NEXT: li a3, 0410; RV32-NEXT: call __divdi3411; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload412; RV32-NEXT: addi sp, sp, 16413; RV32-NEXT: ret414;415; RV64-LABEL: sdiv64_constant_srai:416; RV64: # %bb.0:417; RV64-NEXT: lui a1, %hi(.LCPI13_0)418; RV64-NEXT: ld a1, %lo(.LCPI13_0)(a1)419; RV64-NEXT: mulh a0, a0, a1420; RV64-NEXT: srli a1, a0, 63421; RV64-NEXT: srai a0, a0, 1422; RV64-NEXT: add a0, a0, a1423; RV64-NEXT: ret424 %1 = sdiv i64 %a, 5425 ret i64 %1426}427 428define i64 @sdiv64_constant_add_srai(i64 %a) nounwind {429; RV32-LABEL: sdiv64_constant_add_srai:430; RV32: # %bb.0:431; RV32-NEXT: addi sp, sp, -16432; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill433; RV32-NEXT: li a2, 15434; RV32-NEXT: li a3, 0435; RV32-NEXT: call __divdi3436; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload437; RV32-NEXT: addi sp, sp, 16438; RV32-NEXT: ret439;440; RV64-LABEL: sdiv64_constant_add_srai:441; RV64: # %bb.0:442; RV64-NEXT: lui a1, 559241443; RV64-NEXT: addi a1, a1, -1911444; RV64-NEXT: slli a2, a1, 32445; RV64-NEXT: add a1, a1, a2446; RV64-NEXT: mulh a1, a0, a1447; RV64-NEXT: add a0, a1, a0448; RV64-NEXT: srli a1, a0, 63449; RV64-NEXT: srai a0, a0, 3450; RV64-NEXT: add a0, a0, a1451; RV64-NEXT: ret452 %1 = sdiv i64 %a, 15453 ret i64 %1454}455 456define i64 @sdiv64_constant_sub_srai(i64 %a) nounwind {457; RV32-LABEL: sdiv64_constant_sub_srai:458; RV32: # %bb.0:459; RV32-NEXT: addi sp, sp, -16460; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill461; RV32-NEXT: li a2, -3462; RV32-NEXT: li a3, -1463; RV32-NEXT: call __divdi3464; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload465; RV32-NEXT: addi sp, sp, 16466; RV32-NEXT: ret467;468; RV64-LABEL: sdiv64_constant_sub_srai:469; RV64: # %bb.0:470; RV64-NEXT: lui a1, 349525471; RV64-NEXT: addi a1, a1, 1365472; RV64-NEXT: slli a2, a1, 32473; RV64-NEXT: add a1, a1, a2474; RV64-NEXT: mulh a1, a0, a1475; RV64-NEXT: sub a1, a1, a0476; RV64-NEXT: srli a0, a1, 63477; RV64-NEXT: srai a1, a1, 1478; RV64-NEXT: add a0, a1, a0479; RV64-NEXT: ret480 %1 = sdiv i64 %a, -3481 ret i64 %1482}483 484define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {485; RV32IM-LABEL: sdiv8_constant_no_srai:486; RV32IM: # %bb.0:487; RV32IM-NEXT: slli a0, a0, 24488; RV32IM-NEXT: li a1, 86489; RV32IM-NEXT: srai a0, a0, 24490; RV32IM-NEXT: mul a0, a0, a1491; RV32IM-NEXT: srli a1, a0, 31492; RV32IM-NEXT: srli a0, a0, 8493; RV32IM-NEXT: add a0, a0, a1494; RV32IM-NEXT: ret495;496; RV32IMZB-LABEL: sdiv8_constant_no_srai:497; RV32IMZB: # %bb.0:498; RV32IMZB-NEXT: sext.b a0, a0499; RV32IMZB-NEXT: li a1, 86500; RV32IMZB-NEXT: mul a0, a0, a1501; RV32IMZB-NEXT: srli a1, a0, 31502; RV32IMZB-NEXT: srli a0, a0, 8503; RV32IMZB-NEXT: add a0, a0, a1504; RV32IMZB-NEXT: ret505;506; RV64IM-LABEL: sdiv8_constant_no_srai:507; RV64IM: # %bb.0:508; RV64IM-NEXT: slli a0, a0, 56509; RV64IM-NEXT: li a1, 86510; RV64IM-NEXT: srai a0, a0, 56511; RV64IM-NEXT: mul a0, a0, a1512; RV64IM-NEXT: srli a1, a0, 63513; RV64IM-NEXT: srli a0, a0, 8514; RV64IM-NEXT: add a0, a0, a1515; RV64IM-NEXT: ret516;517; RV64IMZB-LABEL: sdiv8_constant_no_srai:518; RV64IMZB: # %bb.0:519; RV64IMZB-NEXT: sext.b a0, a0520; RV64IMZB-NEXT: li a1, 86521; RV64IMZB-NEXT: mul a0, a0, a1522; RV64IMZB-NEXT: srli a1, a0, 63523; RV64IMZB-NEXT: srli a0, a0, 8524; RV64IMZB-NEXT: add a0, a0, a1525; RV64IMZB-NEXT: ret526 %1 = sdiv i8 %a, 3527 ret i8 %1528}529 530define i8 @sdiv8_constant_srai(i8 %a) nounwind {531; RV32IM-LABEL: sdiv8_constant_srai:532; RV32IM: # %bb.0:533; RV32IM-NEXT: slli a0, a0, 24534; RV32IM-NEXT: li a1, 103535; RV32IM-NEXT: srai a0, a0, 24536; RV32IM-NEXT: mul a0, a0, a1537; RV32IM-NEXT: srli a1, a0, 31538; RV32IM-NEXT: srai a0, a0, 9539; RV32IM-NEXT: add a0, a0, a1540; RV32IM-NEXT: ret541;542; RV32IMZB-LABEL: sdiv8_constant_srai:543; RV32IMZB: # %bb.0:544; RV32IMZB-NEXT: sext.b a0, a0545; RV32IMZB-NEXT: li a1, 103546; RV32IMZB-NEXT: mul a0, a0, a1547; RV32IMZB-NEXT: srli a1, a0, 31548; RV32IMZB-NEXT: srai a0, a0, 9549; RV32IMZB-NEXT: add a0, a0, a1550; RV32IMZB-NEXT: ret551;552; RV64IM-LABEL: sdiv8_constant_srai:553; RV64IM: # %bb.0:554; RV64IM-NEXT: slli a0, a0, 56555; RV64IM-NEXT: li a1, 103556; RV64IM-NEXT: srai a0, a0, 56557; RV64IM-NEXT: mul a0, a0, a1558; RV64IM-NEXT: srli a1, a0, 63559; RV64IM-NEXT: srai a0, a0, 9560; RV64IM-NEXT: add a0, a0, a1561; RV64IM-NEXT: ret562;563; RV64IMZB-LABEL: sdiv8_constant_srai:564; RV64IMZB: # %bb.0:565; RV64IMZB-NEXT: sext.b a0, a0566; RV64IMZB-NEXT: li a1, 103567; RV64IMZB-NEXT: mul a0, a0, a1568; RV64IMZB-NEXT: srli a1, a0, 63569; RV64IMZB-NEXT: srai a0, a0, 9570; RV64IMZB-NEXT: add a0, a0, a1571; RV64IMZB-NEXT: ret572 %1 = sdiv i8 %a, 5573 ret i8 %1574}575 576define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {577; RV32IM-LABEL: sdiv8_constant_add_srai:578; RV32IM: # %bb.0:579; RV32IM-NEXT: slli a1, a0, 24580; RV32IM-NEXT: li a2, -109581; RV32IM-NEXT: srai a1, a1, 24582; RV32IM-NEXT: mul a1, a1, a2583; RV32IM-NEXT: srli a1, a1, 8584; RV32IM-NEXT: add a0, a1, a0585; RV32IM-NEXT: slli a0, a0, 24586; RV32IM-NEXT: srli a1, a0, 31587; RV32IM-NEXT: srai a0, a0, 26588; RV32IM-NEXT: add a0, a0, a1589; RV32IM-NEXT: ret590;591; RV32IMZB-LABEL: sdiv8_constant_add_srai:592; RV32IMZB: # %bb.0:593; RV32IMZB-NEXT: sext.b a1, a0594; RV32IMZB-NEXT: li a2, -109595; RV32IMZB-NEXT: mul a1, a1, a2596; RV32IMZB-NEXT: srli a1, a1, 8597; RV32IMZB-NEXT: add a0, a1, a0598; RV32IMZB-NEXT: slli a0, a0, 24599; RV32IMZB-NEXT: srli a1, a0, 31600; RV32IMZB-NEXT: srai a0, a0, 26601; RV32IMZB-NEXT: add a0, a0, a1602; RV32IMZB-NEXT: ret603;604; RV64IM-LABEL: sdiv8_constant_add_srai:605; RV64IM: # %bb.0:606; RV64IM-NEXT: slli a1, a0, 56607; RV64IM-NEXT: li a2, -109608; RV64IM-NEXT: srai a1, a1, 56609; RV64IM-NEXT: mul a1, a1, a2610; RV64IM-NEXT: srli a1, a1, 8611; RV64IM-NEXT: add a0, a1, a0612; RV64IM-NEXT: slli a0, a0, 56613; RV64IM-NEXT: srli a1, a0, 63614; RV64IM-NEXT: srai a0, a0, 58615; RV64IM-NEXT: add a0, a0, a1616; RV64IM-NEXT: ret617;618; RV64IMZB-LABEL: sdiv8_constant_add_srai:619; RV64IMZB: # %bb.0:620; RV64IMZB-NEXT: sext.b a1, a0621; RV64IMZB-NEXT: li a2, -109622; RV64IMZB-NEXT: mul a1, a1, a2623; RV64IMZB-NEXT: srli a1, a1, 8624; RV64IMZB-NEXT: add a0, a1, a0625; RV64IMZB-NEXT: slli a0, a0, 56626; RV64IMZB-NEXT: srli a1, a0, 63627; RV64IMZB-NEXT: srai a0, a0, 58628; RV64IMZB-NEXT: add a0, a0, a1629; RV64IMZB-NEXT: ret630 %1 = sdiv i8 %a, 7631 ret i8 %1632}633 634define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {635; RV32IM-LABEL: sdiv8_constant_sub_srai:636; RV32IM: # %bb.0:637; RV32IM-NEXT: slli a1, a0, 24638; RV32IM-NEXT: li a2, 109639; RV32IM-NEXT: srai a1, a1, 24640; RV32IM-NEXT: mul a1, a1, a2641; RV32IM-NEXT: srli a1, a1, 8642; RV32IM-NEXT: sub a1, a1, a0643; RV32IM-NEXT: slli a1, a1, 24644; RV32IM-NEXT: srli a0, a1, 31645; RV32IM-NEXT: srai a1, a1, 26646; RV32IM-NEXT: add a0, a1, a0647; RV32IM-NEXT: ret648;649; RV32IMZB-LABEL: sdiv8_constant_sub_srai:650; RV32IMZB: # %bb.0:651; RV32IMZB-NEXT: sext.b a1, a0652; RV32IMZB-NEXT: li a2, 109653; RV32IMZB-NEXT: mul a1, a1, a2654; RV32IMZB-NEXT: srli a1, a1, 8655; RV32IMZB-NEXT: sub a1, a1, a0656; RV32IMZB-NEXT: slli a1, a1, 24657; RV32IMZB-NEXT: srli a0, a1, 31658; RV32IMZB-NEXT: srai a1, a1, 26659; RV32IMZB-NEXT: add a0, a1, a0660; RV32IMZB-NEXT: ret661;662; RV64IM-LABEL: sdiv8_constant_sub_srai:663; RV64IM: # %bb.0:664; RV64IM-NEXT: slli a1, a0, 56665; RV64IM-NEXT: li a2, 109666; RV64IM-NEXT: srai a1, a1, 56667; RV64IM-NEXT: mul a1, a1, a2668; RV64IM-NEXT: srli a1, a1, 8669; RV64IM-NEXT: sub a1, a1, a0670; RV64IM-NEXT: slli a1, a1, 56671; RV64IM-NEXT: srli a0, a1, 63672; RV64IM-NEXT: srai a1, a1, 58673; RV64IM-NEXT: add a0, a1, a0674; RV64IM-NEXT: ret675;676; RV64IMZB-LABEL: sdiv8_constant_sub_srai:677; RV64IMZB: # %bb.0:678; RV64IMZB-NEXT: sext.b a1, a0679; RV64IMZB-NEXT: li a2, 109680; RV64IMZB-NEXT: mul a1, a1, a2681; RV64IMZB-NEXT: srli a1, a1, 8682; RV64IMZB-NEXT: sub a1, a1, a0683; RV64IMZB-NEXT: slli a1, a1, 56684; RV64IMZB-NEXT: srli a0, a1, 63685; RV64IMZB-NEXT: srai a1, a1, 58686; RV64IMZB-NEXT: add a0, a1, a0687; RV64IMZB-NEXT: ret688 %1 = sdiv i8 %a, -7689 ret i8 %1690}691 692define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {693; RV32IM-LABEL: sdiv16_constant_no_srai:694; RV32IM: # %bb.0:695; RV32IM-NEXT: slli a0, a0, 16696; RV32IM-NEXT: lui a1, 5697; RV32IM-NEXT: srai a0, a0, 16698; RV32IM-NEXT: addi a1, a1, 1366699; RV32IM-NEXT: mul a0, a0, a1700; RV32IM-NEXT: srli a1, a0, 31701; RV32IM-NEXT: srli a0, a0, 16702; RV32IM-NEXT: add a0, a0, a1703; RV32IM-NEXT: ret704;705; RV32IMZB-LABEL: sdiv16_constant_no_srai:706; RV32IMZB: # %bb.0:707; RV32IMZB-NEXT: sext.h a0, a0708; RV32IMZB-NEXT: lui a1, 5709; RV32IMZB-NEXT: addi a1, a1, 1366710; RV32IMZB-NEXT: mul a0, a0, a1711; RV32IMZB-NEXT: srli a1, a0, 31712; RV32IMZB-NEXT: srli a0, a0, 16713; RV32IMZB-NEXT: add a0, a0, a1714; RV32IMZB-NEXT: ret715;716; RV64IM-LABEL: sdiv16_constant_no_srai:717; RV64IM: # %bb.0:718; RV64IM-NEXT: slli a0, a0, 48719; RV64IM-NEXT: lui a1, 5720; RV64IM-NEXT: srai a0, a0, 48721; RV64IM-NEXT: addi a1, a1, 1366722; RV64IM-NEXT: mul a0, a0, a1723; RV64IM-NEXT: srli a1, a0, 63724; RV64IM-NEXT: srli a0, a0, 16725; RV64IM-NEXT: add a0, a0, a1726; RV64IM-NEXT: ret727;728; RV64IMZB-LABEL: sdiv16_constant_no_srai:729; RV64IMZB: # %bb.0:730; RV64IMZB-NEXT: sext.h a0, a0731; RV64IMZB-NEXT: lui a1, 5732; RV64IMZB-NEXT: addi a1, a1, 1366733; RV64IMZB-NEXT: mul a0, a0, a1734; RV64IMZB-NEXT: srli a1, a0, 63735; RV64IMZB-NEXT: srli a0, a0, 16736; RV64IMZB-NEXT: add a0, a0, a1737; RV64IMZB-NEXT: ret738 %1 = sdiv i16 %a, 3739 ret i16 %1740}741 742define i16 @sdiv16_constant_srai(i16 %a) nounwind {743; RV32IM-LABEL: sdiv16_constant_srai:744; RV32IM: # %bb.0:745; RV32IM-NEXT: slli a0, a0, 16746; RV32IM-NEXT: lui a1, 6747; RV32IM-NEXT: srai a0, a0, 16748; RV32IM-NEXT: addi a1, a1, 1639749; RV32IM-NEXT: mul a0, a0, a1750; RV32IM-NEXT: srli a1, a0, 31751; RV32IM-NEXT: srai a0, a0, 17752; RV32IM-NEXT: add a0, a0, a1753; RV32IM-NEXT: ret754;755; RV32IMZB-LABEL: sdiv16_constant_srai:756; RV32IMZB: # %bb.0:757; RV32IMZB-NEXT: sext.h a0, a0758; RV32IMZB-NEXT: lui a1, 6759; RV32IMZB-NEXT: addi a1, a1, 1639760; RV32IMZB-NEXT: mul a0, a0, a1761; RV32IMZB-NEXT: srli a1, a0, 31762; RV32IMZB-NEXT: srai a0, a0, 17763; RV32IMZB-NEXT: add a0, a0, a1764; RV32IMZB-NEXT: ret765;766; RV64IM-LABEL: sdiv16_constant_srai:767; RV64IM: # %bb.0:768; RV64IM-NEXT: slli a0, a0, 48769; RV64IM-NEXT: lui a1, 6770; RV64IM-NEXT: srai a0, a0, 48771; RV64IM-NEXT: addi a1, a1, 1639772; RV64IM-NEXT: mul a0, a0, a1773; RV64IM-NEXT: srli a1, a0, 63774; RV64IM-NEXT: srai a0, a0, 17775; RV64IM-NEXT: add a0, a0, a1776; RV64IM-NEXT: ret777;778; RV64IMZB-LABEL: sdiv16_constant_srai:779; RV64IMZB: # %bb.0:780; RV64IMZB-NEXT: sext.h a0, a0781; RV64IMZB-NEXT: lui a1, 6782; RV64IMZB-NEXT: addi a1, a1, 1639783; RV64IMZB-NEXT: mul a0, a0, a1784; RV64IMZB-NEXT: srli a1, a0, 63785; RV64IMZB-NEXT: srai a0, a0, 17786; RV64IMZB-NEXT: add a0, a0, a1787; RV64IMZB-NEXT: ret788 %1 = sdiv i16 %a, 5789 ret i16 %1790}791 792define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {793; RV32IM-LABEL: sdiv16_constant_add_srai:794; RV32IM: # %bb.0:795; RV32IM-NEXT: slli a1, a0, 16796; RV32IM-NEXT: lui a2, 1048569797; RV32IM-NEXT: srai a1, a1, 16798; RV32IM-NEXT: addi a2, a2, -1911799; RV32IM-NEXT: mul a1, a1, a2800; RV32IM-NEXT: srli a1, a1, 16801; RV32IM-NEXT: add a0, a1, a0802; RV32IM-NEXT: slli a0, a0, 16803; RV32IM-NEXT: srli a1, a0, 31804; RV32IM-NEXT: srai a0, a0, 19805; RV32IM-NEXT: add a0, a0, a1806; RV32IM-NEXT: ret807;808; RV32IMZB-LABEL: sdiv16_constant_add_srai:809; RV32IMZB: # %bb.0:810; RV32IMZB-NEXT: sext.h a1, a0811; RV32IMZB-NEXT: lui a2, 1048569812; RV32IMZB-NEXT: addi a2, a2, -1911813; RV32IMZB-NEXT: mul a1, a1, a2814; RV32IMZB-NEXT: srli a1, a1, 16815; RV32IMZB-NEXT: add a0, a1, a0816; RV32IMZB-NEXT: slli a0, a0, 16817; RV32IMZB-NEXT: srli a1, a0, 31818; RV32IMZB-NEXT: srai a0, a0, 19819; RV32IMZB-NEXT: add a0, a0, a1820; RV32IMZB-NEXT: ret821;822; RV64IM-LABEL: sdiv16_constant_add_srai:823; RV64IM: # %bb.0:824; RV64IM-NEXT: slli a1, a0, 48825; RV64IM-NEXT: lui a2, 1048569826; RV64IM-NEXT: srai a1, a1, 48827; RV64IM-NEXT: addi a2, a2, -1911828; RV64IM-NEXT: mul a1, a1, a2829; RV64IM-NEXT: srli a1, a1, 16830; RV64IM-NEXT: add a0, a1, a0831; RV64IM-NEXT: slli a0, a0, 48832; RV64IM-NEXT: srli a1, a0, 63833; RV64IM-NEXT: srai a0, a0, 51834; RV64IM-NEXT: add a0, a0, a1835; RV64IM-NEXT: ret836;837; RV64IMZB-LABEL: sdiv16_constant_add_srai:838; RV64IMZB: # %bb.0:839; RV64IMZB-NEXT: sext.h a1, a0840; RV64IMZB-NEXT: lui a2, 1048569841; RV64IMZB-NEXT: addi a2, a2, -1911842; RV64IMZB-NEXT: mul a1, a1, a2843; RV64IMZB-NEXT: srli a1, a1, 16844; RV64IMZB-NEXT: add a0, a1, a0845; RV64IMZB-NEXT: slli a0, a0, 48846; RV64IMZB-NEXT: srli a1, a0, 63847; RV64IMZB-NEXT: srai a0, a0, 51848; RV64IMZB-NEXT: add a0, a0, a1849; RV64IMZB-NEXT: ret850 %1 = sdiv i16 %a, 15851 ret i16 %1852}853 854define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {855; RV32IM-LABEL: sdiv16_constant_sub_srai:856; RV32IM: # %bb.0:857; RV32IM-NEXT: slli a1, a0, 16858; RV32IM-NEXT: lui a2, 7859; RV32IM-NEXT: srai a1, a1, 16860; RV32IM-NEXT: addi a2, a2, 1911861; RV32IM-NEXT: mul a1, a1, a2862; RV32IM-NEXT: srli a1, a1, 16863; RV32IM-NEXT: sub a1, a1, a0864; RV32IM-NEXT: slli a1, a1, 16865; RV32IM-NEXT: srli a0, a1, 31866; RV32IM-NEXT: srai a1, a1, 19867; RV32IM-NEXT: add a0, a1, a0868; RV32IM-NEXT: ret869;870; RV32IMZB-LABEL: sdiv16_constant_sub_srai:871; RV32IMZB: # %bb.0:872; RV32IMZB-NEXT: sext.h a1, a0873; RV32IMZB-NEXT: lui a2, 7874; RV32IMZB-NEXT: addi a2, a2, 1911875; RV32IMZB-NEXT: mul a1, a1, a2876; RV32IMZB-NEXT: srli a1, a1, 16877; RV32IMZB-NEXT: sub a1, a1, a0878; RV32IMZB-NEXT: slli a1, a1, 16879; RV32IMZB-NEXT: srli a0, a1, 31880; RV32IMZB-NEXT: srai a1, a1, 19881; RV32IMZB-NEXT: add a0, a1, a0882; RV32IMZB-NEXT: ret883;884; RV64IM-LABEL: sdiv16_constant_sub_srai:885; RV64IM: # %bb.0:886; RV64IM-NEXT: slli a1, a0, 48887; RV64IM-NEXT: lui a2, 7888; RV64IM-NEXT: srai a1, a1, 48889; RV64IM-NEXT: addi a2, a2, 1911890; RV64IM-NEXT: mul a1, a1, a2891; RV64IM-NEXT: srli a1, a1, 16892; RV64IM-NEXT: sub a1, a1, a0893; RV64IM-NEXT: slli a1, a1, 48894; RV64IM-NEXT: srli a0, a1, 63895; RV64IM-NEXT: srai a1, a1, 51896; RV64IM-NEXT: add a0, a1, a0897; RV64IM-NEXT: ret898;899; RV64IMZB-LABEL: sdiv16_constant_sub_srai:900; RV64IMZB: # %bb.0:901; RV64IMZB-NEXT: sext.h a1, a0902; RV64IMZB-NEXT: lui a2, 7903; RV64IMZB-NEXT: addi a2, a2, 1911904; RV64IMZB-NEXT: mul a1, a1, a2905; RV64IMZB-NEXT: srli a1, a1, 16906; RV64IMZB-NEXT: sub a1, a1, a0907; RV64IMZB-NEXT: slli a1, a1, 48908; RV64IMZB-NEXT: srli a0, a1, 63909; RV64IMZB-NEXT: srai a1, a1, 51910; RV64IMZB-NEXT: add a0, a1, a0911; RV64IMZB-NEXT: ret912 %1 = sdiv i16 %a, -15913 ret i16 %1914}915