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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV64I6 7define i32 @sdiv32_pow2_2(i32 %a) {8; RV32I-LABEL: sdiv32_pow2_2:9; RV32I: # %bb.0: # %entry10; RV32I-NEXT: srli a1, a0, 3111; RV32I-NEXT: add a0, a0, a112; RV32I-NEXT: srai a0, a0, 113; RV32I-NEXT: ret14;15; RV64I-LABEL: sdiv32_pow2_2:16; RV64I: # %bb.0: # %entry17; RV64I-NEXT: srliw a1, a0, 3118; RV64I-NEXT: add a0, a0, a119; RV64I-NEXT: sraiw a0, a0, 120; RV64I-NEXT: ret21entry:22 %div = sdiv i32 %a, 223 ret i32 %div24}25 26define i32 @sdiv32_pow2_negative_2(i32 %a) {27; RV32I-LABEL: sdiv32_pow2_negative_2:28; RV32I: # %bb.0: # %entry29; RV32I-NEXT: srli a1, a0, 3130; RV32I-NEXT: add a0, a0, a131; RV32I-NEXT: srai a0, a0, 132; RV32I-NEXT: neg a0, a033; RV32I-NEXT: ret34;35; RV64I-LABEL: sdiv32_pow2_negative_2:36; RV64I: # %bb.0: # %entry37; RV64I-NEXT: srliw a1, a0, 3138; RV64I-NEXT: add a0, a0, a139; RV64I-NEXT: sraiw a0, a0, 140; RV64I-NEXT: neg a0, a041; RV64I-NEXT: ret42entry:43 %div = sdiv i32 %a, -244 ret i32 %div45}46 47define i32 @sdiv32_pow2_2048(i32 %a) {48; RV32I-LABEL: sdiv32_pow2_2048:49; RV32I: # %bb.0: # %entry50; RV32I-NEXT: srai a1, a0, 3151; RV32I-NEXT: srli a1, a1, 2152; RV32I-NEXT: add a0, a0, a153; RV32I-NEXT: srai a0, a0, 1154; RV32I-NEXT: ret55;56; RV64I-LABEL: sdiv32_pow2_2048:57; RV64I: # %bb.0: # %entry58; RV64I-NEXT: sraiw a1, a0, 3159; RV64I-NEXT: srliw a1, a1, 2160; RV64I-NEXT: add a0, a0, a161; RV64I-NEXT: sraiw a0, a0, 1162; RV64I-NEXT: ret63entry:64 %div = sdiv i32 %a, 204865 ret i32 %div66}67 68define i32 @sdiv32_pow2_negative_2048(i32 %a) {69; RV32I-LABEL: sdiv32_pow2_negative_2048:70; RV32I: # %bb.0: # %entry71; RV32I-NEXT: srai a1, a0, 3172; RV32I-NEXT: srli a1, a1, 2173; RV32I-NEXT: add a0, a0, a174; RV32I-NEXT: srai a0, a0, 1175; RV32I-NEXT: neg a0, a076; RV32I-NEXT: ret77;78; RV64I-LABEL: sdiv32_pow2_negative_2048:79; RV64I: # %bb.0: # %entry80; RV64I-NEXT: sraiw a1, a0, 3181; RV64I-NEXT: srliw a1, a1, 2182; RV64I-NEXT: add a0, a0, a183; RV64I-NEXT: sraiw a0, a0, 1184; RV64I-NEXT: neg a0, a085; RV64I-NEXT: ret86entry:87 %div = sdiv i32 %a, -204888 ret i32 %div89}90 91define i32 @sdiv32_pow2_4096(i32 %a) {92; RV32I-LABEL: sdiv32_pow2_4096:93; RV32I: # %bb.0: # %entry94; RV32I-NEXT: srai a1, a0, 3195; RV32I-NEXT: srli a1, a1, 2096; RV32I-NEXT: add a0, a0, a197; RV32I-NEXT: srai a0, a0, 1298; RV32I-NEXT: ret99;100; RV64I-LABEL: sdiv32_pow2_4096:101; RV64I: # %bb.0: # %entry102; RV64I-NEXT: sraiw a1, a0, 31103; RV64I-NEXT: srliw a1, a1, 20104; RV64I-NEXT: add a0, a0, a1105; RV64I-NEXT: sraiw a0, a0, 12106; RV64I-NEXT: ret107entry:108 %div = sdiv i32 %a, 4096109 ret i32 %div110}111 112define i32 @sdiv32_pow2_negative_4096(i32 %a) {113; RV32I-LABEL: sdiv32_pow2_negative_4096:114; RV32I: # %bb.0: # %entry115; RV32I-NEXT: srai a1, a0, 31116; RV32I-NEXT: srli a1, a1, 20117; RV32I-NEXT: add a0, a0, a1118; RV32I-NEXT: srai a0, a0, 12119; RV32I-NEXT: neg a0, a0120; RV32I-NEXT: ret121;122; RV64I-LABEL: sdiv32_pow2_negative_4096:123; RV64I: # %bb.0: # %entry124; RV64I-NEXT: sraiw a1, a0, 31125; RV64I-NEXT: srliw a1, a1, 20126; RV64I-NEXT: add a0, a0, a1127; RV64I-NEXT: sraiw a0, a0, 12128; RV64I-NEXT: neg a0, a0129; RV64I-NEXT: ret130entry:131 %div = sdiv i32 %a, -4096132 ret i32 %div133}134 135define i32 @sdiv32_pow2_65536(i32 %a) {136; RV32I-LABEL: sdiv32_pow2_65536:137; RV32I: # %bb.0: # %entry138; RV32I-NEXT: srai a1, a0, 31139; RV32I-NEXT: srli a1, a1, 16140; RV32I-NEXT: add a0, a0, a1141; RV32I-NEXT: srai a0, a0, 16142; RV32I-NEXT: ret143;144; RV64I-LABEL: sdiv32_pow2_65536:145; RV64I: # %bb.0: # %entry146; RV64I-NEXT: sraiw a1, a0, 31147; RV64I-NEXT: srliw a1, a1, 16148; RV64I-NEXT: add a0, a0, a1149; RV64I-NEXT: sraiw a0, a0, 16150; RV64I-NEXT: ret151entry:152 %div = sdiv i32 %a, 65536153 ret i32 %div154}155 156define i32 @sdiv32_pow2_negative_65536(i32 %a) {157; RV32I-LABEL: sdiv32_pow2_negative_65536:158; RV32I: # %bb.0: # %entry159; RV32I-NEXT: srai a1, a0, 31160; RV32I-NEXT: srli a1, a1, 16161; RV32I-NEXT: add a0, a0, a1162; RV32I-NEXT: srai a0, a0, 16163; RV32I-NEXT: neg a0, a0164; RV32I-NEXT: ret165;166; RV64I-LABEL: sdiv32_pow2_negative_65536:167; RV64I: # %bb.0: # %entry168; RV64I-NEXT: sraiw a1, a0, 31169; RV64I-NEXT: srliw a1, a1, 16170; RV64I-NEXT: add a0, a0, a1171; RV64I-NEXT: sraiw a0, a0, 16172; RV64I-NEXT: neg a0, a0173; RV64I-NEXT: ret174entry:175 %div = sdiv i32 %a, -65536176 ret i32 %div177}178 179define i64 @sdiv64_pow2_2(i64 %a) {180; RV32I-LABEL: sdiv64_pow2_2:181; RV32I: # %bb.0: # %entry182; RV32I-NEXT: srli a2, a1, 31183; RV32I-NEXT: add a2, a0, a2184; RV32I-NEXT: srli a3, a2, 1185; RV32I-NEXT: sltu a0, a2, a0186; RV32I-NEXT: add a1, a1, a0187; RV32I-NEXT: slli a0, a1, 31188; RV32I-NEXT: or a0, a3, a0189; RV32I-NEXT: srai a1, a1, 1190; RV32I-NEXT: ret191;192; RV64I-LABEL: sdiv64_pow2_2:193; RV64I: # %bb.0: # %entry194; RV64I-NEXT: srli a1, a0, 63195; RV64I-NEXT: add a0, a0, a1196; RV64I-NEXT: srai a0, a0, 1197; RV64I-NEXT: ret198entry:199 %div = sdiv i64 %a, 2200 ret i64 %div201}202 203define i64 @sdiv64_pow2_negative_2(i64 %a) {204; RV32I-LABEL: sdiv64_pow2_negative_2:205; RV32I: # %bb.0: # %entry206; RV32I-NEXT: srli a2, a1, 31207; RV32I-NEXT: add a2, a0, a2208; RV32I-NEXT: srli a3, a2, 1209; RV32I-NEXT: sltu a0, a2, a0210; RV32I-NEXT: add a0, a1, a0211; RV32I-NEXT: slli a1, a0, 31212; RV32I-NEXT: srai a2, a0, 1213; RV32I-NEXT: or a1, a3, a1214; RV32I-NEXT: neg a0, a1215; RV32I-NEXT: snez a1, a1216; RV32I-NEXT: neg a2, a2217; RV32I-NEXT: sub a1, a2, a1218; RV32I-NEXT: ret219;220; RV64I-LABEL: sdiv64_pow2_negative_2:221; RV64I: # %bb.0: # %entry222; RV64I-NEXT: srli a1, a0, 63223; RV64I-NEXT: add a0, a0, a1224; RV64I-NEXT: srai a0, a0, 1225; RV64I-NEXT: neg a0, a0226; RV64I-NEXT: ret227entry:228 %div = sdiv i64 %a, -2229 ret i64 %div230}231 232define i64 @sdiv64_pow2_2048(i64 %a) {233; RV32I-LABEL: sdiv64_pow2_2048:234; RV32I: # %bb.0: # %entry235; RV32I-NEXT: srai a2, a1, 31236; RV32I-NEXT: srli a2, a2, 21237; RV32I-NEXT: add a2, a0, a2238; RV32I-NEXT: srli a3, a2, 11239; RV32I-NEXT: sltu a0, a2, a0240; RV32I-NEXT: add a1, a1, a0241; RV32I-NEXT: slli a0, a1, 21242; RV32I-NEXT: or a0, a3, a0243; RV32I-NEXT: srai a1, a1, 11244; RV32I-NEXT: ret245;246; RV64I-LABEL: sdiv64_pow2_2048:247; RV64I: # %bb.0: # %entry248; RV64I-NEXT: srai a1, a0, 63249; RV64I-NEXT: srli a1, a1, 53250; RV64I-NEXT: add a0, a0, a1251; RV64I-NEXT: srai a0, a0, 11252; RV64I-NEXT: ret253entry:254 %div = sdiv i64 %a, 2048255 ret i64 %div256}257 258define i64 @sdiv64_pow2_negative_2048(i64 %a) {259; RV32I-LABEL: sdiv64_pow2_negative_2048:260; RV32I: # %bb.0: # %entry261; RV32I-NEXT: srai a2, a1, 31262; RV32I-NEXT: srli a2, a2, 21263; RV32I-NEXT: add a2, a0, a2264; RV32I-NEXT: srli a3, a2, 11265; RV32I-NEXT: sltu a0, a2, a0266; RV32I-NEXT: add a0, a1, a0267; RV32I-NEXT: slli a1, a0, 21268; RV32I-NEXT: srai a2, a0, 11269; RV32I-NEXT: or a1, a3, a1270; RV32I-NEXT: neg a0, a1271; RV32I-NEXT: snez a1, a1272; RV32I-NEXT: neg a2, a2273; RV32I-NEXT: sub a1, a2, a1274; RV32I-NEXT: ret275;276; RV64I-LABEL: sdiv64_pow2_negative_2048:277; RV64I: # %bb.0: # %entry278; RV64I-NEXT: srai a1, a0, 63279; RV64I-NEXT: srli a1, a1, 53280; RV64I-NEXT: add a0, a0, a1281; RV64I-NEXT: srai a0, a0, 11282; RV64I-NEXT: neg a0, a0283; RV64I-NEXT: ret284entry:285 %div = sdiv i64 %a, -2048286 ret i64 %div287}288 289define i64 @sdiv64_pow2_4096(i64 %a) {290; RV32I-LABEL: sdiv64_pow2_4096:291; RV32I: # %bb.0: # %entry292; RV32I-NEXT: srai a2, a1, 31293; RV32I-NEXT: srli a2, a2, 20294; RV32I-NEXT: add a2, a0, a2295; RV32I-NEXT: srli a3, a2, 12296; RV32I-NEXT: sltu a0, a2, a0297; RV32I-NEXT: add a1, a1, a0298; RV32I-NEXT: slli a0, a1, 20299; RV32I-NEXT: or a0, a3, a0300; RV32I-NEXT: srai a1, a1, 12301; RV32I-NEXT: ret302;303; RV64I-LABEL: sdiv64_pow2_4096:304; RV64I: # %bb.0: # %entry305; RV64I-NEXT: srai a1, a0, 63306; RV64I-NEXT: srli a1, a1, 52307; RV64I-NEXT: add a0, a0, a1308; RV64I-NEXT: srai a0, a0, 12309; RV64I-NEXT: ret310entry:311 %div = sdiv i64 %a, 4096312 ret i64 %div313}314 315define i64 @sdiv64_pow2_negative_4096(i64 %a) {316; RV32I-LABEL: sdiv64_pow2_negative_4096:317; RV32I: # %bb.0: # %entry318; RV32I-NEXT: srai a2, a1, 31319; RV32I-NEXT: srli a2, a2, 20320; RV32I-NEXT: add a2, a0, a2321; RV32I-NEXT: srli a3, a2, 12322; RV32I-NEXT: sltu a0, a2, a0323; RV32I-NEXT: add a0, a1, a0324; RV32I-NEXT: slli a1, a0, 20325; RV32I-NEXT: srai a2, a0, 12326; RV32I-NEXT: or a1, a3, a1327; RV32I-NEXT: neg a0, a1328; RV32I-NEXT: snez a1, a1329; RV32I-NEXT: neg a2, a2330; RV32I-NEXT: sub a1, a2, a1331; RV32I-NEXT: ret332;333; RV64I-LABEL: sdiv64_pow2_negative_4096:334; RV64I: # %bb.0: # %entry335; RV64I-NEXT: srai a1, a0, 63336; RV64I-NEXT: srli a1, a1, 52337; RV64I-NEXT: add a0, a0, a1338; RV64I-NEXT: srai a0, a0, 12339; RV64I-NEXT: neg a0, a0340; RV64I-NEXT: ret341entry:342 %div = sdiv i64 %a, -4096343 ret i64 %div344}345 346define i64 @sdiv64_pow2_65536(i64 %a) {347; RV32I-LABEL: sdiv64_pow2_65536:348; RV32I: # %bb.0: # %entry349; RV32I-NEXT: srai a2, a1, 31350; RV32I-NEXT: srli a2, a2, 16351; RV32I-NEXT: add a2, a0, a2352; RV32I-NEXT: srli a3, a2, 16353; RV32I-NEXT: sltu a0, a2, a0354; RV32I-NEXT: add a1, a1, a0355; RV32I-NEXT: slli a0, a1, 16356; RV32I-NEXT: or a0, a3, a0357; RV32I-NEXT: srai a1, a1, 16358; RV32I-NEXT: ret359;360; RV64I-LABEL: sdiv64_pow2_65536:361; RV64I: # %bb.0: # %entry362; RV64I-NEXT: srai a1, a0, 63363; RV64I-NEXT: srli a1, a1, 48364; RV64I-NEXT: add a0, a0, a1365; RV64I-NEXT: srai a0, a0, 16366; RV64I-NEXT: ret367entry:368 %div = sdiv i64 %a, 65536369 ret i64 %div370}371 372define i64 @sdiv64_pow2_negative_65536(i64 %a) {373; RV32I-LABEL: sdiv64_pow2_negative_65536:374; RV32I: # %bb.0: # %entry375; RV32I-NEXT: srai a2, a1, 31376; RV32I-NEXT: srli a2, a2, 16377; RV32I-NEXT: add a2, a0, a2378; RV32I-NEXT: srli a3, a2, 16379; RV32I-NEXT: sltu a0, a2, a0380; RV32I-NEXT: add a0, a1, a0381; RV32I-NEXT: slli a1, a0, 16382; RV32I-NEXT: srai a2, a0, 16383; RV32I-NEXT: or a1, a3, a1384; RV32I-NEXT: neg a0, a1385; RV32I-NEXT: snez a1, a1386; RV32I-NEXT: neg a2, a2387; RV32I-NEXT: sub a1, a2, a1388; RV32I-NEXT: ret389;390; RV64I-LABEL: sdiv64_pow2_negative_65536:391; RV64I: # %bb.0: # %entry392; RV64I-NEXT: srai a1, a0, 63393; RV64I-NEXT: srli a1, a1, 48394; RV64I-NEXT: add a0, a0, a1395; RV64I-NEXT: srai a0, a0, 16396; RV64I-NEXT: neg a0, a0397; RV64I-NEXT: ret398entry:399 %div = sdiv i64 %a, -65536400 ret i64 %div401}402 403define i64 @sdiv64_pow2_8589934592(i64 %a) {404; RV32I-LABEL: sdiv64_pow2_8589934592:405; RV32I: # %bb.0: # %entry406; RV32I-NEXT: srli a2, a1, 31407; RV32I-NEXT: add a2, a1, a2408; RV32I-NEXT: srai a1, a1, 31409; RV32I-NEXT: add a1, a0, a1410; RV32I-NEXT: sltu a0, a1, a0411; RV32I-NEXT: add a1, a2, a0412; RV32I-NEXT: srai a0, a1, 1413; RV32I-NEXT: srai a1, a1, 31414; RV32I-NEXT: ret415;416; RV64I-LABEL: sdiv64_pow2_8589934592:417; RV64I: # %bb.0: # %entry418; RV64I-NEXT: srai a1, a0, 63419; RV64I-NEXT: srli a1, a1, 31420; RV64I-NEXT: add a0, a0, a1421; RV64I-NEXT: srai a0, a0, 33422; RV64I-NEXT: ret423entry:424 %div = sdiv i64 %a, 8589934592 ; 2^33425 ret i64 %div426}427 428define i64 @sdiv64_pow2_negative_8589934592(i64 %a) {429; RV32I-LABEL: sdiv64_pow2_negative_8589934592:430; RV32I: # %bb.0: # %entry431; RV32I-NEXT: srli a2, a1, 31432; RV32I-NEXT: add a2, a1, a2433; RV32I-NEXT: srai a1, a1, 31434; RV32I-NEXT: add a1, a0, a1435; RV32I-NEXT: sltu a0, a1, a0436; RV32I-NEXT: add a0, a2, a0437; RV32I-NEXT: srai a1, a0, 31438; RV32I-NEXT: srai a0, a0, 1439; RV32I-NEXT: snez a2, a0440; RV32I-NEXT: neg a1, a1441; RV32I-NEXT: sub a1, a1, a2442; RV32I-NEXT: neg a0, a0443; RV32I-NEXT: ret444;445; RV64I-LABEL: sdiv64_pow2_negative_8589934592:446; RV64I: # %bb.0: # %entry447; RV64I-NEXT: srai a1, a0, 63448; RV64I-NEXT: srli a1, a1, 31449; RV64I-NEXT: add a0, a0, a1450; RV64I-NEXT: srai a0, a0, 33451; RV64I-NEXT: neg a0, a0452; RV64I-NEXT: ret453entry:454 %div = sdiv i64 %a, -8589934592 ; -2^33455 ret i64 %div456}457