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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefixes=RV32IM %s4; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefixes=RV64IM %s6 7define i32 @testsize1(i32 %x) minsize nounwind {8; RV32IM-LABEL: testsize1:9; RV32IM: # %bb.0: # %entry10; RV32IM-NEXT: li a1, 3211; RV32IM-NEXT: div a0, a0, a112; RV32IM-NEXT: ret13;14; RV64IM-LABEL: testsize1:15; RV64IM: # %bb.0: # %entry16; RV64IM-NEXT: li a1, 3217; RV64IM-NEXT: divw a0, a0, a118; RV64IM-NEXT: ret19entry:20 %div = sdiv i32 %x, 3221 ret i32 %div22}23 24define i32 @testsize2(i32 %x) minsize nounwind {25; RV32IM-LABEL: testsize2:26; RV32IM: # %bb.0: # %entry27; RV32IM-NEXT: li a1, 3328; RV32IM-NEXT: div a0, a0, a129; RV32IM-NEXT: ret30;31; RV64IM-LABEL: testsize2:32; RV64IM: # %bb.0: # %entry33; RV64IM-NEXT: li a1, 3334; RV64IM-NEXT: divw a0, a0, a135; RV64IM-NEXT: ret36entry:37 %div = sdiv i32 %x, 3338 ret i32 %div39}40 41define i32 @testsize3(i32 %x) minsize nounwind {42; RV32IM-LABEL: testsize3:43; RV32IM: # %bb.0: # %entry44; RV32IM-NEXT: srli a0, a0, 545; RV32IM-NEXT: ret46;47; RV64IM-LABEL: testsize3:48; RV64IM: # %bb.0: # %entry49; RV64IM-NEXT: srliw a0, a0, 550; RV64IM-NEXT: ret51entry:52 %div = udiv i32 %x, 3253 ret i32 %div54}55 56define i32 @testsize4(i32 %x) minsize nounwind {57; RV32IM-LABEL: testsize4:58; RV32IM: # %bb.0:59; RV32IM-NEXT: li a1, 3360; RV32IM-NEXT: divu a0, a0, a161; RV32IM-NEXT: ret62;63; RV64IM-LABEL: testsize4:64; RV64IM: # %bb.0:65; RV64IM-NEXT: li a1, 3366; RV64IM-NEXT: divuw a0, a0, a167; RV64IM-NEXT: ret68 %div = udiv i32 %x, 3369 ret i32 %div70}71 72define i128 @i128_sdiv(i128 %arg0) minsize nounwind {73; RV32IM-LABEL: i128_sdiv:74; RV32IM: # %bb.0:75; RV32IM-NEXT: lw a2, 12(a1)76; RV32IM-NEXT: lw a3, 8(a1)77; RV32IM-NEXT: lw a4, 0(a1)78; RV32IM-NEXT: lw a1, 4(a1)79; RV32IM-NEXT: srai a5, a2, 3180; RV32IM-NEXT: srli a5, a5, 3081; RV32IM-NEXT: add a5, a4, a582; RV32IM-NEXT: sltu a4, a5, a483; RV32IM-NEXT: srli a5, a5, 284; RV32IM-NEXT: add a6, a1, a485; RV32IM-NEXT: sltu a1, a6, a186; RV32IM-NEXT: and a1, a4, a187; RV32IM-NEXT: srli a4, a6, 288; RV32IM-NEXT: slli a6, a6, 3089; RV32IM-NEXT: or a5, a5, a690; RV32IM-NEXT: add a1, a3, a191; RV32IM-NEXT: srli a6, a1, 292; RV32IM-NEXT: sltu a3, a1, a393; RV32IM-NEXT: slli a1, a1, 3094; RV32IM-NEXT: add a2, a2, a395; RV32IM-NEXT: or a1, a4, a196; RV32IM-NEXT: slli a3, a2, 3097; RV32IM-NEXT: srai a2, a2, 298; RV32IM-NEXT: or a3, a6, a399; RV32IM-NEXT: sw a5, 0(a0)100; RV32IM-NEXT: sw a1, 4(a0)101; RV32IM-NEXT: sw a3, 8(a0)102; RV32IM-NEXT: sw a2, 12(a0)103; RV32IM-NEXT: ret104;105; RV64IM-LABEL: i128_sdiv:106; RV64IM: # %bb.0:107; RV64IM-NEXT: addi sp, sp, -16108; RV64IM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill109; RV64IM-NEXT: li a2, 4110; RV64IM-NEXT: li a3, 0111; RV64IM-NEXT: call __divti3112; RV64IM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload113; RV64IM-NEXT: addi sp, sp, 16114; RV64IM-NEXT: ret115 %div = sdiv i128 %arg0, 4116 ret i128 %div117}118 119define i256 @i256_sdiv(i256 %arg0) minsize nounwind {120; RV32IM-LABEL: i256_sdiv:121; RV32IM: # %bb.0:122; RV32IM-NEXT: lw a5, 16(a1)123; RV32IM-NEXT: lw a4, 20(a1)124; RV32IM-NEXT: lw a2, 24(a1)125; RV32IM-NEXT: lw a3, 28(a1)126; RV32IM-NEXT: lw a6, 0(a1)127; RV32IM-NEXT: lw a7, 4(a1)128; RV32IM-NEXT: lw t0, 8(a1)129; RV32IM-NEXT: lw t1, 12(a1)130; RV32IM-NEXT: srai a1, a3, 31131; RV32IM-NEXT: srli a1, a1, 30132; RV32IM-NEXT: add a1, a6, a1133; RV32IM-NEXT: sltu t2, a1, a6134; RV32IM-NEXT: add a6, a7, t2135; RV32IM-NEXT: sltu a7, a6, a7136; RV32IM-NEXT: and t2, t2, a7137; RV32IM-NEXT: add a7, t0, t2138; RV32IM-NEXT: sltu t3, a7, t0139; RV32IM-NEXT: add t0, t1, t3140; RV32IM-NEXT: beqz t2, .LBB5_2141; RV32IM-NEXT: # %bb.1:142; RV32IM-NEXT: sltu t1, t0, t1143; RV32IM-NEXT: and t2, t3, t1144; RV32IM-NEXT: .LBB5_2:145; RV32IM-NEXT: add t2, a5, t2146; RV32IM-NEXT: srli t1, t0, 2147; RV32IM-NEXT: srli t3, a7, 2148; RV32IM-NEXT: slli t0, t0, 30149; RV32IM-NEXT: slli a7, a7, 30150; RV32IM-NEXT: or t0, t3, t0151; RV32IM-NEXT: srli t3, a6, 2152; RV32IM-NEXT: srli a1, a1, 2153; RV32IM-NEXT: slli a6, a6, 30154; RV32IM-NEXT: sltu a5, t2, a5155; RV32IM-NEXT: or a7, t3, a7156; RV32IM-NEXT: srli t3, t2, 2157; RV32IM-NEXT: slli t2, t2, 30158; RV32IM-NEXT: or a1, a1, a6159; RV32IM-NEXT: add a6, a4, a5160; RV32IM-NEXT: or t1, t1, t2161; RV32IM-NEXT: sltu a4, a6, a4162; RV32IM-NEXT: srli t2, a6, 2163; RV32IM-NEXT: slli a6, a6, 30164; RV32IM-NEXT: sw a1, 0(a0)165; RV32IM-NEXT: sw a7, 4(a0)166; RV32IM-NEXT: sw t0, 8(a0)167; RV32IM-NEXT: sw t1, 12(a0)168; RV32IM-NEXT: and a4, a5, a4169; RV32IM-NEXT: or a1, t3, a6170; RV32IM-NEXT: add a4, a2, a4171; RV32IM-NEXT: srli a5, a4, 2172; RV32IM-NEXT: sltu a2, a4, a2173; RV32IM-NEXT: slli a4, a4, 30174; RV32IM-NEXT: add a2, a3, a2175; RV32IM-NEXT: or a3, t2, a4176; RV32IM-NEXT: slli a4, a2, 30177; RV32IM-NEXT: srai a2, a2, 2178; RV32IM-NEXT: or a4, a5, a4179; RV32IM-NEXT: sw a1, 16(a0)180; RV32IM-NEXT: sw a3, 20(a0)181; RV32IM-NEXT: sw a4, 24(a0)182; RV32IM-NEXT: sw a2, 28(a0)183; RV32IM-NEXT: ret184;185; RV64IM-LABEL: i256_sdiv:186; RV64IM: # %bb.0:187; RV64IM-NEXT: ld a2, 24(a1)188; RV64IM-NEXT: ld a3, 16(a1)189; RV64IM-NEXT: ld a4, 0(a1)190; RV64IM-NEXT: ld a1, 8(a1)191; RV64IM-NEXT: srai a5, a2, 63192; RV64IM-NEXT: srli a5, a5, 62193; RV64IM-NEXT: add a5, a4, a5194; RV64IM-NEXT: sltu a4, a5, a4195; RV64IM-NEXT: srli a5, a5, 2196; RV64IM-NEXT: add a6, a1, a4197; RV64IM-NEXT: sltu a1, a6, a1198; RV64IM-NEXT: and a1, a4, a1199; RV64IM-NEXT: srli a4, a6, 2200; RV64IM-NEXT: slli a6, a6, 62201; RV64IM-NEXT: or a5, a5, a6202; RV64IM-NEXT: add a1, a3, a1203; RV64IM-NEXT: srli a6, a1, 2204; RV64IM-NEXT: sltu a3, a1, a3205; RV64IM-NEXT: slli a1, a1, 62206; RV64IM-NEXT: add a2, a2, a3207; RV64IM-NEXT: or a1, a4, a1208; RV64IM-NEXT: slli a3, a2, 62209; RV64IM-NEXT: srai a2, a2, 2210; RV64IM-NEXT: or a3, a6, a3211; RV64IM-NEXT: sd a5, 0(a0)212; RV64IM-NEXT: sd a1, 8(a0)213; RV64IM-NEXT: sd a3, 16(a0)214; RV64IM-NEXT: sd a2, 24(a0)215; RV64IM-NEXT: ret216 %div = sdiv i256 %arg0, 4217 ret i256 %div218}219