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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \3; RUN: -disable-strictnode-mutation -target-abi=ilp32d \4; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s5; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \6; RUN: -disable-strictnode-mutation -target-abi=lp64d \7; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s8; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \9; RUN: -disable-strictnode-mutation -target-abi=ilp32 \10; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s11; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \12; RUN: -disable-strictnode-mutation -target-abi=lp64 \13; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s14; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \15; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s16; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \17; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s18 19; NOTE: The rounding mode metadata does not effect which instruction is20; selected. Dynamic rounding mode is always used for operations that21; support rounding mode.22 23define float @fcvt_s_d(double %a) nounwind strictfp {24; CHECKIFD-LABEL: fcvt_s_d:25; CHECKIFD: # %bb.0:26; CHECKIFD-NEXT: fcvt.s.d fa0, fa027; CHECKIFD-NEXT: ret28;29; RV32IZFINXZDINX-LABEL: fcvt_s_d:30; RV32IZFINXZDINX: # %bb.0:31; RV32IZFINXZDINX-NEXT: fcvt.s.d a0, a032; RV32IZFINXZDINX-NEXT: ret33;34; RV64IZFINXZDINX-LABEL: fcvt_s_d:35; RV64IZFINXZDINX: # %bb.0:36; RV64IZFINXZDINX-NEXT: fcvt.s.d a0, a037; RV64IZFINXZDINX-NEXT: ret38;39; RV32I-LABEL: fcvt_s_d:40; RV32I: # %bb.0:41; RV32I-NEXT: addi sp, sp, -1642; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill43; RV32I-NEXT: call __truncdfsf244; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload45; RV32I-NEXT: addi sp, sp, 1646; RV32I-NEXT: ret47;48; RV64I-LABEL: fcvt_s_d:49; RV64I: # %bb.0:50; RV64I-NEXT: addi sp, sp, -1651; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill52; RV64I-NEXT: call __truncdfsf253; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload54; RV64I-NEXT: addi sp, sp, 1655; RV64I-NEXT: ret56 %1 = call float @llvm.experimental.constrained.fptrunc.f32.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict")57 ret float %158}59 60define double @fcvt_d_s(float %a) nounwind strictfp {61; CHECKIFD-LABEL: fcvt_d_s:62; CHECKIFD: # %bb.0:63; CHECKIFD-NEXT: fcvt.d.s fa0, fa064; CHECKIFD-NEXT: ret65;66; RV32IZFINXZDINX-LABEL: fcvt_d_s:67; RV32IZFINXZDINX: # %bb.0:68; RV32IZFINXZDINX-NEXT: fcvt.d.s a0, a069; RV32IZFINXZDINX-NEXT: ret70;71; RV64IZFINXZDINX-LABEL: fcvt_d_s:72; RV64IZFINXZDINX: # %bb.0:73; RV64IZFINXZDINX-NEXT: fcvt.d.s a0, a074; RV64IZFINXZDINX-NEXT: ret75;76; RV32I-LABEL: fcvt_d_s:77; RV32I: # %bb.0:78; RV32I-NEXT: addi sp, sp, -1679; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill80; RV32I-NEXT: call __extendsfdf281; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload82; RV32I-NEXT: addi sp, sp, 1683; RV32I-NEXT: ret84;85; RV64I-LABEL: fcvt_d_s:86; RV64I: # %bb.0:87; RV64I-NEXT: addi sp, sp, -1688; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill89; RV64I-NEXT: call __extendsfdf290; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload91; RV64I-NEXT: addi sp, sp, 1692; RV64I-NEXT: ret93 %1 = call double @llvm.experimental.constrained.fpext.f64.f32(float %a, metadata !"fpexcept.strict")94 ret double %195}96 97define i32 @fcvt_w_d(double %a) nounwind strictfp {98; CHECKIFD-LABEL: fcvt_w_d:99; CHECKIFD: # %bb.0:100; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz101; CHECKIFD-NEXT: ret102;103; RV32IZFINXZDINX-LABEL: fcvt_w_d:104; RV32IZFINXZDINX: # %bb.0:105; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz106; RV32IZFINXZDINX-NEXT: ret107;108; RV64IZFINXZDINX-LABEL: fcvt_w_d:109; RV64IZFINXZDINX: # %bb.0:110; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz111; RV64IZFINXZDINX-NEXT: ret112;113; RV32I-LABEL: fcvt_w_d:114; RV32I: # %bb.0:115; RV32I-NEXT: addi sp, sp, -16116; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill117; RV32I-NEXT: call __fixdfsi118; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload119; RV32I-NEXT: addi sp, sp, 16120; RV32I-NEXT: ret121;122; RV64I-LABEL: fcvt_w_d:123; RV64I: # %bb.0:124; RV64I-NEXT: addi sp, sp, -16125; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill126; RV64I-NEXT: call __fixdfsi127; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload128; RV64I-NEXT: addi sp, sp, 16129; RV64I-NEXT: ret130 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")131 ret i32 %1132}133 134; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case135; because fptosi will produce poison if the result doesn't fit into an i32.136define i32 @fcvt_wu_d(double %a) nounwind strictfp {137; CHECKIFD-LABEL: fcvt_wu_d:138; CHECKIFD: # %bb.0:139; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz140; CHECKIFD-NEXT: ret141;142; RV32IZFINXZDINX-LABEL: fcvt_wu_d:143; RV32IZFINXZDINX: # %bb.0:144; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz145; RV32IZFINXZDINX-NEXT: ret146;147; RV64IZFINXZDINX-LABEL: fcvt_wu_d:148; RV64IZFINXZDINX: # %bb.0:149; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz150; RV64IZFINXZDINX-NEXT: ret151;152; RV32I-LABEL: fcvt_wu_d:153; RV32I: # %bb.0:154; RV32I-NEXT: addi sp, sp, -16155; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill156; RV32I-NEXT: call __fixunsdfsi157; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload158; RV32I-NEXT: addi sp, sp, 16159; RV32I-NEXT: ret160;161; RV64I-LABEL: fcvt_wu_d:162; RV64I: # %bb.0:163; RV64I-NEXT: addi sp, sp, -16164; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill165; RV64I-NEXT: call __fixunsdfsi166; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload167; RV64I-NEXT: addi sp, sp, 16168; RV64I-NEXT: ret169 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")170 ret i32 %1171}172 173; Test where the fptoui has multiple uses, one of which causes a sext to be174; inserted on RV64.175define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind strictfp {176; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:177; CHECKIFD: # %bb.0:178; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz179; CHECKIFD-NEXT: seqz a1, a0180; CHECKIFD-NEXT: add a0, a0, a1181; CHECKIFD-NEXT: ret182;183; RV32IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:184; RV32IZFINXZDINX: # %bb.0:185; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz186; RV32IZFINXZDINX-NEXT: seqz a1, a0187; RV32IZFINXZDINX-NEXT: add a0, a0, a1188; RV32IZFINXZDINX-NEXT: ret189;190; RV64IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:191; RV64IZFINXZDINX: # %bb.0:192; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz193; RV64IZFINXZDINX-NEXT: seqz a1, a0194; RV64IZFINXZDINX-NEXT: add a0, a0, a1195; RV64IZFINXZDINX-NEXT: ret196;197; RV32I-LABEL: fcvt_wu_d_multiple_use:198; RV32I: # %bb.0:199; RV32I-NEXT: addi sp, sp, -16200; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill201; RV32I-NEXT: call __fixunsdfsi202; RV32I-NEXT: seqz a1, a0203; RV32I-NEXT: add a0, a0, a1204; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload205; RV32I-NEXT: addi sp, sp, 16206; RV32I-NEXT: ret207;208; RV64I-LABEL: fcvt_wu_d_multiple_use:209; RV64I: # %bb.0:210; RV64I-NEXT: addi sp, sp, -16211; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill212; RV64I-NEXT: call __fixunsdfsi213; RV64I-NEXT: seqz a1, a0214; RV64I-NEXT: add a0, a0, a1215; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload216; RV64I-NEXT: addi sp, sp, 16217; RV64I-NEXT: ret218 %a = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict")219 %b = icmp eq i32 %a, 0220 %c = select i1 %b, i32 1, i32 %a221 ret i32 %c222}223 224define double @fcvt_d_w(i32 %a) nounwind strictfp {225; CHECKIFD-LABEL: fcvt_d_w:226; CHECKIFD: # %bb.0:227; CHECKIFD-NEXT: fcvt.d.w fa0, a0228; CHECKIFD-NEXT: ret229;230; RV32IZFINXZDINX-LABEL: fcvt_d_w:231; RV32IZFINXZDINX: # %bb.0:232; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0233; RV32IZFINXZDINX-NEXT: ret234;235; RV64IZFINXZDINX-LABEL: fcvt_d_w:236; RV64IZFINXZDINX: # %bb.0:237; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0238; RV64IZFINXZDINX-NEXT: ret239;240; RV32I-LABEL: fcvt_d_w:241; RV32I: # %bb.0:242; RV32I-NEXT: addi sp, sp, -16243; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill244; RV32I-NEXT: call __floatsidf245; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload246; RV32I-NEXT: addi sp, sp, 16247; RV32I-NEXT: ret248;249; RV64I-LABEL: fcvt_d_w:250; RV64I: # %bb.0:251; RV64I-NEXT: addi sp, sp, -16252; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill253; RV64I-NEXT: sext.w a0, a0254; RV64I-NEXT: call __floatsidf255; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload256; RV64I-NEXT: addi sp, sp, 16257; RV64I-NEXT: ret258 %1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")259 ret double %1260}261 262define double @fcvt_d_w_load(ptr %p) nounwind strictfp {263; CHECKIFD-LABEL: fcvt_d_w_load:264; CHECKIFD: # %bb.0:265; CHECKIFD-NEXT: lw a0, 0(a0)266; CHECKIFD-NEXT: fcvt.d.w fa0, a0267; CHECKIFD-NEXT: ret268;269; RV32IZFINXZDINX-LABEL: fcvt_d_w_load:270; RV32IZFINXZDINX: # %bb.0:271; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)272; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0273; RV32IZFINXZDINX-NEXT: ret274;275; RV64IZFINXZDINX-LABEL: fcvt_d_w_load:276; RV64IZFINXZDINX: # %bb.0:277; RV64IZFINXZDINX-NEXT: lw a0, 0(a0)278; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0279; RV64IZFINXZDINX-NEXT: ret280;281; RV32I-LABEL: fcvt_d_w_load:282; RV32I: # %bb.0:283; RV32I-NEXT: addi sp, sp, -16284; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill285; RV32I-NEXT: lw a0, 0(a0)286; RV32I-NEXT: call __floatsidf287; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload288; RV32I-NEXT: addi sp, sp, 16289; RV32I-NEXT: ret290;291; RV64I-LABEL: fcvt_d_w_load:292; RV64I: # %bb.0:293; RV64I-NEXT: addi sp, sp, -16294; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill295; RV64I-NEXT: lw a0, 0(a0)296; RV64I-NEXT: call __floatsidf297; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload298; RV64I-NEXT: addi sp, sp, 16299; RV64I-NEXT: ret300 %a = load i32, ptr %p301 %1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")302 ret double %1303}304 305define double @fcvt_d_wu(i32 %a) nounwind strictfp {306; CHECKIFD-LABEL: fcvt_d_wu:307; CHECKIFD: # %bb.0:308; CHECKIFD-NEXT: fcvt.d.wu fa0, a0309; CHECKIFD-NEXT: ret310;311; RV32IZFINXZDINX-LABEL: fcvt_d_wu:312; RV32IZFINXZDINX: # %bb.0:313; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0314; RV32IZFINXZDINX-NEXT: ret315;316; RV64IZFINXZDINX-LABEL: fcvt_d_wu:317; RV64IZFINXZDINX: # %bb.0:318; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0319; RV64IZFINXZDINX-NEXT: ret320;321; RV32I-LABEL: fcvt_d_wu:322; RV32I: # %bb.0:323; RV32I-NEXT: addi sp, sp, -16324; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill325; RV32I-NEXT: call __floatunsidf326; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload327; RV32I-NEXT: addi sp, sp, 16328; RV32I-NEXT: ret329;330; RV64I-LABEL: fcvt_d_wu:331; RV64I: # %bb.0:332; RV64I-NEXT: addi sp, sp, -16333; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill334; RV64I-NEXT: sext.w a0, a0335; RV64I-NEXT: call __floatunsidf336; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload337; RV64I-NEXT: addi sp, sp, 16338; RV64I-NEXT: ret339 %1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")340 ret double %1341}342 343define double @fcvt_d_wu_load(ptr %p) nounwind strictfp {344; CHECKIFD-LABEL: fcvt_d_wu_load:345; CHECKIFD: # %bb.0:346; CHECKIFD-NEXT: lw a0, 0(a0)347; CHECKIFD-NEXT: fcvt.d.wu fa0, a0348; CHECKIFD-NEXT: ret349;350; RV32IZFINXZDINX-LABEL: fcvt_d_wu_load:351; RV32IZFINXZDINX: # %bb.0:352; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)353; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0354; RV32IZFINXZDINX-NEXT: ret355;356; RV64IZFINXZDINX-LABEL: fcvt_d_wu_load:357; RV64IZFINXZDINX: # %bb.0:358; RV64IZFINXZDINX-NEXT: lw a0, 0(a0)359; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0360; RV64IZFINXZDINX-NEXT: ret361;362; RV32I-LABEL: fcvt_d_wu_load:363; RV32I: # %bb.0:364; RV32I-NEXT: addi sp, sp, -16365; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill366; RV32I-NEXT: lw a0, 0(a0)367; RV32I-NEXT: call __floatunsidf368; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload369; RV32I-NEXT: addi sp, sp, 16370; RV32I-NEXT: ret371;372; RV64I-LABEL: fcvt_d_wu_load:373; RV64I: # %bb.0:374; RV64I-NEXT: addi sp, sp, -16375; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill376; RV64I-NEXT: lw a0, 0(a0)377; RV64I-NEXT: call __floatunsidf378; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload379; RV64I-NEXT: addi sp, sp, 16380; RV64I-NEXT: ret381 %a = load i32, ptr %p382 %1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")383 ret double %1384}385 386define i64 @fcvt_l_d(double %a) nounwind strictfp {387; RV32IFD-LABEL: fcvt_l_d:388; RV32IFD: # %bb.0:389; RV32IFD-NEXT: addi sp, sp, -16390; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill391; RV32IFD-NEXT: call __fixdfdi392; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload393; RV32IFD-NEXT: addi sp, sp, 16394; RV32IFD-NEXT: ret395;396; RV64IFD-LABEL: fcvt_l_d:397; RV64IFD: # %bb.0:398; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz399; RV64IFD-NEXT: ret400;401; RV32IZFINXZDINX-LABEL: fcvt_l_d:402; RV32IZFINXZDINX: # %bb.0:403; RV32IZFINXZDINX-NEXT: addi sp, sp, -16404; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill405; RV32IZFINXZDINX-NEXT: call __fixdfdi406; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload407; RV32IZFINXZDINX-NEXT: addi sp, sp, 16408; RV32IZFINXZDINX-NEXT: ret409;410; RV64IZFINXZDINX-LABEL: fcvt_l_d:411; RV64IZFINXZDINX: # %bb.0:412; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz413; RV64IZFINXZDINX-NEXT: ret414;415; RV32I-LABEL: fcvt_l_d:416; RV32I: # %bb.0:417; RV32I-NEXT: addi sp, sp, -16418; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill419; RV32I-NEXT: call __fixdfdi420; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload421; RV32I-NEXT: addi sp, sp, 16422; RV32I-NEXT: ret423;424; RV64I-LABEL: fcvt_l_d:425; RV64I: # %bb.0:426; RV64I-NEXT: addi sp, sp, -16427; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill428; RV64I-NEXT: call __fixdfdi429; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload430; RV64I-NEXT: addi sp, sp, 16431; RV64I-NEXT: ret432 %1 = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %a, metadata !"fpexcept.strict")433 ret i64 %1434}435 436define i64 @fcvt_lu_d(double %a) nounwind strictfp {437; RV32IFD-LABEL: fcvt_lu_d:438; RV32IFD: # %bb.0:439; RV32IFD-NEXT: addi sp, sp, -16440; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill441; RV32IFD-NEXT: call __fixunsdfdi442; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload443; RV32IFD-NEXT: addi sp, sp, 16444; RV32IFD-NEXT: ret445;446; RV64IFD-LABEL: fcvt_lu_d:447; RV64IFD: # %bb.0:448; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz449; RV64IFD-NEXT: ret450;451; RV32IZFINXZDINX-LABEL: fcvt_lu_d:452; RV32IZFINXZDINX: # %bb.0:453; RV32IZFINXZDINX-NEXT: addi sp, sp, -16454; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill455; RV32IZFINXZDINX-NEXT: call __fixunsdfdi456; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload457; RV32IZFINXZDINX-NEXT: addi sp, sp, 16458; RV32IZFINXZDINX-NEXT: ret459;460; RV64IZFINXZDINX-LABEL: fcvt_lu_d:461; RV64IZFINXZDINX: # %bb.0:462; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz463; RV64IZFINXZDINX-NEXT: ret464;465; RV32I-LABEL: fcvt_lu_d:466; RV32I: # %bb.0:467; RV32I-NEXT: addi sp, sp, -16468; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill469; RV32I-NEXT: call __fixunsdfdi470; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload471; RV32I-NEXT: addi sp, sp, 16472; RV32I-NEXT: ret473;474; RV64I-LABEL: fcvt_lu_d:475; RV64I: # %bb.0:476; RV64I-NEXT: addi sp, sp, -16477; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill478; RV64I-NEXT: call __fixunsdfdi479; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload480; RV64I-NEXT: addi sp, sp, 16481; RV64I-NEXT: ret482 %1 = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %a, metadata !"fpexcept.strict")483 ret i64 %1484}485 486define double @fcvt_d_l(i64 %a) nounwind strictfp {487; RV32IFD-LABEL: fcvt_d_l:488; RV32IFD: # %bb.0:489; RV32IFD-NEXT: addi sp, sp, -16490; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill491; RV32IFD-NEXT: call __floatdidf492; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload493; RV32IFD-NEXT: addi sp, sp, 16494; RV32IFD-NEXT: ret495;496; RV64IFD-LABEL: fcvt_d_l:497; RV64IFD: # %bb.0:498; RV64IFD-NEXT: fcvt.d.l fa0, a0499; RV64IFD-NEXT: ret500;501; RV32IZFINXZDINX-LABEL: fcvt_d_l:502; RV32IZFINXZDINX: # %bb.0:503; RV32IZFINXZDINX-NEXT: addi sp, sp, -16504; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill505; RV32IZFINXZDINX-NEXT: call __floatdidf506; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload507; RV32IZFINXZDINX-NEXT: addi sp, sp, 16508; RV32IZFINXZDINX-NEXT: ret509;510; RV64IZFINXZDINX-LABEL: fcvt_d_l:511; RV64IZFINXZDINX: # %bb.0:512; RV64IZFINXZDINX-NEXT: fcvt.d.l a0, a0513; RV64IZFINXZDINX-NEXT: ret514;515; RV32I-LABEL: fcvt_d_l:516; RV32I: # %bb.0:517; RV32I-NEXT: addi sp, sp, -16518; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill519; RV32I-NEXT: call __floatdidf520; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload521; RV32I-NEXT: addi sp, sp, 16522; RV32I-NEXT: ret523;524; RV64I-LABEL: fcvt_d_l:525; RV64I: # %bb.0:526; RV64I-NEXT: addi sp, sp, -16527; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill528; RV64I-NEXT: call __floatdidf529; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload530; RV64I-NEXT: addi sp, sp, 16531; RV64I-NEXT: ret532 %1 = call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")533 ret double %1534}535 536define double @fcvt_d_lu(i64 %a) nounwind strictfp {537; RV32IFD-LABEL: fcvt_d_lu:538; RV32IFD: # %bb.0:539; RV32IFD-NEXT: addi sp, sp, -16540; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill541; RV32IFD-NEXT: call __floatundidf542; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload543; RV32IFD-NEXT: addi sp, sp, 16544; RV32IFD-NEXT: ret545;546; RV64IFD-LABEL: fcvt_d_lu:547; RV64IFD: # %bb.0:548; RV64IFD-NEXT: fcvt.d.lu fa0, a0549; RV64IFD-NEXT: ret550;551; RV32IZFINXZDINX-LABEL: fcvt_d_lu:552; RV32IZFINXZDINX: # %bb.0:553; RV32IZFINXZDINX-NEXT: addi sp, sp, -16554; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill555; RV32IZFINXZDINX-NEXT: call __floatundidf556; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload557; RV32IZFINXZDINX-NEXT: addi sp, sp, 16558; RV32IZFINXZDINX-NEXT: ret559;560; RV64IZFINXZDINX-LABEL: fcvt_d_lu:561; RV64IZFINXZDINX: # %bb.0:562; RV64IZFINXZDINX-NEXT: fcvt.d.lu a0, a0563; RV64IZFINXZDINX-NEXT: ret564;565; RV32I-LABEL: fcvt_d_lu:566; RV32I: # %bb.0:567; RV32I-NEXT: addi sp, sp, -16568; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill569; RV32I-NEXT: call __floatundidf570; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload571; RV32I-NEXT: addi sp, sp, 16572; RV32I-NEXT: ret573;574; RV64I-LABEL: fcvt_d_lu:575; RV64I: # %bb.0:576; RV64I-NEXT: addi sp, sp, -16577; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill578; RV64I-NEXT: call __floatundidf579; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload580; RV64I-NEXT: addi sp, sp, 16581; RV64I-NEXT: ret582 %1 = call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")583 ret double %1584}585 586define double @fcvt_d_w_i8(i8 signext %a) nounwind strictfp {587; CHECKIFD-LABEL: fcvt_d_w_i8:588; CHECKIFD: # %bb.0:589; CHECKIFD-NEXT: fcvt.d.w fa0, a0590; CHECKIFD-NEXT: ret591;592; RV32IZFINXZDINX-LABEL: fcvt_d_w_i8:593; RV32IZFINXZDINX: # %bb.0:594; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0595; RV32IZFINXZDINX-NEXT: ret596;597; RV64IZFINXZDINX-LABEL: fcvt_d_w_i8:598; RV64IZFINXZDINX: # %bb.0:599; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0600; RV64IZFINXZDINX-NEXT: ret601;602; RV32I-LABEL: fcvt_d_w_i8:603; RV32I: # %bb.0:604; RV32I-NEXT: addi sp, sp, -16605; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill606; RV32I-NEXT: call __floatsidf607; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload608; RV32I-NEXT: addi sp, sp, 16609; RV32I-NEXT: ret610;611; RV64I-LABEL: fcvt_d_w_i8:612; RV64I: # %bb.0:613; RV64I-NEXT: addi sp, sp, -16614; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill615; RV64I-NEXT: call __floatsidf616; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload617; RV64I-NEXT: addi sp, sp, 16618; RV64I-NEXT: ret619 %1 = call double @llvm.experimental.constrained.sitofp.f64.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")620 ret double %1621}622 623define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind strictfp {624; CHECKIFD-LABEL: fcvt_d_wu_i8:625; CHECKIFD: # %bb.0:626; CHECKIFD-NEXT: fcvt.d.wu fa0, a0627; CHECKIFD-NEXT: ret628;629; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i8:630; RV32IZFINXZDINX: # %bb.0:631; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0632; RV32IZFINXZDINX-NEXT: ret633;634; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i8:635; RV64IZFINXZDINX: # %bb.0:636; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0637; RV64IZFINXZDINX-NEXT: ret638;639; RV32I-LABEL: fcvt_d_wu_i8:640; RV32I: # %bb.0:641; RV32I-NEXT: addi sp, sp, -16642; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill643; RV32I-NEXT: call __floatunsidf644; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload645; RV32I-NEXT: addi sp, sp, 16646; RV32I-NEXT: ret647;648; RV64I-LABEL: fcvt_d_wu_i8:649; RV64I: # %bb.0:650; RV64I-NEXT: addi sp, sp, -16651; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill652; RV64I-NEXT: call __floatunsidf653; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload654; RV64I-NEXT: addi sp, sp, 16655; RV64I-NEXT: ret656 %1 = call double @llvm.experimental.constrained.uitofp.f64.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")657 ret double %1658}659 660define double @fcvt_d_w_i16(i16 signext %a) nounwind strictfp {661; CHECKIFD-LABEL: fcvt_d_w_i16:662; CHECKIFD: # %bb.0:663; CHECKIFD-NEXT: fcvt.d.w fa0, a0664; CHECKIFD-NEXT: ret665;666; RV32IZFINXZDINX-LABEL: fcvt_d_w_i16:667; RV32IZFINXZDINX: # %bb.0:668; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0669; RV32IZFINXZDINX-NEXT: ret670;671; RV64IZFINXZDINX-LABEL: fcvt_d_w_i16:672; RV64IZFINXZDINX: # %bb.0:673; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0674; RV64IZFINXZDINX-NEXT: ret675;676; RV32I-LABEL: fcvt_d_w_i16:677; RV32I: # %bb.0:678; RV32I-NEXT: addi sp, sp, -16679; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill680; RV32I-NEXT: call __floatsidf681; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload682; RV32I-NEXT: addi sp, sp, 16683; RV32I-NEXT: ret684;685; RV64I-LABEL: fcvt_d_w_i16:686; RV64I: # %bb.0:687; RV64I-NEXT: addi sp, sp, -16688; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill689; RV64I-NEXT: call __floatsidf690; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload691; RV64I-NEXT: addi sp, sp, 16692; RV64I-NEXT: ret693 %1 = call double @llvm.experimental.constrained.sitofp.f64.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")694 ret double %1695}696 697define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind strictfp {698; CHECKIFD-LABEL: fcvt_d_wu_i16:699; CHECKIFD: # %bb.0:700; CHECKIFD-NEXT: fcvt.d.wu fa0, a0701; CHECKIFD-NEXT: ret702;703; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i16:704; RV32IZFINXZDINX: # %bb.0:705; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0706; RV32IZFINXZDINX-NEXT: ret707;708; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i16:709; RV64IZFINXZDINX: # %bb.0:710; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0711; RV64IZFINXZDINX-NEXT: ret712;713; RV32I-LABEL: fcvt_d_wu_i16:714; RV32I: # %bb.0:715; RV32I-NEXT: addi sp, sp, -16716; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill717; RV32I-NEXT: call __floatunsidf718; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload719; RV32I-NEXT: addi sp, sp, 16720; RV32I-NEXT: ret721;722; RV64I-LABEL: fcvt_d_wu_i16:723; RV64I: # %bb.0:724; RV64I-NEXT: addi sp, sp, -16725; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill726; RV64I-NEXT: call __floatunsidf727; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload728; RV64I-NEXT: addi sp, sp, 16729; RV64I-NEXT: ret730 %1 = call double @llvm.experimental.constrained.uitofp.f64.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")731 ret double %1732}733 734; Make sure we select W version of addi on RV64.735define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind strictfp {736; RV32IFD-LABEL: fcvt_d_w_demanded_bits:737; RV32IFD: # %bb.0:738; RV32IFD-NEXT: addi a0, a0, 1739; RV32IFD-NEXT: fcvt.d.w fa5, a0740; RV32IFD-NEXT: fsd fa5, 0(a1)741; RV32IFD-NEXT: ret742;743; RV64IFD-LABEL: fcvt_d_w_demanded_bits:744; RV64IFD: # %bb.0:745; RV64IFD-NEXT: addiw a0, a0, 1746; RV64IFD-NEXT: fcvt.d.w fa5, a0747; RV64IFD-NEXT: fsd fa5, 0(a1)748; RV64IFD-NEXT: ret749;750; RV32IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:751; RV32IZFINXZDINX: # %bb.0:752; RV32IZFINXZDINX-NEXT: addi a0, a0, 1753; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, a0754; RV32IZFINXZDINX-NEXT: sw a2, 0(a1)755; RV32IZFINXZDINX-NEXT: sw a3, 4(a1)756; RV32IZFINXZDINX-NEXT: ret757;758; RV64IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:759; RV64IZFINXZDINX: # %bb.0:760; RV64IZFINXZDINX-NEXT: addiw a0, a0, 1761; RV64IZFINXZDINX-NEXT: fcvt.d.w a2, a0762; RV64IZFINXZDINX-NEXT: sd a2, 0(a1)763; RV64IZFINXZDINX-NEXT: ret764;765; RV32I-LABEL: fcvt_d_w_demanded_bits:766; RV32I: # %bb.0:767; RV32I-NEXT: addi sp, sp, -16768; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill769; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill770; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill771; RV32I-NEXT: mv s0, a1772; RV32I-NEXT: addi s1, a0, 1773; RV32I-NEXT: mv a0, s1774; RV32I-NEXT: call __floatsidf775; RV32I-NEXT: sw a0, 0(s0)776; RV32I-NEXT: sw a1, 4(s0)777; RV32I-NEXT: mv a0, s1778; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload779; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload780; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload781; RV32I-NEXT: addi sp, sp, 16782; RV32I-NEXT: ret783;784; RV64I-LABEL: fcvt_d_w_demanded_bits:785; RV64I: # %bb.0:786; RV64I-NEXT: addi sp, sp, -32787; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill788; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill789; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill790; RV64I-NEXT: mv s0, a1791; RV64I-NEXT: addiw s1, a0, 1792; RV64I-NEXT: mv a0, s1793; RV64I-NEXT: call __floatsidf794; RV64I-NEXT: sd a0, 0(s0)795; RV64I-NEXT: mv a0, s1796; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload797; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload798; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload799; RV64I-NEXT: addi sp, sp, 32800; RV64I-NEXT: ret801 %3 = add i32 %0, 1802 %4 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict")803 store double %4, ptr %1, align 8804 ret i32 %3805}806 807; Make sure we select W version of addi on RV64.808define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind strictfp {809; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:810; RV32IFD: # %bb.0:811; RV32IFD-NEXT: addi a0, a0, 1812; RV32IFD-NEXT: fcvt.d.wu fa5, a0813; RV32IFD-NEXT: fsd fa5, 0(a1)814; RV32IFD-NEXT: ret815;816; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:817; RV64IFD: # %bb.0:818; RV64IFD-NEXT: addiw a0, a0, 1819; RV64IFD-NEXT: fcvt.d.wu fa5, a0820; RV64IFD-NEXT: fsd fa5, 0(a1)821; RV64IFD-NEXT: ret822;823; RV32IZFINXZDINX-LABEL: fcvt_d_wu_demanded_bits:824; RV32IZFINXZDINX: # %bb.0:825; RV32IZFINXZDINX-NEXT: addi a0, a0, 1826; RV32IZFINXZDINX-NEXT: fcvt.d.wu a2, a0827; RV32IZFINXZDINX-NEXT: sw a2, 0(a1)828; RV32IZFINXZDINX-NEXT: sw a3, 4(a1)829; RV32IZFINXZDINX-NEXT: ret830;831; RV64IZFINXZDINX-LABEL: fcvt_d_wu_demanded_bits:832; RV64IZFINXZDINX: # %bb.0:833; RV64IZFINXZDINX-NEXT: addiw a0, a0, 1834; RV64IZFINXZDINX-NEXT: fcvt.d.wu a2, a0835; RV64IZFINXZDINX-NEXT: sd a2, 0(a1)836; RV64IZFINXZDINX-NEXT: ret837;838; RV32I-LABEL: fcvt_d_wu_demanded_bits:839; RV32I: # %bb.0:840; RV32I-NEXT: addi sp, sp, -16841; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill842; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill843; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill844; RV32I-NEXT: mv s0, a1845; RV32I-NEXT: addi s1, a0, 1846; RV32I-NEXT: mv a0, s1847; RV32I-NEXT: call __floatunsidf848; RV32I-NEXT: sw a0, 0(s0)849; RV32I-NEXT: sw a1, 4(s0)850; RV32I-NEXT: mv a0, s1851; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload852; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload853; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload854; RV32I-NEXT: addi sp, sp, 16855; RV32I-NEXT: ret856;857; RV64I-LABEL: fcvt_d_wu_demanded_bits:858; RV64I: # %bb.0:859; RV64I-NEXT: addi sp, sp, -32860; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill861; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill862; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill863; RV64I-NEXT: mv s0, a1864; RV64I-NEXT: addiw s1, a0, 1865; RV64I-NEXT: mv a0, s1866; RV64I-NEXT: call __floatunsidf867; RV64I-NEXT: sd a0, 0(s0)868; RV64I-NEXT: mv a0, s1869; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload870; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload871; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload872; RV64I-NEXT: addi sp, sp, 32873; RV64I-NEXT: ret874 %3 = add i32 %0, 1875 %4 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict")876 store double %4, ptr %1, align 8877 ret i32 %3878}879