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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \3; RUN: -verify-machineinstrs -target-abi=ilp32d \4; RUN: | FileCheck -check-prefixes=CHECKIFD %s5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \6; RUN: -verify-machineinstrs -target-abi=lp64d \7; RUN: | FileCheck -check-prefixes=CHECKIFD %s8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \9; RUN: -verify-machineinstrs -target-abi=ilp32 \10; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \12; RUN: -verify-machineinstrs -target-abi=lp64 \13; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s14 15define double @fminimum_f64(double %a, double %b) nounwind {16; CHECKIFD-LABEL: fminimum_f64:17; CHECKIFD: # %bb.0:18; CHECKIFD-NEXT: feq.d a0, fa0, fa019; CHECKIFD-NEXT: fmv.d fa5, fa120; CHECKIFD-NEXT: beqz a0, .LBB0_321; CHECKIFD-NEXT: # %bb.1:22; CHECKIFD-NEXT: feq.d a0, fa1, fa123; CHECKIFD-NEXT: beqz a0, .LBB0_424; CHECKIFD-NEXT: .LBB0_2:25; CHECKIFD-NEXT: fmin.d fa0, fa0, fa526; CHECKIFD-NEXT: ret27; CHECKIFD-NEXT: .LBB0_3:28; CHECKIFD-NEXT: fmv.d fa5, fa029; CHECKIFD-NEXT: feq.d a0, fa1, fa130; CHECKIFD-NEXT: bnez a0, .LBB0_231; CHECKIFD-NEXT: .LBB0_4:32; CHECKIFD-NEXT: fmin.d fa0, fa1, fa533; CHECKIFD-NEXT: ret34;35; RV32IZFINXZDINX-LABEL: fminimum_f64:36; RV32IZFINXZDINX: # %bb.0:37; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a038; RV32IZFINXZDINX-NEXT: fmv.d a4, a239; RV32IZFINXZDINX-NEXT: beqz a6, .LBB0_340; RV32IZFINXZDINX-NEXT: # %bb.1:41; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a242; RV32IZFINXZDINX-NEXT: beqz a6, .LBB0_443; RV32IZFINXZDINX-NEXT: .LBB0_2:44; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a445; RV32IZFINXZDINX-NEXT: ret46; RV32IZFINXZDINX-NEXT: .LBB0_3:47; RV32IZFINXZDINX-NEXT: fmv.d a4, a048; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a249; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_250; RV32IZFINXZDINX-NEXT: .LBB0_4:51; RV32IZFINXZDINX-NEXT: fmin.d a0, a2, a452; RV32IZFINXZDINX-NEXT: ret53;54; RV64IZFINXZDINX-LABEL: fminimum_f64:55; RV64IZFINXZDINX: # %bb.0:56; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a057; RV64IZFINXZDINX-NEXT: mv a2, a158; RV64IZFINXZDINX-NEXT: beqz a3, .LBB0_359; RV64IZFINXZDINX-NEXT: # %bb.1:60; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a161; RV64IZFINXZDINX-NEXT: beqz a3, .LBB0_462; RV64IZFINXZDINX-NEXT: .LBB0_2:63; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a264; RV64IZFINXZDINX-NEXT: ret65; RV64IZFINXZDINX-NEXT: .LBB0_3:66; RV64IZFINXZDINX-NEXT: mv a2, a067; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a168; RV64IZFINXZDINX-NEXT: bnez a3, .LBB0_269; RV64IZFINXZDINX-NEXT: .LBB0_4:70; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a271; RV64IZFINXZDINX-NEXT: ret72 %1 = call double @llvm.minimum.f64(double %a, double %b)73 ret double %174}75 76define double @fmaximum_f64(double %a, double %b) nounwind {77; CHECKIFD-LABEL: fmaximum_f64:78; CHECKIFD: # %bb.0:79; CHECKIFD-NEXT: feq.d a0, fa0, fa080; CHECKIFD-NEXT: fmv.d fa5, fa181; CHECKIFD-NEXT: beqz a0, .LBB1_382; CHECKIFD-NEXT: # %bb.1:83; CHECKIFD-NEXT: feq.d a0, fa1, fa184; CHECKIFD-NEXT: beqz a0, .LBB1_485; CHECKIFD-NEXT: .LBB1_2:86; CHECKIFD-NEXT: fmax.d fa0, fa0, fa587; CHECKIFD-NEXT: ret88; CHECKIFD-NEXT: .LBB1_3:89; CHECKIFD-NEXT: fmv.d fa5, fa090; CHECKIFD-NEXT: feq.d a0, fa1, fa191; CHECKIFD-NEXT: bnez a0, .LBB1_292; CHECKIFD-NEXT: .LBB1_4:93; CHECKIFD-NEXT: fmax.d fa0, fa1, fa594; CHECKIFD-NEXT: ret95;96; RV32IZFINXZDINX-LABEL: fmaximum_f64:97; RV32IZFINXZDINX: # %bb.0:98; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a099; RV32IZFINXZDINX-NEXT: fmv.d a4, a2100; RV32IZFINXZDINX-NEXT: beqz a6, .LBB1_3101; RV32IZFINXZDINX-NEXT: # %bb.1:102; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2103; RV32IZFINXZDINX-NEXT: beqz a6, .LBB1_4104; RV32IZFINXZDINX-NEXT: .LBB1_2:105; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4106; RV32IZFINXZDINX-NEXT: ret107; RV32IZFINXZDINX-NEXT: .LBB1_3:108; RV32IZFINXZDINX-NEXT: fmv.d a4, a0109; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2110; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_2111; RV32IZFINXZDINX-NEXT: .LBB1_4:112; RV32IZFINXZDINX-NEXT: fmax.d a0, a2, a4113; RV32IZFINXZDINX-NEXT: ret114;115; RV64IZFINXZDINX-LABEL: fmaximum_f64:116; RV64IZFINXZDINX: # %bb.0:117; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0118; RV64IZFINXZDINX-NEXT: mv a2, a1119; RV64IZFINXZDINX-NEXT: beqz a3, .LBB1_3120; RV64IZFINXZDINX-NEXT: # %bb.1:121; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1122; RV64IZFINXZDINX-NEXT: beqz a3, .LBB1_4123; RV64IZFINXZDINX-NEXT: .LBB1_2:124; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a2125; RV64IZFINXZDINX-NEXT: ret126; RV64IZFINXZDINX-NEXT: .LBB1_3:127; RV64IZFINXZDINX-NEXT: mv a2, a0128; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1129; RV64IZFINXZDINX-NEXT: bnez a3, .LBB1_2130; RV64IZFINXZDINX-NEXT: .LBB1_4:131; RV64IZFINXZDINX-NEXT: fmax.d a0, a1, a2132; RV64IZFINXZDINX-NEXT: ret133 %1 = call double @llvm.maximum.f64(double %a, double %b)134 ret double %1135}136 137define double @fminimum_nnan_f64(double %a, double %b) nounwind {138; CHECKIFD-LABEL: fminimum_nnan_f64:139; CHECKIFD: # %bb.0:140; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1141; CHECKIFD-NEXT: ret142;143; RV32IZFINXZDINX-LABEL: fminimum_nnan_f64:144; RV32IZFINXZDINX: # %bb.0:145; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2146; RV32IZFINXZDINX-NEXT: ret147;148; RV64IZFINXZDINX-LABEL: fminimum_nnan_f64:149; RV64IZFINXZDINX: # %bb.0:150; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1151; RV64IZFINXZDINX-NEXT: ret152 %1 = call nnan double @llvm.minimum.f64(double %a, double %b)153 ret double %1154}155 156define double @fmaximum_nnan_f64(double %a, double %b) nounwind {157; CHECKIFD-LABEL: fmaximum_nnan_f64:158; CHECKIFD: # %bb.0:159; CHECKIFD-NEXT: feq.d a0, fa0, fa0160; CHECKIFD-NEXT: fmv.d fa5, fa1161; CHECKIFD-NEXT: beqz a0, .LBB3_3162; CHECKIFD-NEXT: # %bb.1:163; CHECKIFD-NEXT: feq.d a0, fa1, fa1164; CHECKIFD-NEXT: beqz a0, .LBB3_4165; CHECKIFD-NEXT: .LBB3_2:166; CHECKIFD-NEXT: fmin.d fa0, fa0, fa5167; CHECKIFD-NEXT: ret168; CHECKIFD-NEXT: .LBB3_3:169; CHECKIFD-NEXT: fmv.d fa5, fa0170; CHECKIFD-NEXT: feq.d a0, fa1, fa1171; CHECKIFD-NEXT: bnez a0, .LBB3_2172; CHECKIFD-NEXT: .LBB3_4:173; CHECKIFD-NEXT: fmin.d fa0, fa1, fa5174; CHECKIFD-NEXT: ret175;176; RV32IZFINXZDINX-LABEL: fmaximum_nnan_f64:177; RV32IZFINXZDINX: # %bb.0:178; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0179; RV32IZFINXZDINX-NEXT: fmv.d a4, a2180; RV32IZFINXZDINX-NEXT: beqz a6, .LBB3_3181; RV32IZFINXZDINX-NEXT: # %bb.1:182; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2183; RV32IZFINXZDINX-NEXT: beqz a6, .LBB3_4184; RV32IZFINXZDINX-NEXT: .LBB3_2:185; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4186; RV32IZFINXZDINX-NEXT: ret187; RV32IZFINXZDINX-NEXT: .LBB3_3:188; RV32IZFINXZDINX-NEXT: fmv.d a4, a0189; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2190; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_2191; RV32IZFINXZDINX-NEXT: .LBB3_4:192; RV32IZFINXZDINX-NEXT: fmin.d a0, a2, a4193; RV32IZFINXZDINX-NEXT: ret194;195; RV64IZFINXZDINX-LABEL: fmaximum_nnan_f64:196; RV64IZFINXZDINX: # %bb.0:197; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0198; RV64IZFINXZDINX-NEXT: mv a2, a1199; RV64IZFINXZDINX-NEXT: beqz a3, .LBB3_3200; RV64IZFINXZDINX-NEXT: # %bb.1:201; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1202; RV64IZFINXZDINX-NEXT: beqz a3, .LBB3_4203; RV64IZFINXZDINX-NEXT: .LBB3_2:204; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2205; RV64IZFINXZDINX-NEXT: ret206; RV64IZFINXZDINX-NEXT: .LBB3_3:207; RV64IZFINXZDINX-NEXT: mv a2, a0208; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1209; RV64IZFINXZDINX-NEXT: bnez a3, .LBB3_2210; RV64IZFINXZDINX-NEXT: .LBB3_4:211; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a2212; RV64IZFINXZDINX-NEXT: ret213 %1 = call double @llvm.minimum.f64(double %a, double %b)214 ret double %1215}216 217define double @fminimum_nnan_op_f64(double %a, double %b) nounwind {218; CHECKIFD-LABEL: fminimum_nnan_op_f64:219; CHECKIFD: # %bb.0:220; CHECKIFD-NEXT: feq.d a0, fa1, fa1221; CHECKIFD-NEXT: bnez a0, .LBB4_2222; CHECKIFD-NEXT: # %bb.1:223; CHECKIFD-NEXT: fmin.d fa0, fa1, fa1224; CHECKIFD-NEXT: ret225; CHECKIFD-NEXT: .LBB4_2:226; CHECKIFD-NEXT: fadd.d fa5, fa0, fa0227; CHECKIFD-NEXT: fmin.d fa0, fa5, fa1228; CHECKIFD-NEXT: ret229;230; RV32IZFINXZDINX-LABEL: fminimum_nnan_op_f64:231; RV32IZFINXZDINX: # %bb.0:232; RV32IZFINXZDINX-NEXT: feq.d a4, a2, a2233; RV32IZFINXZDINX-NEXT: bnez a4, .LBB4_2234; RV32IZFINXZDINX-NEXT: # %bb.1:235; RV32IZFINXZDINX-NEXT: fmin.d a0, a2, a2236; RV32IZFINXZDINX-NEXT: ret237; RV32IZFINXZDINX-NEXT: .LBB4_2:238; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a0239; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2240; RV32IZFINXZDINX-NEXT: ret241;242; RV64IZFINXZDINX-LABEL: fminimum_nnan_op_f64:243; RV64IZFINXZDINX: # %bb.0:244; RV64IZFINXZDINX-NEXT: feq.d a2, a1, a1245; RV64IZFINXZDINX-NEXT: bnez a2, .LBB4_2246; RV64IZFINXZDINX-NEXT: # %bb.1:247; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a1248; RV64IZFINXZDINX-NEXT: ret249; RV64IZFINXZDINX-NEXT: .LBB4_2:250; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a0251; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1252; RV64IZFINXZDINX-NEXT: ret253 %c = fadd nnan double %a, %a254 %1 = call double @llvm.minimum.f64(double %c, double %b)255 ret double %1256}257 258define double @fmaximum_nnan_op_f64(double %a, double %b) nounwind {259; CHECKIFD-LABEL: fmaximum_nnan_op_f64:260; CHECKIFD: # %bb.0:261; CHECKIFD-NEXT: fadd.d fa5, fa0, fa1262; CHECKIFD-NEXT: fsub.d fa4, fa0, fa1263; CHECKIFD-NEXT: fmax.d fa0, fa5, fa4264; CHECKIFD-NEXT: ret265;266; RV32IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:267; RV32IZFINXZDINX: # %bb.0:268; RV32IZFINXZDINX-NEXT: fadd.d a4, a0, a2269; RV32IZFINXZDINX-NEXT: fsub.d a0, a0, a2270; RV32IZFINXZDINX-NEXT: fmax.d a0, a4, a0271; RV32IZFINXZDINX-NEXT: ret272;273; RV64IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:274; RV64IZFINXZDINX: # %bb.0:275; RV64IZFINXZDINX-NEXT: fadd.d a2, a0, a1276; RV64IZFINXZDINX-NEXT: fsub.d a0, a0, a1277; RV64IZFINXZDINX-NEXT: fmax.d a0, a2, a0278; RV64IZFINXZDINX-NEXT: ret279 %c = fadd nnan double %a, %b280 %d = fsub nnan double %a, %b281 %1 = call double @llvm.maximum.f64(double %c, double %d)282 ret double %1283}284