436 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \5; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s6; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \7; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32IZFINXZDINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \9; RUN: -target-abi=lp64 | FileCheck -check-prefixes=RV64IZFINXZDINX %s10; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zilsd -verify-machineinstrs < %s \11; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32IZFINXZDINXZILSD %s12 13define dso_local double @fld(ptr %a) nounwind {14; CHECKIFD-LABEL: fld:15; CHECKIFD: # %bb.0:16; CHECKIFD-NEXT: fld fa5, 0(a0)17; CHECKIFD-NEXT: fld fa4, 24(a0)18; CHECKIFD-NEXT: fadd.d fa0, fa5, fa419; CHECKIFD-NEXT: ret20;21; RV32IZFINXZDINX-LABEL: fld:22; RV32IZFINXZDINX: # %bb.0:23; RV32IZFINXZDINX-NEXT: lw a3, 4(a0)24; RV32IZFINXZDINX-NEXT: lw a1, 28(a0)25; RV32IZFINXZDINX-NEXT: lw a2, 0(a0)26; RV32IZFINXZDINX-NEXT: lw a0, 24(a0)27; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a028; RV32IZFINXZDINX-NEXT: ret29;30; RV64IZFINXZDINX-LABEL: fld:31; RV64IZFINXZDINX: # %bb.0:32; RV64IZFINXZDINX-NEXT: ld a1, 0(a0)33; RV64IZFINXZDINX-NEXT: ld a0, 24(a0)34; RV64IZFINXZDINX-NEXT: fadd.d a0, a1, a035; RV64IZFINXZDINX-NEXT: ret36;37; RV32IZFINXZDINXZILSD-LABEL: fld:38; RV32IZFINXZDINXZILSD: # %bb.0:39; RV32IZFINXZDINXZILSD-NEXT: ld a2, 0(a0)40; RV32IZFINXZDINXZILSD-NEXT: ld a0, 24(a0)41; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a2, a042; RV32IZFINXZDINXZILSD-NEXT: ret43 %1 = load double, ptr %a44 %2 = getelementptr double, ptr %a, i32 345 %3 = load double, ptr %246; Use both loaded values in an FP op to ensure an fld is used, even for the47; soft float ABI48 %4 = fadd double %1, %349 ret double %450}51 52define dso_local void @fsd(ptr %a, double %b, double %c) nounwind {53; CHECKIFD-LABEL: fsd:54; CHECKIFD: # %bb.0:55; CHECKIFD-NEXT: fadd.d fa5, fa0, fa156; CHECKIFD-NEXT: fsd fa5, 0(a0)57; CHECKIFD-NEXT: fsd fa5, 64(a0)58; CHECKIFD-NEXT: ret59;60; RV32IZFINXZDINX-LABEL: fsd:61; RV32IZFINXZDINX: # %bb.0:62; RV32IZFINXZDINX-NEXT: mv a5, a463; RV32IZFINXZDINX-NEXT: mv a7, a264; RV32IZFINXZDINX-NEXT: mv a4, a365; RV32IZFINXZDINX-NEXT: mv a6, a166; RV32IZFINXZDINX-NEXT: fadd.d a2, a6, a467; RV32IZFINXZDINX-NEXT: sw a2, 0(a0)68; RV32IZFINXZDINX-NEXT: sw a3, 4(a0)69; RV32IZFINXZDINX-NEXT: sw a2, 64(a0)70; RV32IZFINXZDINX-NEXT: sw a3, 68(a0)71; RV32IZFINXZDINX-NEXT: ret72;73; RV64IZFINXZDINX-LABEL: fsd:74; RV64IZFINXZDINX: # %bb.0:75; RV64IZFINXZDINX-NEXT: fadd.d a1, a1, a276; RV64IZFINXZDINX-NEXT: sd a1, 0(a0)77; RV64IZFINXZDINX-NEXT: sd a1, 64(a0)78; RV64IZFINXZDINX-NEXT: ret79;80; RV32IZFINXZDINXZILSD-LABEL: fsd:81; RV32IZFINXZDINXZILSD: # %bb.0:82; RV32IZFINXZDINXZILSD-NEXT: mv a5, a483; RV32IZFINXZDINXZILSD-NEXT: mv a7, a284; RV32IZFINXZDINXZILSD-NEXT: mv a4, a385; RV32IZFINXZDINXZILSD-NEXT: mv a6, a186; RV32IZFINXZDINXZILSD-NEXT: fadd.d a2, a6, a487; RV32IZFINXZDINXZILSD-NEXT: sd a2, 0(a0)88; RV32IZFINXZDINXZILSD-NEXT: sd a2, 64(a0)89; RV32IZFINXZDINXZILSD-NEXT: ret90; Use %b and %c in an FP op to ensure floating point registers are used, even91; for the soft float ABI92 %1 = fadd double %b, %c93 store double %1, ptr %a94 %2 = getelementptr double, ptr %a, i32 895 store double %1, ptr %296 ret void97}98 99; Check load and store to a global100@G = dso_local global double 0.0101 102define dso_local double @fld_fsd_global(double %a, double %b) nounwind {103; CHECKIFD-LABEL: fld_fsd_global:104; CHECKIFD: # %bb.0:105; CHECKIFD-NEXT: fadd.d fa0, fa0, fa1106; CHECKIFD-NEXT: lui a0, %hi(G)107; CHECKIFD-NEXT: addi a0, a0, %lo(G)108; CHECKIFD-NEXT: fld fa5, 0(a0)109; CHECKIFD-NEXT: fsd fa0, 0(a0)110; CHECKIFD-NEXT: fld fa5, 72(a0)111; CHECKIFD-NEXT: fsd fa0, 72(a0)112; CHECKIFD-NEXT: ret113;114; RV32IZFINXZDINX-LABEL: fld_fsd_global:115; RV32IZFINXZDINX: # %bb.0:116; RV32IZFINXZDINX-NEXT: lui a4, %hi(G)117; RV32IZFINXZDINX-NEXT: addi a4, a4, %lo(G)118; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2119; RV32IZFINXZDINX-NEXT: lw zero, 0(a4)120; RV32IZFINXZDINX-NEXT: lw zero, 4(a4)121; RV32IZFINXZDINX-NEXT: sw a0, 0(a4)122; RV32IZFINXZDINX-NEXT: sw a1, 4(a4)123; RV32IZFINXZDINX-NEXT: lw zero, 72(a4)124; RV32IZFINXZDINX-NEXT: lw zero, 76(a4)125; RV32IZFINXZDINX-NEXT: sw a0, 72(a4)126; RV32IZFINXZDINX-NEXT: sw a1, 76(a4)127; RV32IZFINXZDINX-NEXT: ret128;129; RV64IZFINXZDINX-LABEL: fld_fsd_global:130; RV64IZFINXZDINX: # %bb.0:131; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1132; RV64IZFINXZDINX-NEXT: lui a1, %hi(G)133; RV64IZFINXZDINX-NEXT: addi a1, a1, %lo(G)134; RV64IZFINXZDINX-NEXT: ld zero, 0(a1)135; RV64IZFINXZDINX-NEXT: sd a0, 0(a1)136; RV64IZFINXZDINX-NEXT: ld zero, 72(a1)137; RV64IZFINXZDINX-NEXT: sd a0, 72(a1)138; RV64IZFINXZDINX-NEXT: ret139;140; RV32IZFINXZDINXZILSD-LABEL: fld_fsd_global:141; RV32IZFINXZDINXZILSD: # %bb.0:142; RV32IZFINXZDINXZILSD-NEXT: lui a4, %hi(G)143; RV32IZFINXZDINXZILSD-NEXT: addi a4, a4, %lo(G)144; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2145; RV32IZFINXZDINXZILSD-NEXT: ld zero, 0(a4)146; RV32IZFINXZDINXZILSD-NEXT: sd a0, 0(a4)147; RV32IZFINXZDINXZILSD-NEXT: ld zero, 72(a4)148; RV32IZFINXZDINXZILSD-NEXT: sd a0, 72(a4)149; RV32IZFINXZDINXZILSD-NEXT: ret150; Use %a and %b in an FP op to ensure floating point registers are used, even151; for the soft float ABI152 %1 = fadd double %a, %b153 %2 = load volatile double, ptr @G154 store double %1, ptr @G155 %3 = getelementptr double, ptr @G, i32 9156 %4 = load volatile double, ptr %3157 store double %1, ptr %3158 ret double %1159}160 161; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1162define dso_local double @fld_fsd_constant(double %a) nounwind {163; RV32IFD-LABEL: fld_fsd_constant:164; RV32IFD: # %bb.0:165; RV32IFD-NEXT: lui a0, 912092166; RV32IFD-NEXT: fld fa5, -273(a0)167; RV32IFD-NEXT: fadd.d fa0, fa0, fa5168; RV32IFD-NEXT: fsd fa0, -273(a0)169; RV32IFD-NEXT: ret170;171; RV64IFD-LABEL: fld_fsd_constant:172; RV64IFD: # %bb.0:173; RV64IFD-NEXT: lui a0, 228023174; RV64IFD-NEXT: slli a0, a0, 2175; RV64IFD-NEXT: fld fa5, -273(a0)176; RV64IFD-NEXT: fadd.d fa0, fa0, fa5177; RV64IFD-NEXT: fsd fa0, -273(a0)178; RV64IFD-NEXT: ret179;180; RV32IZFINXZDINX-LABEL: fld_fsd_constant:181; RV32IZFINXZDINX: # %bb.0:182; RV32IZFINXZDINX-NEXT: lui a2, 912092183; RV32IZFINXZDINX-NEXT: lw a4, -273(a2)184; RV32IZFINXZDINX-NEXT: lw a5, -269(a2)185; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a4186; RV32IZFINXZDINX-NEXT: sw a0, -273(a2)187; RV32IZFINXZDINX-NEXT: sw a1, -269(a2)188; RV32IZFINXZDINX-NEXT: ret189;190; RV64IZFINXZDINX-LABEL: fld_fsd_constant:191; RV64IZFINXZDINX: # %bb.0:192; RV64IZFINXZDINX-NEXT: lui a1, 228023193; RV64IZFINXZDINX-NEXT: slli a1, a1, 2194; RV64IZFINXZDINX-NEXT: ld a2, -273(a1)195; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a2196; RV64IZFINXZDINX-NEXT: sd a0, -273(a1)197; RV64IZFINXZDINX-NEXT: ret198;199; RV32IZFINXZDINXZILSD-LABEL: fld_fsd_constant:200; RV32IZFINXZDINXZILSD: # %bb.0:201; RV32IZFINXZDINXZILSD-NEXT: lui a2, 912092202; RV32IZFINXZDINXZILSD-NEXT: ld a4, -273(a2)203; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a4204; RV32IZFINXZDINXZILSD-NEXT: sd a0, -273(a2)205; RV32IZFINXZDINXZILSD-NEXT: ret206 %1 = inttoptr i32 3735928559 to ptr207 %2 = load volatile double, ptr %1208 %3 = fadd double %a, %2209 store double %3, ptr %1210 ret double %3211}212 213declare void @notdead(ptr)214 215define dso_local double @fld_stack(double %a) nounwind {216; RV32IFD-LABEL: fld_stack:217; RV32IFD: # %bb.0:218; RV32IFD-NEXT: addi sp, sp, -32219; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill220; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill221; RV32IFD-NEXT: fmv.d fs0, fa0222; RV32IFD-NEXT: addi a0, sp, 8223; RV32IFD-NEXT: call notdead224; RV32IFD-NEXT: fld fa5, 8(sp)225; RV32IFD-NEXT: fadd.d fa0, fa5, fs0226; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload227; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload228; RV32IFD-NEXT: addi sp, sp, 32229; RV32IFD-NEXT: ret230;231; RV64IFD-LABEL: fld_stack:232; RV64IFD: # %bb.0:233; RV64IFD-NEXT: addi sp, sp, -32234; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill235; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill236; RV64IFD-NEXT: fmv.d fs0, fa0237; RV64IFD-NEXT: addi a0, sp, 8238; RV64IFD-NEXT: call notdead239; RV64IFD-NEXT: fld fa5, 8(sp)240; RV64IFD-NEXT: fadd.d fa0, fa5, fs0241; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload242; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload243; RV64IFD-NEXT: addi sp, sp, 32244; RV64IFD-NEXT: ret245;246; RV32IZFINXZDINX-LABEL: fld_stack:247; RV32IZFINXZDINX: # %bb.0:248; RV32IZFINXZDINX-NEXT: addi sp, sp, -32249; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill250; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill251; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill252; RV32IZFINXZDINX-NEXT: mv s1, a1253; RV32IZFINXZDINX-NEXT: mv s0, a0254; RV32IZFINXZDINX-NEXT: addi a0, sp, 8255; RV32IZFINXZDINX-NEXT: call notdead256; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)257; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)258; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, s0259; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload260; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload261; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload262; RV32IZFINXZDINX-NEXT: addi sp, sp, 32263; RV32IZFINXZDINX-NEXT: ret264;265; RV64IZFINXZDINX-LABEL: fld_stack:266; RV64IZFINXZDINX: # %bb.0:267; RV64IZFINXZDINX-NEXT: addi sp, sp, -32268; RV64IZFINXZDINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill269; RV64IZFINXZDINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill270; RV64IZFINXZDINX-NEXT: mv s0, a0271; RV64IZFINXZDINX-NEXT: addi a0, sp, 8272; RV64IZFINXZDINX-NEXT: call notdead273; RV64IZFINXZDINX-NEXT: ld a0, 8(sp)274; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, s0275; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload276; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload277; RV64IZFINXZDINX-NEXT: addi sp, sp, 32278; RV64IZFINXZDINX-NEXT: ret279;280; RV32IZFINXZDINXZILSD-LABEL: fld_stack:281; RV32IZFINXZDINXZILSD: # %bb.0:282; RV32IZFINXZDINXZILSD-NEXT: addi sp, sp, -32283; RV32IZFINXZDINXZILSD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill284; RV32IZFINXZDINXZILSD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill285; RV32IZFINXZDINXZILSD-NEXT: sw s1, 20(sp) # 4-byte Folded Spill286; RV32IZFINXZDINXZILSD-NEXT: mv s1, a1287; RV32IZFINXZDINXZILSD-NEXT: mv s0, a0288; RV32IZFINXZDINXZILSD-NEXT: addi a0, sp, 8289; RV32IZFINXZDINXZILSD-NEXT: call notdead290; RV32IZFINXZDINXZILSD-NEXT: ld a0, 8(sp)291; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, s0292; RV32IZFINXZDINXZILSD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload293; RV32IZFINXZDINXZILSD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload294; RV32IZFINXZDINXZILSD-NEXT: lw s1, 20(sp) # 4-byte Folded Reload295; RV32IZFINXZDINXZILSD-NEXT: addi sp, sp, 32296; RV32IZFINXZDINXZILSD-NEXT: ret297 %1 = alloca double, align 8298 call void @notdead(ptr %1)299 %2 = load double, ptr %1300 %3 = fadd double %2, %a ; force load in to FPR64301 ret double %3302}303 304define dso_local void @fsd_stack(double %a, double %b) nounwind {305; RV32IFD-LABEL: fsd_stack:306; RV32IFD: # %bb.0:307; RV32IFD-NEXT: addi sp, sp, -16308; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill309; RV32IFD-NEXT: fadd.d fa5, fa0, fa1310; RV32IFD-NEXT: fsd fa5, 0(sp)311; RV32IFD-NEXT: mv a0, sp312; RV32IFD-NEXT: call notdead313; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload314; RV32IFD-NEXT: addi sp, sp, 16315; RV32IFD-NEXT: ret316;317; RV64IFD-LABEL: fsd_stack:318; RV64IFD: # %bb.0:319; RV64IFD-NEXT: addi sp, sp, -16320; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill321; RV64IFD-NEXT: fadd.d fa5, fa0, fa1322; RV64IFD-NEXT: fsd fa5, 0(sp)323; RV64IFD-NEXT: mv a0, sp324; RV64IFD-NEXT: call notdead325; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload326; RV64IFD-NEXT: addi sp, sp, 16327; RV64IFD-NEXT: ret328;329; RV32IZFINXZDINX-LABEL: fsd_stack:330; RV32IZFINXZDINX: # %bb.0:331; RV32IZFINXZDINX-NEXT: addi sp, sp, -16332; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill333; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2334; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)335; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)336; RV32IZFINXZDINX-NEXT: mv a0, sp337; RV32IZFINXZDINX-NEXT: call notdead338; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload339; RV32IZFINXZDINX-NEXT: addi sp, sp, 16340; RV32IZFINXZDINX-NEXT: ret341;342; RV64IZFINXZDINX-LABEL: fsd_stack:343; RV64IZFINXZDINX: # %bb.0:344; RV64IZFINXZDINX-NEXT: addi sp, sp, -16345; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill346; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1347; RV64IZFINXZDINX-NEXT: sd a0, 0(sp)348; RV64IZFINXZDINX-NEXT: mv a0, sp349; RV64IZFINXZDINX-NEXT: call notdead350; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload351; RV64IZFINXZDINX-NEXT: addi sp, sp, 16352; RV64IZFINXZDINX-NEXT: ret353;354; RV32IZFINXZDINXZILSD-LABEL: fsd_stack:355; RV32IZFINXZDINXZILSD: # %bb.0:356; RV32IZFINXZDINXZILSD-NEXT: addi sp, sp, -16357; RV32IZFINXZDINXZILSD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill358; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2359; RV32IZFINXZDINXZILSD-NEXT: sd a0, 0(sp)360; RV32IZFINXZDINXZILSD-NEXT: mv a0, sp361; RV32IZFINXZDINXZILSD-NEXT: call notdead362; RV32IZFINXZDINXZILSD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload363; RV32IZFINXZDINXZILSD-NEXT: addi sp, sp, 16364; RV32IZFINXZDINXZILSD-NEXT: ret365 %1 = fadd double %a, %b ; force store from FPR64366 %2 = alloca double, align 8367 store double %1, ptr %2368 call void @notdead(ptr %2)369 ret void370}371 372; Test selection of store<ST4[%a], trunc to f32>, ..373define dso_local void @fsd_trunc(ptr %a, double %b) nounwind noinline optnone {374; CHECKIFD-LABEL: fsd_trunc:375; CHECKIFD: # %bb.0:376; CHECKIFD-NEXT: fcvt.s.d fa5, fa0377; CHECKIFD-NEXT: fsw fa5, 0(a0)378; CHECKIFD-NEXT: ret379;380; RV32IZFINXZDINX-LABEL: fsd_trunc:381; RV32IZFINXZDINX: # %bb.0:382; RV32IZFINXZDINX-NEXT: mv a3, a2383; RV32IZFINXZDINX-NEXT: mv a2, a1384; RV32IZFINXZDINX-NEXT: fcvt.s.d a1, a2385; RV32IZFINXZDINX-NEXT: sw a1, 0(a0)386; RV32IZFINXZDINX-NEXT: ret387;388; RV64IZFINXZDINX-LABEL: fsd_trunc:389; RV64IZFINXZDINX: # %bb.0:390; RV64IZFINXZDINX-NEXT: fcvt.s.d a1, a1391; RV64IZFINXZDINX-NEXT: sw a1, 0(a0)392; RV64IZFINXZDINX-NEXT: ret393;394; RV32IZFINXZDINXZILSD-LABEL: fsd_trunc:395; RV32IZFINXZDINXZILSD: # %bb.0:396; RV32IZFINXZDINXZILSD-NEXT: mv a3, a2397; RV32IZFINXZDINXZILSD-NEXT: mv a2, a1398; RV32IZFINXZDINXZILSD-NEXT: fcvt.s.d a1, a2399; RV32IZFINXZDINXZILSD-NEXT: sw a1, 0(a0)400; RV32IZFINXZDINXZILSD-NEXT: ret401 %1 = fptrunc double %b to float402 store float %1, ptr %a, align 4403 ret void404}405 406define dso_local void @store_zero(ptr %a) {407; RV32IFD-LABEL: store_zero:408; RV32IFD: # %bb.0:409; RV32IFD-NEXT: fcvt.d.w fa5, zero410; RV32IFD-NEXT: fsd fa5, 0(a0)411; RV32IFD-NEXT: ret412;413; RV64IFD-LABEL: store_zero:414; RV64IFD: # %bb.0:415; RV64IFD-NEXT: sd zero, 0(a0)416; RV64IFD-NEXT: ret417;418; RV32IZFINXZDINX-LABEL: store_zero:419; RV32IZFINXZDINX: # %bb.0:420; RV32IZFINXZDINX-NEXT: sw zero, 0(a0)421; RV32IZFINXZDINX-NEXT: sw zero, 4(a0)422; RV32IZFINXZDINX-NEXT: ret423;424; RV64IZFINXZDINX-LABEL: store_zero:425; RV64IZFINXZDINX: # %bb.0:426; RV64IZFINXZDINX-NEXT: sd zero, 0(a0)427; RV64IZFINXZDINX-NEXT: ret428;429; RV32IZFINXZDINXZILSD-LABEL: store_zero:430; RV32IZFINXZDINXZILSD: # %bb.0:431; RV32IZFINXZDINXZILSD-NEXT: sd zero, 0(a0)432; RV32IZFINXZDINXZILSD-NEXT: ret433 store double 0.0, ptr %a434 ret void435}436