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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \5; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s6; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \7; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32IZFINXZDINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \9; RUN: -target-abi=lp64 | FileCheck -check-prefixes=RV64IZFINXZDINX %s10 11define signext i8 @test_floor_si8(double %x) {12; RV32IFD-LABEL: test_floor_si8:13; RV32IFD: # %bb.0:14; RV32IFD-NEXT: fcvt.w.d a0, fa0, rdn15; RV32IFD-NEXT: ret16;17; RV64IFD-LABEL: test_floor_si8:18; RV64IFD: # %bb.0:19; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn20; RV64IFD-NEXT: ret21;22; RV32IZFINXZDINX-LABEL: test_floor_si8:23; RV32IZFINXZDINX: # %bb.0:24; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rdn25; RV32IZFINXZDINX-NEXT: ret26;27; RV64IZFINXZDINX-LABEL: test_floor_si8:28; RV64IZFINXZDINX: # %bb.0:29; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rdn30; RV64IZFINXZDINX-NEXT: ret31 %a = call double @llvm.floor.f64(double %x)32 %b = fptosi double %a to i833 ret i8 %b34}35 36define signext i16 @test_floor_si16(double %x) {37; RV32IFD-LABEL: test_floor_si16:38; RV32IFD: # %bb.0:39; RV32IFD-NEXT: fcvt.w.d a0, fa0, rdn40; RV32IFD-NEXT: ret41;42; RV64IFD-LABEL: test_floor_si16:43; RV64IFD: # %bb.0:44; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn45; RV64IFD-NEXT: ret46;47; RV32IZFINXZDINX-LABEL: test_floor_si16:48; RV32IZFINXZDINX: # %bb.0:49; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rdn50; RV32IZFINXZDINX-NEXT: ret51;52; RV64IZFINXZDINX-LABEL: test_floor_si16:53; RV64IZFINXZDINX: # %bb.0:54; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rdn55; RV64IZFINXZDINX-NEXT: ret56 %a = call double @llvm.floor.f64(double %x)57 %b = fptosi double %a to i1658 ret i16 %b59}60 61define signext i32 @test_floor_si32(double %x) {62; CHECKIFD-LABEL: test_floor_si32:63; CHECKIFD: # %bb.0:64; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rdn65; CHECKIFD-NEXT: ret66;67; RV32IZFINXZDINX-LABEL: test_floor_si32:68; RV32IZFINXZDINX: # %bb.0:69; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rdn70; RV32IZFINXZDINX-NEXT: ret71;72; RV64IZFINXZDINX-LABEL: test_floor_si32:73; RV64IZFINXZDINX: # %bb.0:74; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rdn75; RV64IZFINXZDINX-NEXT: ret76 %a = call double @llvm.floor.f64(double %x)77 %b = fptosi double %a to i3278 ret i32 %b79}80 81define i64 @test_floor_si64(double %x) {82; RV32IFD-LABEL: test_floor_si64:83; RV32IFD: # %bb.0:84; RV32IFD-NEXT: addi sp, sp, -1685; RV32IFD-NEXT: .cfi_def_cfa_offset 1686; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill87; RV32IFD-NEXT: .cfi_offset ra, -488; RV32IFD-NEXT: call floor89; RV32IFD-NEXT: call __fixdfdi90; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload91; RV32IFD-NEXT: .cfi_restore ra92; RV32IFD-NEXT: addi sp, sp, 1693; RV32IFD-NEXT: .cfi_def_cfa_offset 094; RV32IFD-NEXT: ret95;96; RV64IFD-LABEL: test_floor_si64:97; RV64IFD: # %bb.0:98; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn99; RV64IFD-NEXT: ret100;101; RV32IZFINXZDINX-LABEL: test_floor_si64:102; RV32IZFINXZDINX: # %bb.0:103; RV32IZFINXZDINX-NEXT: addi sp, sp, -16104; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16105; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill106; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4107; RV32IZFINXZDINX-NEXT: call floor108; RV32IZFINXZDINX-NEXT: call __fixdfdi109; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload110; RV32IZFINXZDINX-NEXT: .cfi_restore ra111; RV32IZFINXZDINX-NEXT: addi sp, sp, 16112; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0113; RV32IZFINXZDINX-NEXT: ret114;115; RV64IZFINXZDINX-LABEL: test_floor_si64:116; RV64IZFINXZDINX: # %bb.0:117; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rdn118; RV64IZFINXZDINX-NEXT: ret119 %a = call double @llvm.floor.f64(double %x)120 %b = fptosi double %a to i64121 ret i64 %b122}123 124define zeroext i8 @test_floor_ui8(double %x) {125; RV32IFD-LABEL: test_floor_ui8:126; RV32IFD: # %bb.0:127; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn128; RV32IFD-NEXT: ret129;130; RV64IFD-LABEL: test_floor_ui8:131; RV64IFD: # %bb.0:132; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rdn133; RV64IFD-NEXT: ret134;135; RV32IZFINXZDINX-LABEL: test_floor_ui8:136; RV32IZFINXZDINX: # %bb.0:137; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rdn138; RV32IZFINXZDINX-NEXT: ret139;140; RV64IZFINXZDINX-LABEL: test_floor_ui8:141; RV64IZFINXZDINX: # %bb.0:142; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rdn143; RV64IZFINXZDINX-NEXT: ret144 %a = call double @llvm.floor.f64(double %x)145 %b = fptoui double %a to i8146 ret i8 %b147}148 149define zeroext i16 @test_floor_ui16(double %x) {150; RV32IFD-LABEL: test_floor_ui16:151; RV32IFD: # %bb.0:152; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn153; RV32IFD-NEXT: ret154;155; RV64IFD-LABEL: test_floor_ui16:156; RV64IFD: # %bb.0:157; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rdn158; RV64IFD-NEXT: ret159;160; RV32IZFINXZDINX-LABEL: test_floor_ui16:161; RV32IZFINXZDINX: # %bb.0:162; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rdn163; RV32IZFINXZDINX-NEXT: ret164;165; RV64IZFINXZDINX-LABEL: test_floor_ui16:166; RV64IZFINXZDINX: # %bb.0:167; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rdn168; RV64IZFINXZDINX-NEXT: ret169 %a = call double @llvm.floor.f64(double %x)170 %b = fptoui double %a to i16171 ret i16 %b172}173 174define signext i32 @test_floor_ui32(double %x) {175; CHECKIFD-LABEL: test_floor_ui32:176; CHECKIFD: # %bb.0:177; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rdn178; CHECKIFD-NEXT: ret179;180; RV32IZFINXZDINX-LABEL: test_floor_ui32:181; RV32IZFINXZDINX: # %bb.0:182; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rdn183; RV32IZFINXZDINX-NEXT: ret184;185; RV64IZFINXZDINX-LABEL: test_floor_ui32:186; RV64IZFINXZDINX: # %bb.0:187; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rdn188; RV64IZFINXZDINX-NEXT: ret189 %a = call double @llvm.floor.f64(double %x)190 %b = fptoui double %a to i32191 ret i32 %b192}193 194define i64 @test_floor_ui64(double %x) {195; RV32IFD-LABEL: test_floor_ui64:196; RV32IFD: # %bb.0:197; RV32IFD-NEXT: addi sp, sp, -16198; RV32IFD-NEXT: .cfi_def_cfa_offset 16199; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill200; RV32IFD-NEXT: .cfi_offset ra, -4201; RV32IFD-NEXT: call floor202; RV32IFD-NEXT: call __fixunsdfdi203; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload204; RV32IFD-NEXT: .cfi_restore ra205; RV32IFD-NEXT: addi sp, sp, 16206; RV32IFD-NEXT: .cfi_def_cfa_offset 0207; RV32IFD-NEXT: ret208;209; RV64IFD-LABEL: test_floor_ui64:210; RV64IFD: # %bb.0:211; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rdn212; RV64IFD-NEXT: ret213;214; RV32IZFINXZDINX-LABEL: test_floor_ui64:215; RV32IZFINXZDINX: # %bb.0:216; RV32IZFINXZDINX-NEXT: addi sp, sp, -16217; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16218; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill219; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4220; RV32IZFINXZDINX-NEXT: call floor221; RV32IZFINXZDINX-NEXT: call __fixunsdfdi222; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload223; RV32IZFINXZDINX-NEXT: .cfi_restore ra224; RV32IZFINXZDINX-NEXT: addi sp, sp, 16225; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0226; RV32IZFINXZDINX-NEXT: ret227;228; RV64IZFINXZDINX-LABEL: test_floor_ui64:229; RV64IZFINXZDINX: # %bb.0:230; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rdn231; RV64IZFINXZDINX-NEXT: ret232 %a = call double @llvm.floor.f64(double %x)233 %b = fptoui double %a to i64234 ret i64 %b235}236 237define signext i8 @test_ceil_si8(double %x) {238; RV32IFD-LABEL: test_ceil_si8:239; RV32IFD: # %bb.0:240; RV32IFD-NEXT: fcvt.w.d a0, fa0, rup241; RV32IFD-NEXT: ret242;243; RV64IFD-LABEL: test_ceil_si8:244; RV64IFD: # %bb.0:245; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup246; RV64IFD-NEXT: ret247;248; RV32IZFINXZDINX-LABEL: test_ceil_si8:249; RV32IZFINXZDINX: # %bb.0:250; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rup251; RV32IZFINXZDINX-NEXT: ret252;253; RV64IZFINXZDINX-LABEL: test_ceil_si8:254; RV64IZFINXZDINX: # %bb.0:255; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rup256; RV64IZFINXZDINX-NEXT: ret257 %a = call double @llvm.ceil.f64(double %x)258 %b = fptosi double %a to i8259 ret i8 %b260}261 262define signext i16 @test_ceil_si16(double %x) {263; RV32IFD-LABEL: test_ceil_si16:264; RV32IFD: # %bb.0:265; RV32IFD-NEXT: fcvt.w.d a0, fa0, rup266; RV32IFD-NEXT: ret267;268; RV64IFD-LABEL: test_ceil_si16:269; RV64IFD: # %bb.0:270; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup271; RV64IFD-NEXT: ret272;273; RV32IZFINXZDINX-LABEL: test_ceil_si16:274; RV32IZFINXZDINX: # %bb.0:275; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rup276; RV32IZFINXZDINX-NEXT: ret277;278; RV64IZFINXZDINX-LABEL: test_ceil_si16:279; RV64IZFINXZDINX: # %bb.0:280; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rup281; RV64IZFINXZDINX-NEXT: ret282 %a = call double @llvm.ceil.f64(double %x)283 %b = fptosi double %a to i16284 ret i16 %b285}286 287define signext i32 @test_ceil_si32(double %x) {288; CHECKIFD-LABEL: test_ceil_si32:289; CHECKIFD: # %bb.0:290; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rup291; CHECKIFD-NEXT: ret292;293; RV32IZFINXZDINX-LABEL: test_ceil_si32:294; RV32IZFINXZDINX: # %bb.0:295; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rup296; RV32IZFINXZDINX-NEXT: ret297;298; RV64IZFINXZDINX-LABEL: test_ceil_si32:299; RV64IZFINXZDINX: # %bb.0:300; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rup301; RV64IZFINXZDINX-NEXT: ret302 %a = call double @llvm.ceil.f64(double %x)303 %b = fptosi double %a to i32304 ret i32 %b305}306 307define i64 @test_ceil_si64(double %x) {308; RV32IFD-LABEL: test_ceil_si64:309; RV32IFD: # %bb.0:310; RV32IFD-NEXT: addi sp, sp, -16311; RV32IFD-NEXT: .cfi_def_cfa_offset 16312; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill313; RV32IFD-NEXT: .cfi_offset ra, -4314; RV32IFD-NEXT: call ceil315; RV32IFD-NEXT: call __fixdfdi316; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload317; RV32IFD-NEXT: .cfi_restore ra318; RV32IFD-NEXT: addi sp, sp, 16319; RV32IFD-NEXT: .cfi_def_cfa_offset 0320; RV32IFD-NEXT: ret321;322; RV64IFD-LABEL: test_ceil_si64:323; RV64IFD: # %bb.0:324; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup325; RV64IFD-NEXT: ret326;327; RV32IZFINXZDINX-LABEL: test_ceil_si64:328; RV32IZFINXZDINX: # %bb.0:329; RV32IZFINXZDINX-NEXT: addi sp, sp, -16330; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16331; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill332; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4333; RV32IZFINXZDINX-NEXT: call ceil334; RV32IZFINXZDINX-NEXT: call __fixdfdi335; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload336; RV32IZFINXZDINX-NEXT: .cfi_restore ra337; RV32IZFINXZDINX-NEXT: addi sp, sp, 16338; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0339; RV32IZFINXZDINX-NEXT: ret340;341; RV64IZFINXZDINX-LABEL: test_ceil_si64:342; RV64IZFINXZDINX: # %bb.0:343; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rup344; RV64IZFINXZDINX-NEXT: ret345 %a = call double @llvm.ceil.f64(double %x)346 %b = fptosi double %a to i64347 ret i64 %b348}349 350define zeroext i8 @test_ceil_ui8(double %x) {351; RV32IFD-LABEL: test_ceil_ui8:352; RV32IFD: # %bb.0:353; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rup354; RV32IFD-NEXT: ret355;356; RV64IFD-LABEL: test_ceil_ui8:357; RV64IFD: # %bb.0:358; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rup359; RV64IFD-NEXT: ret360;361; RV32IZFINXZDINX-LABEL: test_ceil_ui8:362; RV32IZFINXZDINX: # %bb.0:363; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rup364; RV32IZFINXZDINX-NEXT: ret365;366; RV64IZFINXZDINX-LABEL: test_ceil_ui8:367; RV64IZFINXZDINX: # %bb.0:368; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rup369; RV64IZFINXZDINX-NEXT: ret370 %a = call double @llvm.ceil.f64(double %x)371 %b = fptoui double %a to i8372 ret i8 %b373}374 375define zeroext i16 @test_ceil_ui16(double %x) {376; RV32IFD-LABEL: test_ceil_ui16:377; RV32IFD: # %bb.0:378; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rup379; RV32IFD-NEXT: ret380;381; RV64IFD-LABEL: test_ceil_ui16:382; RV64IFD: # %bb.0:383; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rup384; RV64IFD-NEXT: ret385;386; RV32IZFINXZDINX-LABEL: test_ceil_ui16:387; RV32IZFINXZDINX: # %bb.0:388; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rup389; RV32IZFINXZDINX-NEXT: ret390;391; RV64IZFINXZDINX-LABEL: test_ceil_ui16:392; RV64IZFINXZDINX: # %bb.0:393; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rup394; RV64IZFINXZDINX-NEXT: ret395 %a = call double @llvm.ceil.f64(double %x)396 %b = fptoui double %a to i16397 ret i16 %b398}399 400define signext i32 @test_ceil_ui32(double %x) {401; CHECKIFD-LABEL: test_ceil_ui32:402; CHECKIFD: # %bb.0:403; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rup404; CHECKIFD-NEXT: ret405;406; RV32IZFINXZDINX-LABEL: test_ceil_ui32:407; RV32IZFINXZDINX: # %bb.0:408; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rup409; RV32IZFINXZDINX-NEXT: ret410;411; RV64IZFINXZDINX-LABEL: test_ceil_ui32:412; RV64IZFINXZDINX: # %bb.0:413; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rup414; RV64IZFINXZDINX-NEXT: ret415 %a = call double @llvm.ceil.f64(double %x)416 %b = fptoui double %a to i32417 ret i32 %b418}419 420define i64 @test_ceil_ui64(double %x) {421; RV32IFD-LABEL: test_ceil_ui64:422; RV32IFD: # %bb.0:423; RV32IFD-NEXT: addi sp, sp, -16424; RV32IFD-NEXT: .cfi_def_cfa_offset 16425; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill426; RV32IFD-NEXT: .cfi_offset ra, -4427; RV32IFD-NEXT: call ceil428; RV32IFD-NEXT: call __fixunsdfdi429; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload430; RV32IFD-NEXT: .cfi_restore ra431; RV32IFD-NEXT: addi sp, sp, 16432; RV32IFD-NEXT: .cfi_def_cfa_offset 0433; RV32IFD-NEXT: ret434;435; RV64IFD-LABEL: test_ceil_ui64:436; RV64IFD: # %bb.0:437; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rup438; RV64IFD-NEXT: ret439;440; RV32IZFINXZDINX-LABEL: test_ceil_ui64:441; RV32IZFINXZDINX: # %bb.0:442; RV32IZFINXZDINX-NEXT: addi sp, sp, -16443; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16444; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill445; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4446; RV32IZFINXZDINX-NEXT: call ceil447; RV32IZFINXZDINX-NEXT: call __fixunsdfdi448; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload449; RV32IZFINXZDINX-NEXT: .cfi_restore ra450; RV32IZFINXZDINX-NEXT: addi sp, sp, 16451; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0452; RV32IZFINXZDINX-NEXT: ret453;454; RV64IZFINXZDINX-LABEL: test_ceil_ui64:455; RV64IZFINXZDINX: # %bb.0:456; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rup457; RV64IZFINXZDINX-NEXT: ret458 %a = call double @llvm.ceil.f64(double %x)459 %b = fptoui double %a to i64460 ret i64 %b461}462 463define signext i8 @test_trunc_si8(double %x) {464; RV32IFD-LABEL: test_trunc_si8:465; RV32IFD: # %bb.0:466; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz467; RV32IFD-NEXT: ret468;469; RV64IFD-LABEL: test_trunc_si8:470; RV64IFD: # %bb.0:471; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz472; RV64IFD-NEXT: ret473;474; RV32IZFINXZDINX-LABEL: test_trunc_si8:475; RV32IZFINXZDINX: # %bb.0:476; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz477; RV32IZFINXZDINX-NEXT: ret478;479; RV64IZFINXZDINX-LABEL: test_trunc_si8:480; RV64IZFINXZDINX: # %bb.0:481; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz482; RV64IZFINXZDINX-NEXT: ret483 %a = call double @llvm.trunc.f64(double %x)484 %b = fptosi double %a to i8485 ret i8 %b486}487 488define signext i16 @test_trunc_si16(double %x) {489; RV32IFD-LABEL: test_trunc_si16:490; RV32IFD: # %bb.0:491; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz492; RV32IFD-NEXT: ret493;494; RV64IFD-LABEL: test_trunc_si16:495; RV64IFD: # %bb.0:496; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz497; RV64IFD-NEXT: ret498;499; RV32IZFINXZDINX-LABEL: test_trunc_si16:500; RV32IZFINXZDINX: # %bb.0:501; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz502; RV32IZFINXZDINX-NEXT: ret503;504; RV64IZFINXZDINX-LABEL: test_trunc_si16:505; RV64IZFINXZDINX: # %bb.0:506; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz507; RV64IZFINXZDINX-NEXT: ret508 %a = call double @llvm.trunc.f64(double %x)509 %b = fptosi double %a to i16510 ret i16 %b511}512 513define signext i32 @test_trunc_si32(double %x) {514; CHECKIFD-LABEL: test_trunc_si32:515; CHECKIFD: # %bb.0:516; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz517; CHECKIFD-NEXT: ret518;519; RV32IZFINXZDINX-LABEL: test_trunc_si32:520; RV32IZFINXZDINX: # %bb.0:521; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz522; RV32IZFINXZDINX-NEXT: ret523;524; RV64IZFINXZDINX-LABEL: test_trunc_si32:525; RV64IZFINXZDINX: # %bb.0:526; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz527; RV64IZFINXZDINX-NEXT: ret528 %a = call double @llvm.trunc.f64(double %x)529 %b = fptosi double %a to i32530 ret i32 %b531}532 533define i64 @test_trunc_si64(double %x) {534; RV32IFD-LABEL: test_trunc_si64:535; RV32IFD: # %bb.0:536; RV32IFD-NEXT: addi sp, sp, -16537; RV32IFD-NEXT: .cfi_def_cfa_offset 16538; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill539; RV32IFD-NEXT: .cfi_offset ra, -4540; RV32IFD-NEXT: call trunc541; RV32IFD-NEXT: call __fixdfdi542; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload543; RV32IFD-NEXT: .cfi_restore ra544; RV32IFD-NEXT: addi sp, sp, 16545; RV32IFD-NEXT: .cfi_def_cfa_offset 0546; RV32IFD-NEXT: ret547;548; RV64IFD-LABEL: test_trunc_si64:549; RV64IFD: # %bb.0:550; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz551; RV64IFD-NEXT: ret552;553; RV32IZFINXZDINX-LABEL: test_trunc_si64:554; RV32IZFINXZDINX: # %bb.0:555; RV32IZFINXZDINX-NEXT: addi sp, sp, -16556; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16557; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill558; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4559; RV32IZFINXZDINX-NEXT: call trunc560; RV32IZFINXZDINX-NEXT: call __fixdfdi561; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload562; RV32IZFINXZDINX-NEXT: .cfi_restore ra563; RV32IZFINXZDINX-NEXT: addi sp, sp, 16564; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0565; RV32IZFINXZDINX-NEXT: ret566;567; RV64IZFINXZDINX-LABEL: test_trunc_si64:568; RV64IZFINXZDINX: # %bb.0:569; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz570; RV64IZFINXZDINX-NEXT: ret571 %a = call double @llvm.trunc.f64(double %x)572 %b = fptosi double %a to i64573 ret i64 %b574}575 576define zeroext i8 @test_trunc_ui8(double %x) {577; RV32IFD-LABEL: test_trunc_ui8:578; RV32IFD: # %bb.0:579; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz580; RV32IFD-NEXT: ret581;582; RV64IFD-LABEL: test_trunc_ui8:583; RV64IFD: # %bb.0:584; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz585; RV64IFD-NEXT: ret586;587; RV32IZFINXZDINX-LABEL: test_trunc_ui8:588; RV32IZFINXZDINX: # %bb.0:589; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz590; RV32IZFINXZDINX-NEXT: ret591;592; RV64IZFINXZDINX-LABEL: test_trunc_ui8:593; RV64IZFINXZDINX: # %bb.0:594; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz595; RV64IZFINXZDINX-NEXT: ret596 %a = call double @llvm.trunc.f64(double %x)597 %b = fptoui double %a to i8598 ret i8 %b599}600 601define zeroext i16 @test_trunc_ui16(double %x) {602; RV32IFD-LABEL: test_trunc_ui16:603; RV32IFD: # %bb.0:604; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz605; RV32IFD-NEXT: ret606;607; RV64IFD-LABEL: test_trunc_ui16:608; RV64IFD: # %bb.0:609; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz610; RV64IFD-NEXT: ret611;612; RV32IZFINXZDINX-LABEL: test_trunc_ui16:613; RV32IZFINXZDINX: # %bb.0:614; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz615; RV32IZFINXZDINX-NEXT: ret616;617; RV64IZFINXZDINX-LABEL: test_trunc_ui16:618; RV64IZFINXZDINX: # %bb.0:619; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz620; RV64IZFINXZDINX-NEXT: ret621 %a = call double @llvm.trunc.f64(double %x)622 %b = fptoui double %a to i16623 ret i16 %b624}625 626define signext i32 @test_trunc_ui32(double %x) {627; CHECKIFD-LABEL: test_trunc_ui32:628; CHECKIFD: # %bb.0:629; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz630; CHECKIFD-NEXT: ret631;632; RV32IZFINXZDINX-LABEL: test_trunc_ui32:633; RV32IZFINXZDINX: # %bb.0:634; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz635; RV32IZFINXZDINX-NEXT: ret636;637; RV64IZFINXZDINX-LABEL: test_trunc_ui32:638; RV64IZFINXZDINX: # %bb.0:639; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz640; RV64IZFINXZDINX-NEXT: ret641 %a = call double @llvm.trunc.f64(double %x)642 %b = fptoui double %a to i32643 ret i32 %b644}645 646define i64 @test_trunc_ui64(double %x) {647; RV32IFD-LABEL: test_trunc_ui64:648; RV32IFD: # %bb.0:649; RV32IFD-NEXT: addi sp, sp, -16650; RV32IFD-NEXT: .cfi_def_cfa_offset 16651; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill652; RV32IFD-NEXT: .cfi_offset ra, -4653; RV32IFD-NEXT: call trunc654; RV32IFD-NEXT: call __fixunsdfdi655; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload656; RV32IFD-NEXT: .cfi_restore ra657; RV32IFD-NEXT: addi sp, sp, 16658; RV32IFD-NEXT: .cfi_def_cfa_offset 0659; RV32IFD-NEXT: ret660;661; RV64IFD-LABEL: test_trunc_ui64:662; RV64IFD: # %bb.0:663; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz664; RV64IFD-NEXT: ret665;666; RV32IZFINXZDINX-LABEL: test_trunc_ui64:667; RV32IZFINXZDINX: # %bb.0:668; RV32IZFINXZDINX-NEXT: addi sp, sp, -16669; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16670; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill671; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4672; RV32IZFINXZDINX-NEXT: call trunc673; RV32IZFINXZDINX-NEXT: call __fixunsdfdi674; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload675; RV32IZFINXZDINX-NEXT: .cfi_restore ra676; RV32IZFINXZDINX-NEXT: addi sp, sp, 16677; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0678; RV32IZFINXZDINX-NEXT: ret679;680; RV64IZFINXZDINX-LABEL: test_trunc_ui64:681; RV64IZFINXZDINX: # %bb.0:682; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz683; RV64IZFINXZDINX-NEXT: ret684 %a = call double @llvm.trunc.f64(double %x)685 %b = fptoui double %a to i64686 ret i64 %b687}688 689define signext i8 @test_round_si8(double %x) {690; RV32IFD-LABEL: test_round_si8:691; RV32IFD: # %bb.0:692; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm693; RV32IFD-NEXT: ret694;695; RV64IFD-LABEL: test_round_si8:696; RV64IFD: # %bb.0:697; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm698; RV64IFD-NEXT: ret699;700; RV32IZFINXZDINX-LABEL: test_round_si8:701; RV32IZFINXZDINX: # %bb.0:702; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm703; RV32IZFINXZDINX-NEXT: ret704;705; RV64IZFINXZDINX-LABEL: test_round_si8:706; RV64IZFINXZDINX: # %bb.0:707; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm708; RV64IZFINXZDINX-NEXT: ret709 %a = call double @llvm.round.f64(double %x)710 %b = fptosi double %a to i8711 ret i8 %b712}713 714define signext i16 @test_round_si16(double %x) {715; RV32IFD-LABEL: test_round_si16:716; RV32IFD: # %bb.0:717; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm718; RV32IFD-NEXT: ret719;720; RV64IFD-LABEL: test_round_si16:721; RV64IFD: # %bb.0:722; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm723; RV64IFD-NEXT: ret724;725; RV32IZFINXZDINX-LABEL: test_round_si16:726; RV32IZFINXZDINX: # %bb.0:727; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm728; RV32IZFINXZDINX-NEXT: ret729;730; RV64IZFINXZDINX-LABEL: test_round_si16:731; RV64IZFINXZDINX: # %bb.0:732; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm733; RV64IZFINXZDINX-NEXT: ret734 %a = call double @llvm.round.f64(double %x)735 %b = fptosi double %a to i16736 ret i16 %b737}738 739define signext i32 @test_round_si32(double %x) {740; CHECKIFD-LABEL: test_round_si32:741; CHECKIFD: # %bb.0:742; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rmm743; CHECKIFD-NEXT: ret744;745; RV32IZFINXZDINX-LABEL: test_round_si32:746; RV32IZFINXZDINX: # %bb.0:747; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm748; RV32IZFINXZDINX-NEXT: ret749;750; RV64IZFINXZDINX-LABEL: test_round_si32:751; RV64IZFINXZDINX: # %bb.0:752; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm753; RV64IZFINXZDINX-NEXT: ret754 %a = call double @llvm.round.f64(double %x)755 %b = fptosi double %a to i32756 ret i32 %b757}758 759define i64 @test_round_si64(double %x) {760; RV32IFD-LABEL: test_round_si64:761; RV32IFD: # %bb.0:762; RV32IFD-NEXT: addi sp, sp, -16763; RV32IFD-NEXT: .cfi_def_cfa_offset 16764; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill765; RV32IFD-NEXT: .cfi_offset ra, -4766; RV32IFD-NEXT: call round767; RV32IFD-NEXT: call __fixdfdi768; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload769; RV32IFD-NEXT: .cfi_restore ra770; RV32IFD-NEXT: addi sp, sp, 16771; RV32IFD-NEXT: .cfi_def_cfa_offset 0772; RV32IFD-NEXT: ret773;774; RV64IFD-LABEL: test_round_si64:775; RV64IFD: # %bb.0:776; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm777; RV64IFD-NEXT: ret778;779; RV32IZFINXZDINX-LABEL: test_round_si64:780; RV32IZFINXZDINX: # %bb.0:781; RV32IZFINXZDINX-NEXT: addi sp, sp, -16782; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16783; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill784; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4785; RV32IZFINXZDINX-NEXT: call round786; RV32IZFINXZDINX-NEXT: call __fixdfdi787; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload788; RV32IZFINXZDINX-NEXT: .cfi_restore ra789; RV32IZFINXZDINX-NEXT: addi sp, sp, 16790; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0791; RV32IZFINXZDINX-NEXT: ret792;793; RV64IZFINXZDINX-LABEL: test_round_si64:794; RV64IZFINXZDINX: # %bb.0:795; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rmm796; RV64IZFINXZDINX-NEXT: ret797 %a = call double @llvm.round.f64(double %x)798 %b = fptosi double %a to i64799 ret i64 %b800}801 802define zeroext i8 @test_round_ui8(double %x) {803; RV32IFD-LABEL: test_round_ui8:804; RV32IFD: # %bb.0:805; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rmm806; RV32IFD-NEXT: ret807;808; RV64IFD-LABEL: test_round_ui8:809; RV64IFD: # %bb.0:810; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rmm811; RV64IFD-NEXT: ret812;813; RV32IZFINXZDINX-LABEL: test_round_ui8:814; RV32IZFINXZDINX: # %bb.0:815; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rmm816; RV32IZFINXZDINX-NEXT: ret817;818; RV64IZFINXZDINX-LABEL: test_round_ui8:819; RV64IZFINXZDINX: # %bb.0:820; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rmm821; RV64IZFINXZDINX-NEXT: ret822 %a = call double @llvm.round.f64(double %x)823 %b = fptoui double %a to i8824 ret i8 %b825}826 827define zeroext i16 @test_round_ui16(double %x) {828; RV32IFD-LABEL: test_round_ui16:829; RV32IFD: # %bb.0:830; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rmm831; RV32IFD-NEXT: ret832;833; RV64IFD-LABEL: test_round_ui16:834; RV64IFD: # %bb.0:835; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rmm836; RV64IFD-NEXT: ret837;838; RV32IZFINXZDINX-LABEL: test_round_ui16:839; RV32IZFINXZDINX: # %bb.0:840; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rmm841; RV32IZFINXZDINX-NEXT: ret842;843; RV64IZFINXZDINX-LABEL: test_round_ui16:844; RV64IZFINXZDINX: # %bb.0:845; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rmm846; RV64IZFINXZDINX-NEXT: ret847 %a = call double @llvm.round.f64(double %x)848 %b = fptoui double %a to i16849 ret i16 %b850}851 852define signext i32 @test_round_ui32(double %x) {853; CHECKIFD-LABEL: test_round_ui32:854; CHECKIFD: # %bb.0:855; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rmm856; CHECKIFD-NEXT: ret857;858; RV32IZFINXZDINX-LABEL: test_round_ui32:859; RV32IZFINXZDINX: # %bb.0:860; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rmm861; RV32IZFINXZDINX-NEXT: ret862;863; RV64IZFINXZDINX-LABEL: test_round_ui32:864; RV64IZFINXZDINX: # %bb.0:865; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rmm866; RV64IZFINXZDINX-NEXT: ret867 %a = call double @llvm.round.f64(double %x)868 %b = fptoui double %a to i32869 ret i32 %b870}871 872define i64 @test_round_ui64(double %x) {873; RV32IFD-LABEL: test_round_ui64:874; RV32IFD: # %bb.0:875; RV32IFD-NEXT: addi sp, sp, -16876; RV32IFD-NEXT: .cfi_def_cfa_offset 16877; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill878; RV32IFD-NEXT: .cfi_offset ra, -4879; RV32IFD-NEXT: call round880; RV32IFD-NEXT: call __fixunsdfdi881; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload882; RV32IFD-NEXT: .cfi_restore ra883; RV32IFD-NEXT: addi sp, sp, 16884; RV32IFD-NEXT: .cfi_def_cfa_offset 0885; RV32IFD-NEXT: ret886;887; RV64IFD-LABEL: test_round_ui64:888; RV64IFD: # %bb.0:889; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rmm890; RV64IFD-NEXT: ret891;892; RV32IZFINXZDINX-LABEL: test_round_ui64:893; RV32IZFINXZDINX: # %bb.0:894; RV32IZFINXZDINX-NEXT: addi sp, sp, -16895; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16896; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill897; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4898; RV32IZFINXZDINX-NEXT: call round899; RV32IZFINXZDINX-NEXT: call __fixunsdfdi900; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload901; RV32IZFINXZDINX-NEXT: .cfi_restore ra902; RV32IZFINXZDINX-NEXT: addi sp, sp, 16903; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0904; RV32IZFINXZDINX-NEXT: ret905;906; RV64IZFINXZDINX-LABEL: test_round_ui64:907; RV64IZFINXZDINX: # %bb.0:908; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rmm909; RV64IZFINXZDINX-NEXT: ret910 %a = call double @llvm.round.f64(double %x)911 %b = fptoui double %a to i64912 ret i64 %b913}914 915define signext i8 @test_roundeven_si8(double %x) {916; RV32IFD-LABEL: test_roundeven_si8:917; RV32IFD: # %bb.0:918; RV32IFD-NEXT: fcvt.w.d a0, fa0, rne919; RV32IFD-NEXT: ret920;921; RV64IFD-LABEL: test_roundeven_si8:922; RV64IFD: # %bb.0:923; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne924; RV64IFD-NEXT: ret925;926; RV32IZFINXZDINX-LABEL: test_roundeven_si8:927; RV32IZFINXZDINX: # %bb.0:928; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rne929; RV32IZFINXZDINX-NEXT: ret930;931; RV64IZFINXZDINX-LABEL: test_roundeven_si8:932; RV64IZFINXZDINX: # %bb.0:933; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rne934; RV64IZFINXZDINX-NEXT: ret935 %a = call double @llvm.roundeven.f64(double %x)936 %b = fptosi double %a to i8937 ret i8 %b938}939 940define signext i16 @test_roundeven_si16(double %x) {941; RV32IFD-LABEL: test_roundeven_si16:942; RV32IFD: # %bb.0:943; RV32IFD-NEXT: fcvt.w.d a0, fa0, rne944; RV32IFD-NEXT: ret945;946; RV64IFD-LABEL: test_roundeven_si16:947; RV64IFD: # %bb.0:948; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne949; RV64IFD-NEXT: ret950;951; RV32IZFINXZDINX-LABEL: test_roundeven_si16:952; RV32IZFINXZDINX: # %bb.0:953; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rne954; RV32IZFINXZDINX-NEXT: ret955;956; RV64IZFINXZDINX-LABEL: test_roundeven_si16:957; RV64IZFINXZDINX: # %bb.0:958; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rne959; RV64IZFINXZDINX-NEXT: ret960 %a = call double @llvm.roundeven.f64(double %x)961 %b = fptosi double %a to i16962 ret i16 %b963}964 965define signext i32 @test_roundeven_si32(double %x) {966; CHECKIFD-LABEL: test_roundeven_si32:967; CHECKIFD: # %bb.0:968; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rne969; CHECKIFD-NEXT: ret970;971; RV32IZFINXZDINX-LABEL: test_roundeven_si32:972; RV32IZFINXZDINX: # %bb.0:973; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rne974; RV32IZFINXZDINX-NEXT: ret975;976; RV64IZFINXZDINX-LABEL: test_roundeven_si32:977; RV64IZFINXZDINX: # %bb.0:978; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rne979; RV64IZFINXZDINX-NEXT: ret980 %a = call double @llvm.roundeven.f64(double %x)981 %b = fptosi double %a to i32982 ret i32 %b983}984 985define i64 @test_roundeven_si64(double %x) {986; RV32IFD-LABEL: test_roundeven_si64:987; RV32IFD: # %bb.0:988; RV32IFD-NEXT: addi sp, sp, -16989; RV32IFD-NEXT: .cfi_def_cfa_offset 16990; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill991; RV32IFD-NEXT: .cfi_offset ra, -4992; RV32IFD-NEXT: call roundeven993; RV32IFD-NEXT: call __fixdfdi994; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload995; RV32IFD-NEXT: .cfi_restore ra996; RV32IFD-NEXT: addi sp, sp, 16997; RV32IFD-NEXT: .cfi_def_cfa_offset 0998; RV32IFD-NEXT: ret999;1000; RV64IFD-LABEL: test_roundeven_si64:1001; RV64IFD: # %bb.0:1002; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne1003; RV64IFD-NEXT: ret1004;1005; RV32IZFINXZDINX-LABEL: test_roundeven_si64:1006; RV32IZFINXZDINX: # %bb.0:1007; RV32IZFINXZDINX-NEXT: addi sp, sp, -161008; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 161009; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1010; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -41011; RV32IZFINXZDINX-NEXT: call roundeven1012; RV32IZFINXZDINX-NEXT: call __fixdfdi1013; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1014; RV32IZFINXZDINX-NEXT: .cfi_restore ra1015; RV32IZFINXZDINX-NEXT: addi sp, sp, 161016; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 01017; RV32IZFINXZDINX-NEXT: ret1018;1019; RV64IZFINXZDINX-LABEL: test_roundeven_si64:1020; RV64IZFINXZDINX: # %bb.0:1021; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rne1022; RV64IZFINXZDINX-NEXT: ret1023 %a = call double @llvm.roundeven.f64(double %x)1024 %b = fptosi double %a to i641025 ret i64 %b1026}1027 1028define zeroext i8 @test_roundeven_ui8(double %x) {1029; RV32IFD-LABEL: test_roundeven_ui8:1030; RV32IFD: # %bb.0:1031; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rne1032; RV32IFD-NEXT: ret1033;1034; RV64IFD-LABEL: test_roundeven_ui8:1035; RV64IFD: # %bb.0:1036; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rne1037; RV64IFD-NEXT: ret1038;1039; RV32IZFINXZDINX-LABEL: test_roundeven_ui8:1040; RV32IZFINXZDINX: # %bb.0:1041; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rne1042; RV32IZFINXZDINX-NEXT: ret1043;1044; RV64IZFINXZDINX-LABEL: test_roundeven_ui8:1045; RV64IZFINXZDINX: # %bb.0:1046; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rne1047; RV64IZFINXZDINX-NEXT: ret1048 %a = call double @llvm.roundeven.f64(double %x)1049 %b = fptoui double %a to i81050 ret i8 %b1051}1052 1053define zeroext i16 @test_roundeven_ui16(double %x) {1054; RV32IFD-LABEL: test_roundeven_ui16:1055; RV32IFD: # %bb.0:1056; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rne1057; RV32IFD-NEXT: ret1058;1059; RV64IFD-LABEL: test_roundeven_ui16:1060; RV64IFD: # %bb.0:1061; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rne1062; RV64IFD-NEXT: ret1063;1064; RV32IZFINXZDINX-LABEL: test_roundeven_ui16:1065; RV32IZFINXZDINX: # %bb.0:1066; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rne1067; RV32IZFINXZDINX-NEXT: ret1068;1069; RV64IZFINXZDINX-LABEL: test_roundeven_ui16:1070; RV64IZFINXZDINX: # %bb.0:1071; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rne1072; RV64IZFINXZDINX-NEXT: ret1073 %a = call double @llvm.roundeven.f64(double %x)1074 %b = fptoui double %a to i161075 ret i16 %b1076}1077 1078define signext i32 @test_roundeven_ui32(double %x) {1079; CHECKIFD-LABEL: test_roundeven_ui32:1080; CHECKIFD: # %bb.0:1081; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rne1082; CHECKIFD-NEXT: ret1083;1084; RV32IZFINXZDINX-LABEL: test_roundeven_ui32:1085; RV32IZFINXZDINX: # %bb.0:1086; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rne1087; RV32IZFINXZDINX-NEXT: ret1088;1089; RV64IZFINXZDINX-LABEL: test_roundeven_ui32:1090; RV64IZFINXZDINX: # %bb.0:1091; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rne1092; RV64IZFINXZDINX-NEXT: ret1093 %a = call double @llvm.roundeven.f64(double %x)1094 %b = fptoui double %a to i321095 ret i32 %b1096}1097 1098define i64 @test_roundeven_ui64(double %x) {1099; RV32IFD-LABEL: test_roundeven_ui64:1100; RV32IFD: # %bb.0:1101; RV32IFD-NEXT: addi sp, sp, -161102; RV32IFD-NEXT: .cfi_def_cfa_offset 161103; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1104; RV32IFD-NEXT: .cfi_offset ra, -41105; RV32IFD-NEXT: call roundeven1106; RV32IFD-NEXT: call __fixunsdfdi1107; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1108; RV32IFD-NEXT: .cfi_restore ra1109; RV32IFD-NEXT: addi sp, sp, 161110; RV32IFD-NEXT: .cfi_def_cfa_offset 01111; RV32IFD-NEXT: ret1112;1113; RV64IFD-LABEL: test_roundeven_ui64:1114; RV64IFD: # %bb.0:1115; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rne1116; RV64IFD-NEXT: ret1117;1118; RV32IZFINXZDINX-LABEL: test_roundeven_ui64:1119; RV32IZFINXZDINX: # %bb.0:1120; RV32IZFINXZDINX-NEXT: addi sp, sp, -161121; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 161122; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1123; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -41124; RV32IZFINXZDINX-NEXT: call roundeven1125; RV32IZFINXZDINX-NEXT: call __fixunsdfdi1126; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1127; RV32IZFINXZDINX-NEXT: .cfi_restore ra1128; RV32IZFINXZDINX-NEXT: addi sp, sp, 161129; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 01130; RV32IZFINXZDINX-NEXT: ret1131;1132; RV64IZFINXZDINX-LABEL: test_roundeven_ui64:1133; RV64IZFINXZDINX: # %bb.0:1134; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rne1135; RV64IZFINXZDINX-NEXT: ret1136 %a = call double @llvm.roundeven.f64(double %x)1137 %b = fptoui double %a to i641138 ret i64 %b1139}1140 1141define double @test_floor_double(double %x) {1142; RV32IFD-LABEL: test_floor_double:1143; RV32IFD: # %bb.0:1144; RV32IFD-NEXT: tail floor1145;1146; RV64IFD-LABEL: test_floor_double:1147; RV64IFD: # %bb.0:1148; RV64IFD-NEXT: li a0, 10751149; RV64IFD-NEXT: slli a0, a0, 521150; RV64IFD-NEXT: fmv.d.x fa5, a01151; RV64IFD-NEXT: fabs.d fa4, fa01152; RV64IFD-NEXT: flt.d a0, fa4, fa51153; RV64IFD-NEXT: beqz a0, .LBB40_21154; RV64IFD-NEXT: # %bb.1:1155; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn1156; RV64IFD-NEXT: fcvt.d.l fa5, a0, rdn1157; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa01158; RV64IFD-NEXT: .LBB40_2:1159; RV64IFD-NEXT: ret1160;1161; RV32IZFINXZDINX-LABEL: test_floor_double:1162; RV32IZFINXZDINX: # %bb.0:1163; RV32IZFINXZDINX-NEXT: addi sp, sp, -161164; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 161165; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1166; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -41167; RV32IZFINXZDINX-NEXT: call floor1168; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1169; RV32IZFINXZDINX-NEXT: .cfi_restore ra1170; RV32IZFINXZDINX-NEXT: addi sp, sp, 161171; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 01172; RV32IZFINXZDINX-NEXT: ret1173;1174; RV64IZFINXZDINX-LABEL: test_floor_double:1175; RV64IZFINXZDINX: # %bb.0:1176; RV64IZFINXZDINX-NEXT: li a1, 10751177; RV64IZFINXZDINX-NEXT: slli a1, a1, 521178; RV64IZFINXZDINX-NEXT: fabs.d a2, a01179; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a11180; RV64IZFINXZDINX-NEXT: beqz a1, .LBB40_21181; RV64IZFINXZDINX-NEXT: # %bb.1:1182; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rdn1183; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rdn1184; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a01185; RV64IZFINXZDINX-NEXT: .LBB40_2:1186; RV64IZFINXZDINX-NEXT: ret1187 %a = call double @llvm.floor.f64(double %x)1188 ret double %a1189}1190 1191define double @test_ceil_double(double %x) {1192; RV32IFD-LABEL: test_ceil_double:1193; RV32IFD: # %bb.0:1194; RV32IFD-NEXT: tail ceil1195;1196; RV64IFD-LABEL: test_ceil_double:1197; RV64IFD: # %bb.0:1198; RV64IFD-NEXT: li a0, 10751199; RV64IFD-NEXT: slli a0, a0, 521200; RV64IFD-NEXT: fmv.d.x fa5, a01201; RV64IFD-NEXT: fabs.d fa4, fa01202; RV64IFD-NEXT: flt.d a0, fa4, fa51203; RV64IFD-NEXT: beqz a0, .LBB41_21204; RV64IFD-NEXT: # %bb.1:1205; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup1206; RV64IFD-NEXT: fcvt.d.l fa5, a0, rup1207; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa01208; RV64IFD-NEXT: .LBB41_2:1209; RV64IFD-NEXT: ret1210;1211; RV32IZFINXZDINX-LABEL: test_ceil_double:1212; RV32IZFINXZDINX: # %bb.0:1213; RV32IZFINXZDINX-NEXT: addi sp, sp, -161214; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 161215; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1216; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -41217; RV32IZFINXZDINX-NEXT: call ceil1218; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1219; RV32IZFINXZDINX-NEXT: .cfi_restore ra1220; RV32IZFINXZDINX-NEXT: addi sp, sp, 161221; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 01222; RV32IZFINXZDINX-NEXT: ret1223;1224; RV64IZFINXZDINX-LABEL: test_ceil_double:1225; RV64IZFINXZDINX: # %bb.0:1226; RV64IZFINXZDINX-NEXT: li a1, 10751227; RV64IZFINXZDINX-NEXT: slli a1, a1, 521228; RV64IZFINXZDINX-NEXT: fabs.d a2, a01229; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a11230; RV64IZFINXZDINX-NEXT: beqz a1, .LBB41_21231; RV64IZFINXZDINX-NEXT: # %bb.1:1232; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rup1233; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rup1234; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a01235; RV64IZFINXZDINX-NEXT: .LBB41_2:1236; RV64IZFINXZDINX-NEXT: ret1237 %a = call double @llvm.ceil.f64(double %x)1238 ret double %a1239}1240 1241define double @test_trunc_double(double %x) {1242; RV32IFD-LABEL: test_trunc_double:1243; RV32IFD: # %bb.0:1244; RV32IFD-NEXT: tail trunc1245;1246; RV64IFD-LABEL: test_trunc_double:1247; RV64IFD: # %bb.0:1248; RV64IFD-NEXT: li a0, 10751249; RV64IFD-NEXT: slli a0, a0, 521250; RV64IFD-NEXT: fmv.d.x fa5, a01251; RV64IFD-NEXT: fabs.d fa4, fa01252; RV64IFD-NEXT: flt.d a0, fa4, fa51253; RV64IFD-NEXT: beqz a0, .LBB42_21254; RV64IFD-NEXT: # %bb.1:1255; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz1256; RV64IFD-NEXT: fcvt.d.l fa5, a0, rtz1257; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa01258; RV64IFD-NEXT: .LBB42_2:1259; RV64IFD-NEXT: ret1260;1261; RV32IZFINXZDINX-LABEL: test_trunc_double:1262; RV32IZFINXZDINX: # %bb.0:1263; RV32IZFINXZDINX-NEXT: addi sp, sp, -161264; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 161265; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1266; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -41267; RV32IZFINXZDINX-NEXT: call trunc1268; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1269; RV32IZFINXZDINX-NEXT: .cfi_restore ra1270; RV32IZFINXZDINX-NEXT: addi sp, sp, 161271; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 01272; RV32IZFINXZDINX-NEXT: ret1273;1274; RV64IZFINXZDINX-LABEL: test_trunc_double:1275; RV64IZFINXZDINX: # %bb.0:1276; RV64IZFINXZDINX-NEXT: li a1, 10751277; RV64IZFINXZDINX-NEXT: slli a1, a1, 521278; RV64IZFINXZDINX-NEXT: fabs.d a2, a01279; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a11280; RV64IZFINXZDINX-NEXT: beqz a1, .LBB42_21281; RV64IZFINXZDINX-NEXT: # %bb.1:1282; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rtz1283; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rtz1284; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a01285; RV64IZFINXZDINX-NEXT: .LBB42_2:1286; RV64IZFINXZDINX-NEXT: ret1287 %a = call double @llvm.trunc.f64(double %x)1288 ret double %a1289}1290 1291define double @test_round_double(double %x) {1292; RV32IFD-LABEL: test_round_double:1293; RV32IFD: # %bb.0:1294; RV32IFD-NEXT: tail round1295;1296; RV64IFD-LABEL: test_round_double:1297; RV64IFD: # %bb.0:1298; RV64IFD-NEXT: li a0, 10751299; RV64IFD-NEXT: slli a0, a0, 521300; RV64IFD-NEXT: fmv.d.x fa5, a01301; RV64IFD-NEXT: fabs.d fa4, fa01302; RV64IFD-NEXT: flt.d a0, fa4, fa51303; RV64IFD-NEXT: beqz a0, .LBB43_21304; RV64IFD-NEXT: # %bb.1:1305; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm1306; RV64IFD-NEXT: fcvt.d.l fa5, a0, rmm1307; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa01308; RV64IFD-NEXT: .LBB43_2:1309; RV64IFD-NEXT: ret1310;1311; RV32IZFINXZDINX-LABEL: test_round_double:1312; RV32IZFINXZDINX: # %bb.0:1313; RV32IZFINXZDINX-NEXT: addi sp, sp, -161314; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 161315; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1316; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -41317; RV32IZFINXZDINX-NEXT: call round1318; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1319; RV32IZFINXZDINX-NEXT: .cfi_restore ra1320; RV32IZFINXZDINX-NEXT: addi sp, sp, 161321; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 01322; RV32IZFINXZDINX-NEXT: ret1323;1324; RV64IZFINXZDINX-LABEL: test_round_double:1325; RV64IZFINXZDINX: # %bb.0:1326; RV64IZFINXZDINX-NEXT: li a1, 10751327; RV64IZFINXZDINX-NEXT: slli a1, a1, 521328; RV64IZFINXZDINX-NEXT: fabs.d a2, a01329; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a11330; RV64IZFINXZDINX-NEXT: beqz a1, .LBB43_21331; RV64IZFINXZDINX-NEXT: # %bb.1:1332; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rmm1333; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rmm1334; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a01335; RV64IZFINXZDINX-NEXT: .LBB43_2:1336; RV64IZFINXZDINX-NEXT: ret1337 %a = call double @llvm.round.f64(double %x)1338 ret double %a1339}1340 1341define double @test_roundeven_double(double %x) {1342; RV32IFD-LABEL: test_roundeven_double:1343; RV32IFD: # %bb.0:1344; RV32IFD-NEXT: tail roundeven1345;1346; RV64IFD-LABEL: test_roundeven_double:1347; RV64IFD: # %bb.0:1348; RV64IFD-NEXT: li a0, 10751349; RV64IFD-NEXT: slli a0, a0, 521350; RV64IFD-NEXT: fmv.d.x fa5, a01351; RV64IFD-NEXT: fabs.d fa4, fa01352; RV64IFD-NEXT: flt.d a0, fa4, fa51353; RV64IFD-NEXT: beqz a0, .LBB44_21354; RV64IFD-NEXT: # %bb.1:1355; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne1356; RV64IFD-NEXT: fcvt.d.l fa5, a0, rne1357; RV64IFD-NEXT: fsgnj.d fa0, fa5, fa01358; RV64IFD-NEXT: .LBB44_2:1359; RV64IFD-NEXT: ret1360;1361; RV32IZFINXZDINX-LABEL: test_roundeven_double:1362; RV32IZFINXZDINX: # %bb.0:1363; RV32IZFINXZDINX-NEXT: addi sp, sp, -161364; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 161365; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1366; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -41367; RV32IZFINXZDINX-NEXT: call roundeven1368; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1369; RV32IZFINXZDINX-NEXT: .cfi_restore ra1370; RV32IZFINXZDINX-NEXT: addi sp, sp, 161371; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 01372; RV32IZFINXZDINX-NEXT: ret1373;1374; RV64IZFINXZDINX-LABEL: test_roundeven_double:1375; RV64IZFINXZDINX: # %bb.0:1376; RV64IZFINXZDINX-NEXT: li a1, 10751377; RV64IZFINXZDINX-NEXT: slli a1, a1, 521378; RV64IZFINXZDINX-NEXT: fabs.d a2, a01379; RV64IZFINXZDINX-NEXT: flt.d a1, a2, a11380; RV64IZFINXZDINX-NEXT: beqz a1, .LBB44_21381; RV64IZFINXZDINX-NEXT: # %bb.1:1382; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rne1383; RV64IZFINXZDINX-NEXT: fcvt.d.l a1, a1, rne1384; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a1, a01385; RV64IZFINXZDINX-NEXT: .LBB44_2:1386; RV64IZFINXZDINX-NEXT: ret1387 %a = call double @llvm.roundeven.f64(double %x)1388 ret double %a1389}1390 1391