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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32d | FileCheck --check-prefixes=CHECK,RV32D %s4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \5; RUN: -target-abi=lp64d | FileCheck --check-prefixes=CHECK,RV64D %s6; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \7; RUN: -target-abi=ilp32 | FileCheck --check-prefix=CHECKRV32ZDINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \9; RUN: -target-abi=lp64 | FileCheck --check-prefix=CHECKRV64ZDINX %s10 11define double @select_fcmp_false(double %a, double %b) nounwind {12; CHECK-LABEL: select_fcmp_false:13; CHECK: # %bb.0:14; CHECK-NEXT: fmv.d fa0, fa115; CHECK-NEXT: ret16;17; CHECKRV32ZDINX-LABEL: select_fcmp_false:18; CHECKRV32ZDINX: # %bb.0:19; CHECKRV32ZDINX-NEXT: mv a1, a320; CHECKRV32ZDINX-NEXT: mv a0, a221; CHECKRV32ZDINX-NEXT: ret22;23; CHECKRV64ZDINX-LABEL: select_fcmp_false:24; CHECKRV64ZDINX: # %bb.0:25; CHECKRV64ZDINX-NEXT: mv a0, a126; CHECKRV64ZDINX-NEXT: ret27 %1 = fcmp false double %a, %b28 %2 = select i1 %1, double %a, double %b29 ret double %230}31 32define double @select_fcmp_oeq(double %a, double %b) nounwind {33; CHECK-LABEL: select_fcmp_oeq:34; CHECK: # %bb.0:35; CHECK-NEXT: feq.d a0, fa0, fa136; CHECK-NEXT: bnez a0, .LBB1_237; CHECK-NEXT: # %bb.1:38; CHECK-NEXT: fmv.d fa0, fa139; CHECK-NEXT: .LBB1_2:40; CHECK-NEXT: ret41;42; CHECKRV32ZDINX-LABEL: select_fcmp_oeq:43; CHECKRV32ZDINX: # %bb.0:44; CHECKRV32ZDINX-NEXT: feq.d a4, a0, a245; CHECKRV32ZDINX-NEXT: bnez a4, .LBB1_246; CHECKRV32ZDINX-NEXT: # %bb.1:47; CHECKRV32ZDINX-NEXT: fmv.d a0, a248; CHECKRV32ZDINX-NEXT: .LBB1_2:49; CHECKRV32ZDINX-NEXT: ret50;51; CHECKRV64ZDINX-LABEL: select_fcmp_oeq:52; CHECKRV64ZDINX: # %bb.0:53; CHECKRV64ZDINX-NEXT: feq.d a2, a0, a154; CHECKRV64ZDINX-NEXT: bnez a2, .LBB1_255; CHECKRV64ZDINX-NEXT: # %bb.1:56; CHECKRV64ZDINX-NEXT: mv a0, a157; CHECKRV64ZDINX-NEXT: .LBB1_2:58; CHECKRV64ZDINX-NEXT: ret59 %1 = fcmp oeq double %a, %b60 %2 = select i1 %1, double %a, double %b61 ret double %262}63 64define double @select_fcmp_ogt(double %a, double %b) nounwind {65; CHECK-LABEL: select_fcmp_ogt:66; CHECK: # %bb.0:67; CHECK-NEXT: flt.d a0, fa1, fa068; CHECK-NEXT: bnez a0, .LBB2_269; CHECK-NEXT: # %bb.1:70; CHECK-NEXT: fmv.d fa0, fa171; CHECK-NEXT: .LBB2_2:72; CHECK-NEXT: ret73;74; CHECKRV32ZDINX-LABEL: select_fcmp_ogt:75; CHECKRV32ZDINX: # %bb.0:76; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a077; CHECKRV32ZDINX-NEXT: bnez a4, .LBB2_278; CHECKRV32ZDINX-NEXT: # %bb.1:79; CHECKRV32ZDINX-NEXT: fmv.d a0, a280; CHECKRV32ZDINX-NEXT: .LBB2_2:81; CHECKRV32ZDINX-NEXT: ret82;83; CHECKRV64ZDINX-LABEL: select_fcmp_ogt:84; CHECKRV64ZDINX: # %bb.0:85; CHECKRV64ZDINX-NEXT: flt.d a2, a1, a086; CHECKRV64ZDINX-NEXT: bnez a2, .LBB2_287; CHECKRV64ZDINX-NEXT: # %bb.1:88; CHECKRV64ZDINX-NEXT: mv a0, a189; CHECKRV64ZDINX-NEXT: .LBB2_2:90; CHECKRV64ZDINX-NEXT: ret91 %1 = fcmp ogt double %a, %b92 %2 = select i1 %1, double %a, double %b93 ret double %294}95 96define double @select_fcmp_oge(double %a, double %b) nounwind {97; CHECK-LABEL: select_fcmp_oge:98; CHECK: # %bb.0:99; CHECK-NEXT: fle.d a0, fa1, fa0100; CHECK-NEXT: bnez a0, .LBB3_2101; CHECK-NEXT: # %bb.1:102; CHECK-NEXT: fmv.d fa0, fa1103; CHECK-NEXT: .LBB3_2:104; CHECK-NEXT: ret105;106; CHECKRV32ZDINX-LABEL: select_fcmp_oge:107; CHECKRV32ZDINX: # %bb.0:108; CHECKRV32ZDINX-NEXT: fle.d a4, a2, a0109; CHECKRV32ZDINX-NEXT: bnez a4, .LBB3_2110; CHECKRV32ZDINX-NEXT: # %bb.1:111; CHECKRV32ZDINX-NEXT: fmv.d a0, a2112; CHECKRV32ZDINX-NEXT: .LBB3_2:113; CHECKRV32ZDINX-NEXT: ret114;115; CHECKRV64ZDINX-LABEL: select_fcmp_oge:116; CHECKRV64ZDINX: # %bb.0:117; CHECKRV64ZDINX-NEXT: fle.d a2, a1, a0118; CHECKRV64ZDINX-NEXT: bnez a2, .LBB3_2119; CHECKRV64ZDINX-NEXT: # %bb.1:120; CHECKRV64ZDINX-NEXT: mv a0, a1121; CHECKRV64ZDINX-NEXT: .LBB3_2:122; CHECKRV64ZDINX-NEXT: ret123 %1 = fcmp oge double %a, %b124 %2 = select i1 %1, double %a, double %b125 ret double %2126}127 128define double @select_fcmp_olt(double %a, double %b) nounwind {129; CHECK-LABEL: select_fcmp_olt:130; CHECK: # %bb.0:131; CHECK-NEXT: flt.d a0, fa0, fa1132; CHECK-NEXT: bnez a0, .LBB4_2133; CHECK-NEXT: # %bb.1:134; CHECK-NEXT: fmv.d fa0, fa1135; CHECK-NEXT: .LBB4_2:136; CHECK-NEXT: ret137;138; CHECKRV32ZDINX-LABEL: select_fcmp_olt:139; CHECKRV32ZDINX: # %bb.0:140; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2141; CHECKRV32ZDINX-NEXT: bnez a4, .LBB4_2142; CHECKRV32ZDINX-NEXT: # %bb.1:143; CHECKRV32ZDINX-NEXT: fmv.d a0, a2144; CHECKRV32ZDINX-NEXT: .LBB4_2:145; CHECKRV32ZDINX-NEXT: ret146;147; CHECKRV64ZDINX-LABEL: select_fcmp_olt:148; CHECKRV64ZDINX: # %bb.0:149; CHECKRV64ZDINX-NEXT: flt.d a2, a0, a1150; CHECKRV64ZDINX-NEXT: bnez a2, .LBB4_2151; CHECKRV64ZDINX-NEXT: # %bb.1:152; CHECKRV64ZDINX-NEXT: mv a0, a1153; CHECKRV64ZDINX-NEXT: .LBB4_2:154; CHECKRV64ZDINX-NEXT: ret155 %1 = fcmp olt double %a, %b156 %2 = select i1 %1, double %a, double %b157 ret double %2158}159 160define double @select_fcmp_ole(double %a, double %b) nounwind {161; CHECK-LABEL: select_fcmp_ole:162; CHECK: # %bb.0:163; CHECK-NEXT: fle.d a0, fa0, fa1164; CHECK-NEXT: bnez a0, .LBB5_2165; CHECK-NEXT: # %bb.1:166; CHECK-NEXT: fmv.d fa0, fa1167; CHECK-NEXT: .LBB5_2:168; CHECK-NEXT: ret169;170; CHECKRV32ZDINX-LABEL: select_fcmp_ole:171; CHECKRV32ZDINX: # %bb.0:172; CHECKRV32ZDINX-NEXT: fle.d a4, a0, a2173; CHECKRV32ZDINX-NEXT: bnez a4, .LBB5_2174; CHECKRV32ZDINX-NEXT: # %bb.1:175; CHECKRV32ZDINX-NEXT: fmv.d a0, a2176; CHECKRV32ZDINX-NEXT: .LBB5_2:177; CHECKRV32ZDINX-NEXT: ret178;179; CHECKRV64ZDINX-LABEL: select_fcmp_ole:180; CHECKRV64ZDINX: # %bb.0:181; CHECKRV64ZDINX-NEXT: fle.d a2, a0, a1182; CHECKRV64ZDINX-NEXT: bnez a2, .LBB5_2183; CHECKRV64ZDINX-NEXT: # %bb.1:184; CHECKRV64ZDINX-NEXT: mv a0, a1185; CHECKRV64ZDINX-NEXT: .LBB5_2:186; CHECKRV64ZDINX-NEXT: ret187 %1 = fcmp ole double %a, %b188 %2 = select i1 %1, double %a, double %b189 ret double %2190}191 192define double @select_fcmp_one(double %a, double %b) nounwind {193; CHECK-LABEL: select_fcmp_one:194; CHECK: # %bb.0:195; CHECK-NEXT: flt.d a0, fa0, fa1196; CHECK-NEXT: flt.d a1, fa1, fa0197; CHECK-NEXT: or a0, a1, a0198; CHECK-NEXT: bnez a0, .LBB6_2199; CHECK-NEXT: # %bb.1:200; CHECK-NEXT: fmv.d fa0, fa1201; CHECK-NEXT: .LBB6_2:202; CHECK-NEXT: ret203;204; CHECKRV32ZDINX-LABEL: select_fcmp_one:205; CHECKRV32ZDINX: # %bb.0:206; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2207; CHECKRV32ZDINX-NEXT: flt.d a5, a2, a0208; CHECKRV32ZDINX-NEXT: or a4, a5, a4209; CHECKRV32ZDINX-NEXT: bnez a4, .LBB6_2210; CHECKRV32ZDINX-NEXT: # %bb.1:211; CHECKRV32ZDINX-NEXT: fmv.d a0, a2212; CHECKRV32ZDINX-NEXT: .LBB6_2:213; CHECKRV32ZDINX-NEXT: ret214;215; CHECKRV64ZDINX-LABEL: select_fcmp_one:216; CHECKRV64ZDINX: # %bb.0:217; CHECKRV64ZDINX-NEXT: flt.d a2, a0, a1218; CHECKRV64ZDINX-NEXT: flt.d a3, a1, a0219; CHECKRV64ZDINX-NEXT: or a2, a3, a2220; CHECKRV64ZDINX-NEXT: bnez a2, .LBB6_2221; CHECKRV64ZDINX-NEXT: # %bb.1:222; CHECKRV64ZDINX-NEXT: mv a0, a1223; CHECKRV64ZDINX-NEXT: .LBB6_2:224; CHECKRV64ZDINX-NEXT: ret225 %1 = fcmp one double %a, %b226 %2 = select i1 %1, double %a, double %b227 ret double %2228}229 230define double @select_fcmp_ord(double %a, double %b) nounwind {231; CHECK-LABEL: select_fcmp_ord:232; CHECK: # %bb.0:233; CHECK-NEXT: feq.d a0, fa1, fa1234; CHECK-NEXT: feq.d a1, fa0, fa0235; CHECK-NEXT: and a0, a1, a0236; CHECK-NEXT: bnez a0, .LBB7_2237; CHECK-NEXT: # %bb.1:238; CHECK-NEXT: fmv.d fa0, fa1239; CHECK-NEXT: .LBB7_2:240; CHECK-NEXT: ret241;242; CHECKRV32ZDINX-LABEL: select_fcmp_ord:243; CHECKRV32ZDINX: # %bb.0:244; CHECKRV32ZDINX-NEXT: feq.d a4, a2, a2245; CHECKRV32ZDINX-NEXT: feq.d a5, a0, a0246; CHECKRV32ZDINX-NEXT: and a4, a5, a4247; CHECKRV32ZDINX-NEXT: bnez a4, .LBB7_2248; CHECKRV32ZDINX-NEXT: # %bb.1:249; CHECKRV32ZDINX-NEXT: fmv.d a0, a2250; CHECKRV32ZDINX-NEXT: .LBB7_2:251; CHECKRV32ZDINX-NEXT: ret252;253; CHECKRV64ZDINX-LABEL: select_fcmp_ord:254; CHECKRV64ZDINX: # %bb.0:255; CHECKRV64ZDINX-NEXT: feq.d a2, a1, a1256; CHECKRV64ZDINX-NEXT: feq.d a3, a0, a0257; CHECKRV64ZDINX-NEXT: and a2, a3, a2258; CHECKRV64ZDINX-NEXT: bnez a2, .LBB7_2259; CHECKRV64ZDINX-NEXT: # %bb.1:260; CHECKRV64ZDINX-NEXT: mv a0, a1261; CHECKRV64ZDINX-NEXT: .LBB7_2:262; CHECKRV64ZDINX-NEXT: ret263 %1 = fcmp ord double %a, %b264 %2 = select i1 %1, double %a, double %b265 ret double %2266}267 268define double @select_fcmp_ueq(double %a, double %b) nounwind {269; CHECK-LABEL: select_fcmp_ueq:270; CHECK: # %bb.0:271; CHECK-NEXT: flt.d a0, fa0, fa1272; CHECK-NEXT: flt.d a1, fa1, fa0273; CHECK-NEXT: or a0, a1, a0274; CHECK-NEXT: beqz a0, .LBB8_2275; CHECK-NEXT: # %bb.1:276; CHECK-NEXT: fmv.d fa0, fa1277; CHECK-NEXT: .LBB8_2:278; CHECK-NEXT: ret279;280; CHECKRV32ZDINX-LABEL: select_fcmp_ueq:281; CHECKRV32ZDINX: # %bb.0:282; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2283; CHECKRV32ZDINX-NEXT: flt.d a5, a2, a0284; CHECKRV32ZDINX-NEXT: or a4, a5, a4285; CHECKRV32ZDINX-NEXT: beqz a4, .LBB8_2286; CHECKRV32ZDINX-NEXT: # %bb.1:287; CHECKRV32ZDINX-NEXT: fmv.d a0, a2288; CHECKRV32ZDINX-NEXT: .LBB8_2:289; CHECKRV32ZDINX-NEXT: ret290;291; CHECKRV64ZDINX-LABEL: select_fcmp_ueq:292; CHECKRV64ZDINX: # %bb.0:293; CHECKRV64ZDINX-NEXT: flt.d a2, a0, a1294; CHECKRV64ZDINX-NEXT: flt.d a3, a1, a0295; CHECKRV64ZDINX-NEXT: or a2, a3, a2296; CHECKRV64ZDINX-NEXT: beqz a2, .LBB8_2297; CHECKRV64ZDINX-NEXT: # %bb.1:298; CHECKRV64ZDINX-NEXT: mv a0, a1299; CHECKRV64ZDINX-NEXT: .LBB8_2:300; CHECKRV64ZDINX-NEXT: ret301 %1 = fcmp ueq double %a, %b302 %2 = select i1 %1, double %a, double %b303 ret double %2304}305 306define double @select_fcmp_ugt(double %a, double %b) nounwind {307; CHECK-LABEL: select_fcmp_ugt:308; CHECK: # %bb.0:309; CHECK-NEXT: fle.d a0, fa0, fa1310; CHECK-NEXT: beqz a0, .LBB9_2311; CHECK-NEXT: # %bb.1:312; CHECK-NEXT: fmv.d fa0, fa1313; CHECK-NEXT: .LBB9_2:314; CHECK-NEXT: ret315;316; CHECKRV32ZDINX-LABEL: select_fcmp_ugt:317; CHECKRV32ZDINX: # %bb.0:318; CHECKRV32ZDINX-NEXT: fle.d a4, a0, a2319; CHECKRV32ZDINX-NEXT: beqz a4, .LBB9_2320; CHECKRV32ZDINX-NEXT: # %bb.1:321; CHECKRV32ZDINX-NEXT: fmv.d a0, a2322; CHECKRV32ZDINX-NEXT: .LBB9_2:323; CHECKRV32ZDINX-NEXT: ret324;325; CHECKRV64ZDINX-LABEL: select_fcmp_ugt:326; CHECKRV64ZDINX: # %bb.0:327; CHECKRV64ZDINX-NEXT: fle.d a2, a0, a1328; CHECKRV64ZDINX-NEXT: beqz a2, .LBB9_2329; CHECKRV64ZDINX-NEXT: # %bb.1:330; CHECKRV64ZDINX-NEXT: mv a0, a1331; CHECKRV64ZDINX-NEXT: .LBB9_2:332; CHECKRV64ZDINX-NEXT: ret333 %1 = fcmp ugt double %a, %b334 %2 = select i1 %1, double %a, double %b335 ret double %2336}337 338define double @select_fcmp_uge(double %a, double %b) nounwind {339; CHECK-LABEL: select_fcmp_uge:340; CHECK: # %bb.0:341; CHECK-NEXT: flt.d a0, fa0, fa1342; CHECK-NEXT: beqz a0, .LBB10_2343; CHECK-NEXT: # %bb.1:344; CHECK-NEXT: fmv.d fa0, fa1345; CHECK-NEXT: .LBB10_2:346; CHECK-NEXT: ret347;348; CHECKRV32ZDINX-LABEL: select_fcmp_uge:349; CHECKRV32ZDINX: # %bb.0:350; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2351; CHECKRV32ZDINX-NEXT: beqz a4, .LBB10_2352; CHECKRV32ZDINX-NEXT: # %bb.1:353; CHECKRV32ZDINX-NEXT: fmv.d a0, a2354; CHECKRV32ZDINX-NEXT: .LBB10_2:355; CHECKRV32ZDINX-NEXT: ret356;357; CHECKRV64ZDINX-LABEL: select_fcmp_uge:358; CHECKRV64ZDINX: # %bb.0:359; CHECKRV64ZDINX-NEXT: flt.d a2, a0, a1360; CHECKRV64ZDINX-NEXT: beqz a2, .LBB10_2361; CHECKRV64ZDINX-NEXT: # %bb.1:362; CHECKRV64ZDINX-NEXT: mv a0, a1363; CHECKRV64ZDINX-NEXT: .LBB10_2:364; CHECKRV64ZDINX-NEXT: ret365 %1 = fcmp uge double %a, %b366 %2 = select i1 %1, double %a, double %b367 ret double %2368}369 370define double @select_fcmp_ult(double %a, double %b) nounwind {371; CHECK-LABEL: select_fcmp_ult:372; CHECK: # %bb.0:373; CHECK-NEXT: fle.d a0, fa1, fa0374; CHECK-NEXT: beqz a0, .LBB11_2375; CHECK-NEXT: # %bb.1:376; CHECK-NEXT: fmv.d fa0, fa1377; CHECK-NEXT: .LBB11_2:378; CHECK-NEXT: ret379;380; CHECKRV32ZDINX-LABEL: select_fcmp_ult:381; CHECKRV32ZDINX: # %bb.0:382; CHECKRV32ZDINX-NEXT: fle.d a4, a2, a0383; CHECKRV32ZDINX-NEXT: beqz a4, .LBB11_2384; CHECKRV32ZDINX-NEXT: # %bb.1:385; CHECKRV32ZDINX-NEXT: fmv.d a0, a2386; CHECKRV32ZDINX-NEXT: .LBB11_2:387; CHECKRV32ZDINX-NEXT: ret388;389; CHECKRV64ZDINX-LABEL: select_fcmp_ult:390; CHECKRV64ZDINX: # %bb.0:391; CHECKRV64ZDINX-NEXT: fle.d a2, a1, a0392; CHECKRV64ZDINX-NEXT: beqz a2, .LBB11_2393; CHECKRV64ZDINX-NEXT: # %bb.1:394; CHECKRV64ZDINX-NEXT: mv a0, a1395; CHECKRV64ZDINX-NEXT: .LBB11_2:396; CHECKRV64ZDINX-NEXT: ret397 %1 = fcmp ult double %a, %b398 %2 = select i1 %1, double %a, double %b399 ret double %2400}401 402define double @select_fcmp_ule(double %a, double %b) nounwind {403; CHECK-LABEL: select_fcmp_ule:404; CHECK: # %bb.0:405; CHECK-NEXT: flt.d a0, fa1, fa0406; CHECK-NEXT: beqz a0, .LBB12_2407; CHECK-NEXT: # %bb.1:408; CHECK-NEXT: fmv.d fa0, fa1409; CHECK-NEXT: .LBB12_2:410; CHECK-NEXT: ret411;412; CHECKRV32ZDINX-LABEL: select_fcmp_ule:413; CHECKRV32ZDINX: # %bb.0:414; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0415; CHECKRV32ZDINX-NEXT: beqz a4, .LBB12_2416; CHECKRV32ZDINX-NEXT: # %bb.1:417; CHECKRV32ZDINX-NEXT: fmv.d a0, a2418; CHECKRV32ZDINX-NEXT: .LBB12_2:419; CHECKRV32ZDINX-NEXT: ret420;421; CHECKRV64ZDINX-LABEL: select_fcmp_ule:422; CHECKRV64ZDINX: # %bb.0:423; CHECKRV64ZDINX-NEXT: flt.d a2, a1, a0424; CHECKRV64ZDINX-NEXT: beqz a2, .LBB12_2425; CHECKRV64ZDINX-NEXT: # %bb.1:426; CHECKRV64ZDINX-NEXT: mv a0, a1427; CHECKRV64ZDINX-NEXT: .LBB12_2:428; CHECKRV64ZDINX-NEXT: ret429 %1 = fcmp ule double %a, %b430 %2 = select i1 %1, double %a, double %b431 ret double %2432}433 434define double @select_fcmp_une(double %a, double %b) nounwind {435; CHECK-LABEL: select_fcmp_une:436; CHECK: # %bb.0:437; CHECK-NEXT: feq.d a0, fa0, fa1438; CHECK-NEXT: beqz a0, .LBB13_2439; CHECK-NEXT: # %bb.1:440; CHECK-NEXT: fmv.d fa0, fa1441; CHECK-NEXT: .LBB13_2:442; CHECK-NEXT: ret443;444; CHECKRV32ZDINX-LABEL: select_fcmp_une:445; CHECKRV32ZDINX: # %bb.0:446; CHECKRV32ZDINX-NEXT: feq.d a4, a0, a2447; CHECKRV32ZDINX-NEXT: beqz a4, .LBB13_2448; CHECKRV32ZDINX-NEXT: # %bb.1:449; CHECKRV32ZDINX-NEXT: fmv.d a0, a2450; CHECKRV32ZDINX-NEXT: .LBB13_2:451; CHECKRV32ZDINX-NEXT: ret452;453; CHECKRV64ZDINX-LABEL: select_fcmp_une:454; CHECKRV64ZDINX: # %bb.0:455; CHECKRV64ZDINX-NEXT: feq.d a2, a0, a1456; CHECKRV64ZDINX-NEXT: beqz a2, .LBB13_2457; CHECKRV64ZDINX-NEXT: # %bb.1:458; CHECKRV64ZDINX-NEXT: mv a0, a1459; CHECKRV64ZDINX-NEXT: .LBB13_2:460; CHECKRV64ZDINX-NEXT: ret461 %1 = fcmp une double %a, %b462 %2 = select i1 %1, double %a, double %b463 ret double %2464}465 466define double @select_fcmp_uno(double %a, double %b) nounwind {467; CHECK-LABEL: select_fcmp_uno:468; CHECK: # %bb.0:469; CHECK-NEXT: feq.d a0, fa1, fa1470; CHECK-NEXT: feq.d a1, fa0, fa0471; CHECK-NEXT: and a0, a1, a0472; CHECK-NEXT: beqz a0, .LBB14_2473; CHECK-NEXT: # %bb.1:474; CHECK-NEXT: fmv.d fa0, fa1475; CHECK-NEXT: .LBB14_2:476; CHECK-NEXT: ret477;478; CHECKRV32ZDINX-LABEL: select_fcmp_uno:479; CHECKRV32ZDINX: # %bb.0:480; CHECKRV32ZDINX-NEXT: feq.d a4, a2, a2481; CHECKRV32ZDINX-NEXT: feq.d a5, a0, a0482; CHECKRV32ZDINX-NEXT: and a4, a5, a4483; CHECKRV32ZDINX-NEXT: beqz a4, .LBB14_2484; CHECKRV32ZDINX-NEXT: # %bb.1:485; CHECKRV32ZDINX-NEXT: fmv.d a0, a2486; CHECKRV32ZDINX-NEXT: .LBB14_2:487; CHECKRV32ZDINX-NEXT: ret488;489; CHECKRV64ZDINX-LABEL: select_fcmp_uno:490; CHECKRV64ZDINX: # %bb.0:491; CHECKRV64ZDINX-NEXT: feq.d a2, a1, a1492; CHECKRV64ZDINX-NEXT: feq.d a3, a0, a0493; CHECKRV64ZDINX-NEXT: and a2, a3, a2494; CHECKRV64ZDINX-NEXT: beqz a2, .LBB14_2495; CHECKRV64ZDINX-NEXT: # %bb.1:496; CHECKRV64ZDINX-NEXT: mv a0, a1497; CHECKRV64ZDINX-NEXT: .LBB14_2:498; CHECKRV64ZDINX-NEXT: ret499 %1 = fcmp uno double %a, %b500 %2 = select i1 %1, double %a, double %b501 ret double %2502}503 504define double @select_fcmp_true(double %a, double %b) nounwind {505; CHECK-LABEL: select_fcmp_true:506; CHECK: # %bb.0:507; CHECK-NEXT: ret508;509; CHECKRV32ZDINX-LABEL: select_fcmp_true:510; CHECKRV32ZDINX: # %bb.0:511; CHECKRV32ZDINX-NEXT: ret512;513; CHECKRV64ZDINX-LABEL: select_fcmp_true:514; CHECKRV64ZDINX: # %bb.0:515; CHECKRV64ZDINX-NEXT: ret516 %1 = fcmp true double %a, %b517 %2 = select i1 %1, double %a, double %b518 ret double %2519}520 521; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.522define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {523; CHECK-LABEL: i32_select_fcmp_oeq:524; CHECK: # %bb.0:525; CHECK-NEXT: feq.d a2, fa0, fa1526; CHECK-NEXT: bnez a2, .LBB16_2527; CHECK-NEXT: # %bb.1:528; CHECK-NEXT: mv a0, a1529; CHECK-NEXT: .LBB16_2:530; CHECK-NEXT: ret531;532; CHECKRV32ZDINX-LABEL: i32_select_fcmp_oeq:533; CHECKRV32ZDINX: # %bb.0:534; CHECKRV32ZDINX-NEXT: feq.d a1, a0, a2535; CHECKRV32ZDINX-NEXT: mv a0, a4536; CHECKRV32ZDINX-NEXT: bnez a1, .LBB16_2537; CHECKRV32ZDINX-NEXT: # %bb.1:538; CHECKRV32ZDINX-NEXT: mv a0, a5539; CHECKRV32ZDINX-NEXT: .LBB16_2:540; CHECKRV32ZDINX-NEXT: ret541;542; CHECKRV64ZDINX-LABEL: i32_select_fcmp_oeq:543; CHECKRV64ZDINX: # %bb.0:544; CHECKRV64ZDINX-NEXT: feq.d a1, a0, a1545; CHECKRV64ZDINX-NEXT: mv a0, a2546; CHECKRV64ZDINX-NEXT: bnez a1, .LBB16_2547; CHECKRV64ZDINX-NEXT: # %bb.1:548; CHECKRV64ZDINX-NEXT: mv a0, a3549; CHECKRV64ZDINX-NEXT: .LBB16_2:550; CHECKRV64ZDINX-NEXT: ret551 %1 = fcmp oeq double %a, %b552 %2 = select i1 %1, i32 %c, i32 %d553 ret i32 %2554}555 556define i32 @select_fcmp_oeq_1_2(double %a, double %b) {557; CHECK-LABEL: select_fcmp_oeq_1_2:558; CHECK: # %bb.0:559; CHECK-NEXT: feq.d a0, fa0, fa1560; CHECK-NEXT: li a1, 2561; CHECK-NEXT: sub a0, a1, a0562; CHECK-NEXT: ret563;564; CHECKRV32ZDINX-LABEL: select_fcmp_oeq_1_2:565; CHECKRV32ZDINX: # %bb.0:566; CHECKRV32ZDINX-NEXT: li a4, 2567; CHECKRV32ZDINX-NEXT: feq.d a0, a0, a2568; CHECKRV32ZDINX-NEXT: sub a0, a4, a0569; CHECKRV32ZDINX-NEXT: ret570;571; CHECKRV64ZDINX-LABEL: select_fcmp_oeq_1_2:572; CHECKRV64ZDINX: # %bb.0:573; CHECKRV64ZDINX-NEXT: feq.d a0, a0, a1574; CHECKRV64ZDINX-NEXT: li a1, 2575; CHECKRV64ZDINX-NEXT: sub a0, a1, a0576; CHECKRV64ZDINX-NEXT: ret577 %1 = fcmp fast oeq double %a, %b578 %2 = select i1 %1, i32 1, i32 2579 ret i32 %2580}581 582define signext i32 @select_fcmp_uge_negone_zero(double %a, double %b) nounwind {583; CHECK-LABEL: select_fcmp_uge_negone_zero:584; CHECK: # %bb.0:585; CHECK-NEXT: fle.d a0, fa0, fa1586; CHECK-NEXT: addi a0, a0, -1587; CHECK-NEXT: ret588;589; CHECKRV32ZDINX-LABEL: select_fcmp_uge_negone_zero:590; CHECKRV32ZDINX: # %bb.0:591; CHECKRV32ZDINX-NEXT: fle.d a0, a0, a2592; CHECKRV32ZDINX-NEXT: addi a0, a0, -1593; CHECKRV32ZDINX-NEXT: ret594;595; CHECKRV64ZDINX-LABEL: select_fcmp_uge_negone_zero:596; CHECKRV64ZDINX: # %bb.0:597; CHECKRV64ZDINX-NEXT: fle.d a0, a0, a1598; CHECKRV64ZDINX-NEXT: addi a0, a0, -1599; CHECKRV64ZDINX-NEXT: ret600 %1 = fcmp ugt double %a, %b601 %2 = select i1 %1, i32 -1, i32 0602 ret i32 %2603}604 605define signext i32 @select_fcmp_uge_1_2(double %a, double %b) nounwind {606; CHECK-LABEL: select_fcmp_uge_1_2:607; CHECK: # %bb.0:608; CHECK-NEXT: fle.d a0, fa0, fa1609; CHECK-NEXT: addi a0, a0, 1610; CHECK-NEXT: ret611;612; CHECKRV32ZDINX-LABEL: select_fcmp_uge_1_2:613; CHECKRV32ZDINX: # %bb.0:614; CHECKRV32ZDINX-NEXT: fle.d a0, a0, a2615; CHECKRV32ZDINX-NEXT: addi a0, a0, 1616; CHECKRV32ZDINX-NEXT: ret617;618; CHECKRV64ZDINX-LABEL: select_fcmp_uge_1_2:619; CHECKRV64ZDINX: # %bb.0:620; CHECKRV64ZDINX-NEXT: fle.d a0, a0, a1621; CHECKRV64ZDINX-NEXT: addi a0, a0, 1622; CHECKRV64ZDINX-NEXT: ret623 %1 = fcmp ugt double %a, %b624 %2 = select i1 %1, i32 1, i32 2625 ret i32 %2626}627 628define double @CascadedSelect(double noundef %a) {629; RV32D-LABEL: CascadedSelect:630; RV32D: # %bb.0: # %entry631; RV32D-NEXT: lui a0, %hi(.LCPI20_0)632; RV32D-NEXT: fld fa5, %lo(.LCPI20_0)(a0)633; RV32D-NEXT: flt.d a0, fa5, fa0634; RV32D-NEXT: bnez a0, .LBB20_3635; RV32D-NEXT: # %bb.1: # %entry636; RV32D-NEXT: fcvt.d.w fa5, zero637; RV32D-NEXT: flt.d a0, fa0, fa5638; RV32D-NEXT: bnez a0, .LBB20_3639; RV32D-NEXT: # %bb.2: # %entry640; RV32D-NEXT: fmv.d fa5, fa0641; RV32D-NEXT: .LBB20_3: # %entry642; RV32D-NEXT: fmv.d fa0, fa5643; RV32D-NEXT: ret644;645; RV64D-LABEL: CascadedSelect:646; RV64D: # %bb.0: # %entry647; RV64D-NEXT: li a0, 1023648; RV64D-NEXT: slli a0, a0, 52649; RV64D-NEXT: fmv.d.x fa5, a0650; RV64D-NEXT: flt.d a0, fa5, fa0651; RV64D-NEXT: bnez a0, .LBB20_3652; RV64D-NEXT: # %bb.1: # %entry653; RV64D-NEXT: fmv.d.x fa5, zero654; RV64D-NEXT: flt.d a0, fa0, fa5655; RV64D-NEXT: bnez a0, .LBB20_3656; RV64D-NEXT: # %bb.2: # %entry657; RV64D-NEXT: fmv.d fa5, fa0658; RV64D-NEXT: .LBB20_3: # %entry659; RV64D-NEXT: fmv.d fa0, fa5660; RV64D-NEXT: ret661;662; CHECKRV32ZDINX-LABEL: CascadedSelect:663; CHECKRV32ZDINX: # %bb.0: # %entry664; CHECKRV32ZDINX-NEXT: lui a3, %hi(.LCPI20_0)665; CHECKRV32ZDINX-NEXT: lw a2, %lo(.LCPI20_0)(a3)666; CHECKRV32ZDINX-NEXT: addi a3, a3, %lo(.LCPI20_0)667; CHECKRV32ZDINX-NEXT: lw a3, 4(a3)668; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0669; CHECKRV32ZDINX-NEXT: bnez a4, .LBB20_3670; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry671; CHECKRV32ZDINX-NEXT: flt.d a4, a0, zero672; CHECKRV32ZDINX-NEXT: fmv.d a2, zero673; CHECKRV32ZDINX-NEXT: bnez a4, .LBB20_3674; CHECKRV32ZDINX-NEXT: # %bb.2: # %entry675; CHECKRV32ZDINX-NEXT: fmv.d a2, a0676; CHECKRV32ZDINX-NEXT: .LBB20_3: # %entry677; CHECKRV32ZDINX-NEXT: mv a0, a2678; CHECKRV32ZDINX-NEXT: mv a1, a3679; CHECKRV32ZDINX-NEXT: ret680;681; CHECKRV64ZDINX-LABEL: CascadedSelect:682; CHECKRV64ZDINX: # %bb.0: # %entry683; CHECKRV64ZDINX-NEXT: li a1, 1023684; CHECKRV64ZDINX-NEXT: slli a1, a1, 52685; CHECKRV64ZDINX-NEXT: flt.d a2, a1, a0686; CHECKRV64ZDINX-NEXT: bnez a2, .LBB20_3687; CHECKRV64ZDINX-NEXT: # %bb.1: # %entry688; CHECKRV64ZDINX-NEXT: flt.d a2, a0, zero689; CHECKRV64ZDINX-NEXT: li a1, 0690; CHECKRV64ZDINX-NEXT: bnez a2, .LBB20_3691; CHECKRV64ZDINX-NEXT: # %bb.2: # %entry692; CHECKRV64ZDINX-NEXT: mv a1, a0693; CHECKRV64ZDINX-NEXT: .LBB20_3: # %entry694; CHECKRV64ZDINX-NEXT: mv a0, a1695; CHECKRV64ZDINX-NEXT: ret696entry:697 %cmp = fcmp ogt double %a, 1.000000e+00698 %cmp1 = fcmp olt double %a, 0.000000e+00699 %.a = select i1 %cmp1, double 0.000000e+00, double %a700 %retval.0 = select i1 %cmp, double 1.000000e+00, double %.a701 ret double %retval.0702}703