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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2 3; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \4; RUN: -target-abi=ilp32d | FileCheck %s5; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \6; RUN: -target-abi=lp64d | FileCheck %s7; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \8; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32ZDINX %s9; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \10; RUN: -target-abi=lp64 | FileCheck -check-prefixes=RV64ZDINX %s11 12define double @select_icmp_eq(i32 signext %a, i32 signext %b, double %c, double %d) {13; CHECK-LABEL: select_icmp_eq:14; CHECK: # %bb.0:15; CHECK-NEXT: beq a0, a1, .LBB0_216; CHECK-NEXT: # %bb.1:17; CHECK-NEXT: fmv.d fa0, fa118; CHECK-NEXT: .LBB0_2:19; CHECK-NEXT: ret20;21; RV32ZDINX-LABEL: select_icmp_eq:22; RV32ZDINX: # %bb.0:23; RV32ZDINX-NEXT: beq a0, a1, .LBB0_224; RV32ZDINX-NEXT: # %bb.1:25; RV32ZDINX-NEXT: fmv.d a2, a426; RV32ZDINX-NEXT: .LBB0_2:27; RV32ZDINX-NEXT: mv a0, a228; RV32ZDINX-NEXT: mv a1, a329; RV32ZDINX-NEXT: ret30;31; RV64ZDINX-LABEL: select_icmp_eq:32; RV64ZDINX: # %bb.0:33; RV64ZDINX-NEXT: beq a0, a1, .LBB0_234; RV64ZDINX-NEXT: # %bb.1:35; RV64ZDINX-NEXT: mv a2, a336; RV64ZDINX-NEXT: .LBB0_2:37; RV64ZDINX-NEXT: mv a0, a238; RV64ZDINX-NEXT: ret39 %1 = icmp eq i32 %a, %b40 %2 = select i1 %1, double %c, double %d41 ret double %242}43 44define double @select_icmp_ne(i32 signext %a, i32 signext %b, double %c, double %d) {45; CHECK-LABEL: select_icmp_ne:46; CHECK: # %bb.0:47; CHECK-NEXT: bne a0, a1, .LBB1_248; CHECK-NEXT: # %bb.1:49; CHECK-NEXT: fmv.d fa0, fa150; CHECK-NEXT: .LBB1_2:51; CHECK-NEXT: ret52;53; RV32ZDINX-LABEL: select_icmp_ne:54; RV32ZDINX: # %bb.0:55; RV32ZDINX-NEXT: bne a0, a1, .LBB1_256; RV32ZDINX-NEXT: # %bb.1:57; RV32ZDINX-NEXT: fmv.d a2, a458; RV32ZDINX-NEXT: .LBB1_2:59; RV32ZDINX-NEXT: mv a0, a260; RV32ZDINX-NEXT: mv a1, a361; RV32ZDINX-NEXT: ret62;63; RV64ZDINX-LABEL: select_icmp_ne:64; RV64ZDINX: # %bb.0:65; RV64ZDINX-NEXT: bne a0, a1, .LBB1_266; RV64ZDINX-NEXT: # %bb.1:67; RV64ZDINX-NEXT: mv a2, a368; RV64ZDINX-NEXT: .LBB1_2:69; RV64ZDINX-NEXT: mv a0, a270; RV64ZDINX-NEXT: ret71 %1 = icmp ne i32 %a, %b72 %2 = select i1 %1, double %c, double %d73 ret double %274}75 76define double @select_icmp_ugt(i32 signext %a, i32 signext %b, double %c, double %d) {77; CHECK-LABEL: select_icmp_ugt:78; CHECK: # %bb.0:79; CHECK-NEXT: bltu a1, a0, .LBB2_280; CHECK-NEXT: # %bb.1:81; CHECK-NEXT: fmv.d fa0, fa182; CHECK-NEXT: .LBB2_2:83; CHECK-NEXT: ret84;85; RV32ZDINX-LABEL: select_icmp_ugt:86; RV32ZDINX: # %bb.0:87; RV32ZDINX-NEXT: bltu a1, a0, .LBB2_288; RV32ZDINX-NEXT: # %bb.1:89; RV32ZDINX-NEXT: fmv.d a2, a490; RV32ZDINX-NEXT: .LBB2_2:91; RV32ZDINX-NEXT: mv a0, a292; RV32ZDINX-NEXT: mv a1, a393; RV32ZDINX-NEXT: ret94;95; RV64ZDINX-LABEL: select_icmp_ugt:96; RV64ZDINX: # %bb.0:97; RV64ZDINX-NEXT: bltu a1, a0, .LBB2_298; RV64ZDINX-NEXT: # %bb.1:99; RV64ZDINX-NEXT: mv a2, a3100; RV64ZDINX-NEXT: .LBB2_2:101; RV64ZDINX-NEXT: mv a0, a2102; RV64ZDINX-NEXT: ret103 %1 = icmp ugt i32 %a, %b104 %2 = select i1 %1, double %c, double %d105 ret double %2106}107 108define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double %d) {109; CHECK-LABEL: select_icmp_uge:110; CHECK: # %bb.0:111; CHECK-NEXT: bgeu a0, a1, .LBB3_2112; CHECK-NEXT: # %bb.1:113; CHECK-NEXT: fmv.d fa0, fa1114; CHECK-NEXT: .LBB3_2:115; CHECK-NEXT: ret116;117; RV32ZDINX-LABEL: select_icmp_uge:118; RV32ZDINX: # %bb.0:119; RV32ZDINX-NEXT: bgeu a0, a1, .LBB3_2120; RV32ZDINX-NEXT: # %bb.1:121; RV32ZDINX-NEXT: fmv.d a2, a4122; RV32ZDINX-NEXT: .LBB3_2:123; RV32ZDINX-NEXT: mv a0, a2124; RV32ZDINX-NEXT: mv a1, a3125; RV32ZDINX-NEXT: ret126;127; RV64ZDINX-LABEL: select_icmp_uge:128; RV64ZDINX: # %bb.0:129; RV64ZDINX-NEXT: bgeu a0, a1, .LBB3_2130; RV64ZDINX-NEXT: # %bb.1:131; RV64ZDINX-NEXT: mv a2, a3132; RV64ZDINX-NEXT: .LBB3_2:133; RV64ZDINX-NEXT: mv a0, a2134; RV64ZDINX-NEXT: ret135 %1 = icmp uge i32 %a, %b136 %2 = select i1 %1, double %c, double %d137 ret double %2138}139 140define double @select_icmp_ult(i32 signext %a, i32 signext %b, double %c, double %d) {141; CHECK-LABEL: select_icmp_ult:142; CHECK: # %bb.0:143; CHECK-NEXT: bltu a0, a1, .LBB4_2144; CHECK-NEXT: # %bb.1:145; CHECK-NEXT: fmv.d fa0, fa1146; CHECK-NEXT: .LBB4_2:147; CHECK-NEXT: ret148;149; RV32ZDINX-LABEL: select_icmp_ult:150; RV32ZDINX: # %bb.0:151; RV32ZDINX-NEXT: bltu a0, a1, .LBB4_2152; RV32ZDINX-NEXT: # %bb.1:153; RV32ZDINX-NEXT: fmv.d a2, a4154; RV32ZDINX-NEXT: .LBB4_2:155; RV32ZDINX-NEXT: mv a0, a2156; RV32ZDINX-NEXT: mv a1, a3157; RV32ZDINX-NEXT: ret158;159; RV64ZDINX-LABEL: select_icmp_ult:160; RV64ZDINX: # %bb.0:161; RV64ZDINX-NEXT: bltu a0, a1, .LBB4_2162; RV64ZDINX-NEXT: # %bb.1:163; RV64ZDINX-NEXT: mv a2, a3164; RV64ZDINX-NEXT: .LBB4_2:165; RV64ZDINX-NEXT: mv a0, a2166; RV64ZDINX-NEXT: ret167 %1 = icmp ult i32 %a, %b168 %2 = select i1 %1, double %c, double %d169 ret double %2170}171 172define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double %d) {173; CHECK-LABEL: select_icmp_ule:174; CHECK: # %bb.0:175; CHECK-NEXT: bgeu a1, a0, .LBB5_2176; CHECK-NEXT: # %bb.1:177; CHECK-NEXT: fmv.d fa0, fa1178; CHECK-NEXT: .LBB5_2:179; CHECK-NEXT: ret180;181; RV32ZDINX-LABEL: select_icmp_ule:182; RV32ZDINX: # %bb.0:183; RV32ZDINX-NEXT: bgeu a1, a0, .LBB5_2184; RV32ZDINX-NEXT: # %bb.1:185; RV32ZDINX-NEXT: fmv.d a2, a4186; RV32ZDINX-NEXT: .LBB5_2:187; RV32ZDINX-NEXT: mv a0, a2188; RV32ZDINX-NEXT: mv a1, a3189; RV32ZDINX-NEXT: ret190;191; RV64ZDINX-LABEL: select_icmp_ule:192; RV64ZDINX: # %bb.0:193; RV64ZDINX-NEXT: bgeu a1, a0, .LBB5_2194; RV64ZDINX-NEXT: # %bb.1:195; RV64ZDINX-NEXT: mv a2, a3196; RV64ZDINX-NEXT: .LBB5_2:197; RV64ZDINX-NEXT: mv a0, a2198; RV64ZDINX-NEXT: ret199 %1 = icmp ule i32 %a, %b200 %2 = select i1 %1, double %c, double %d201 ret double %2202}203 204define double @select_icmp_sgt(i32 signext %a, i32 signext %b, double %c, double %d) {205; CHECK-LABEL: select_icmp_sgt:206; CHECK: # %bb.0:207; CHECK-NEXT: blt a1, a0, .LBB6_2208; CHECK-NEXT: # %bb.1:209; CHECK-NEXT: fmv.d fa0, fa1210; CHECK-NEXT: .LBB6_2:211; CHECK-NEXT: ret212;213; RV32ZDINX-LABEL: select_icmp_sgt:214; RV32ZDINX: # %bb.0:215; RV32ZDINX-NEXT: blt a1, a0, .LBB6_2216; RV32ZDINX-NEXT: # %bb.1:217; RV32ZDINX-NEXT: fmv.d a2, a4218; RV32ZDINX-NEXT: .LBB6_2:219; RV32ZDINX-NEXT: mv a0, a2220; RV32ZDINX-NEXT: mv a1, a3221; RV32ZDINX-NEXT: ret222;223; RV64ZDINX-LABEL: select_icmp_sgt:224; RV64ZDINX: # %bb.0:225; RV64ZDINX-NEXT: blt a1, a0, .LBB6_2226; RV64ZDINX-NEXT: # %bb.1:227; RV64ZDINX-NEXT: mv a2, a3228; RV64ZDINX-NEXT: .LBB6_2:229; RV64ZDINX-NEXT: mv a0, a2230; RV64ZDINX-NEXT: ret231 %1 = icmp sgt i32 %a, %b232 %2 = select i1 %1, double %c, double %d233 ret double %2234}235 236define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double %d) {237; CHECK-LABEL: select_icmp_sge:238; CHECK: # %bb.0:239; CHECK-NEXT: bge a0, a1, .LBB7_2240; CHECK-NEXT: # %bb.1:241; CHECK-NEXT: fmv.d fa0, fa1242; CHECK-NEXT: .LBB7_2:243; CHECK-NEXT: ret244;245; RV32ZDINX-LABEL: select_icmp_sge:246; RV32ZDINX: # %bb.0:247; RV32ZDINX-NEXT: bge a0, a1, .LBB7_2248; RV32ZDINX-NEXT: # %bb.1:249; RV32ZDINX-NEXT: fmv.d a2, a4250; RV32ZDINX-NEXT: .LBB7_2:251; RV32ZDINX-NEXT: mv a0, a2252; RV32ZDINX-NEXT: mv a1, a3253; RV32ZDINX-NEXT: ret254;255; RV64ZDINX-LABEL: select_icmp_sge:256; RV64ZDINX: # %bb.0:257; RV64ZDINX-NEXT: bge a0, a1, .LBB7_2258; RV64ZDINX-NEXT: # %bb.1:259; RV64ZDINX-NEXT: mv a2, a3260; RV64ZDINX-NEXT: .LBB7_2:261; RV64ZDINX-NEXT: mv a0, a2262; RV64ZDINX-NEXT: ret263 %1 = icmp sge i32 %a, %b264 %2 = select i1 %1, double %c, double %d265 ret double %2266}267 268define double @select_icmp_slt(i32 signext %a, i32 signext %b, double %c, double %d) {269; CHECK-LABEL: select_icmp_slt:270; CHECK: # %bb.0:271; CHECK-NEXT: blt a0, a1, .LBB8_2272; CHECK-NEXT: # %bb.1:273; CHECK-NEXT: fmv.d fa0, fa1274; CHECK-NEXT: .LBB8_2:275; CHECK-NEXT: ret276;277; RV32ZDINX-LABEL: select_icmp_slt:278; RV32ZDINX: # %bb.0:279; RV32ZDINX-NEXT: blt a0, a1, .LBB8_2280; RV32ZDINX-NEXT: # %bb.1:281; RV32ZDINX-NEXT: fmv.d a2, a4282; RV32ZDINX-NEXT: .LBB8_2:283; RV32ZDINX-NEXT: mv a0, a2284; RV32ZDINX-NEXT: mv a1, a3285; RV32ZDINX-NEXT: ret286;287; RV64ZDINX-LABEL: select_icmp_slt:288; RV64ZDINX: # %bb.0:289; RV64ZDINX-NEXT: blt a0, a1, .LBB8_2290; RV64ZDINX-NEXT: # %bb.1:291; RV64ZDINX-NEXT: mv a2, a3292; RV64ZDINX-NEXT: .LBB8_2:293; RV64ZDINX-NEXT: mv a0, a2294; RV64ZDINX-NEXT: ret295 %1 = icmp slt i32 %a, %b296 %2 = select i1 %1, double %c, double %d297 ret double %2298}299 300define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double %d) {301; CHECK-LABEL: select_icmp_sle:302; CHECK: # %bb.0:303; CHECK-NEXT: bge a1, a0, .LBB9_2304; CHECK-NEXT: # %bb.1:305; CHECK-NEXT: fmv.d fa0, fa1306; CHECK-NEXT: .LBB9_2:307; CHECK-NEXT: ret308;309; RV32ZDINX-LABEL: select_icmp_sle:310; RV32ZDINX: # %bb.0:311; RV32ZDINX-NEXT: bge a1, a0, .LBB9_2312; RV32ZDINX-NEXT: # %bb.1:313; RV32ZDINX-NEXT: fmv.d a2, a4314; RV32ZDINX-NEXT: .LBB9_2:315; RV32ZDINX-NEXT: mv a0, a2316; RV32ZDINX-NEXT: mv a1, a3317; RV32ZDINX-NEXT: ret318;319; RV64ZDINX-LABEL: select_icmp_sle:320; RV64ZDINX: # %bb.0:321; RV64ZDINX-NEXT: bge a1, a0, .LBB9_2322; RV64ZDINX-NEXT: # %bb.1:323; RV64ZDINX-NEXT: mv a2, a3324; RV64ZDINX-NEXT: .LBB9_2:325; RV64ZDINX-NEXT: mv a0, a2326; RV64ZDINX-NEXT: ret327 %1 = icmp sle i32 %a, %b328 %2 = select i1 %1, double %c, double %d329 ret double %2330}331 332define double @select_icmp_slt_one(i32 signext %a) {333; CHECK-LABEL: select_icmp_slt_one:334; CHECK: # %bb.0:335; CHECK-NEXT: slti a0, a0, 1336; CHECK-NEXT: fcvt.d.w fa0, a0337; CHECK-NEXT: ret338;339; RV32ZDINX-LABEL: select_icmp_slt_one:340; RV32ZDINX: # %bb.0:341; RV32ZDINX-NEXT: slti a0, a0, 1342; RV32ZDINX-NEXT: fcvt.d.w a0, a0343; RV32ZDINX-NEXT: ret344;345; RV64ZDINX-LABEL: select_icmp_slt_one:346; RV64ZDINX: # %bb.0:347; RV64ZDINX-NEXT: slti a0, a0, 1348; RV64ZDINX-NEXT: fcvt.d.w a0, a0349; RV64ZDINX-NEXT: ret350 %1 = icmp slt i32 %a, 1351 %2 = select i1 %1, double 1.000000e+00, double 0.000000e+00352 ret double %2353}354 355define double @select_icmp_sgt_zero(i32 signext %a) {356; CHECK-LABEL: select_icmp_sgt_zero:357; CHECK: # %bb.0:358; CHECK-NEXT: slti a0, a0, 1359; CHECK-NEXT: fcvt.d.w fa0, a0360; CHECK-NEXT: ret361;362; RV32ZDINX-LABEL: select_icmp_sgt_zero:363; RV32ZDINX: # %bb.0:364; RV32ZDINX-NEXT: slti a0, a0, 1365; RV32ZDINX-NEXT: fcvt.d.w a0, a0366; RV32ZDINX-NEXT: ret367;368; RV64ZDINX-LABEL: select_icmp_sgt_zero:369; RV64ZDINX: # %bb.0:370; RV64ZDINX-NEXT: slti a0, a0, 1371; RV64ZDINX-NEXT: fcvt.d.w a0, a0372; RV64ZDINX-NEXT: ret373 %1 = icmp sgt i32 %a, 0374 %2 = select i1 %1, double 0.000000e+00, double 1.000000e+00375 ret double %2376}377