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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646 7define float @add_f32(<4 x float> %a, <4 x float> %b) {8; CHECK-LABEL: add_f32:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma11; CHECK-NEXT: vfadd.vv v8, v8, v912; CHECK-NEXT: vmv.s.x v9, zero13; CHECK-NEXT: vfredusum.vs v8, v8, v914; CHECK-NEXT: vfmv.f.s fa0, v815; CHECK-NEXT: ret16 %r1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %a)17 %r2 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %b)18 %r = fadd fast float %r1, %r219 ret float %r20}21 22define float @fmul_f32(<4 x float> %a, <4 x float> %b) {23; CHECK-LABEL: fmul_f32:24; CHECK: # %bb.0:25; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma26; CHECK-NEXT: vslidedown.vi v10, v8, 227; CHECK-NEXT: vfmul.vv v8, v8, v1028; CHECK-NEXT: vslidedown.vi v10, v9, 229; CHECK-NEXT: vfmul.vv v9, v9, v1030; CHECK-NEXT: vrgather.vi v10, v8, 131; CHECK-NEXT: vfmul.vv v8, v8, v1032; CHECK-NEXT: vrgather.vi v10, v9, 133; CHECK-NEXT: vfmul.vv v9, v9, v1034; CHECK-NEXT: vfmv.f.s fa5, v835; CHECK-NEXT: vfmv.f.s fa4, v936; CHECK-NEXT: fmul.s fa0, fa5, fa437; CHECK-NEXT: ret38 %r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)39 %r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b)40 %r = fmul fast float %r1, %r241 ret float %r42}43 44define float @fmin_f32(<4 x float> %a, <4 x float> %b) {45; CHECK-LABEL: fmin_f32:46; CHECK: # %bb.0:47; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma48; CHECK-NEXT: vfmin.vv v8, v8, v949; CHECK-NEXT: vfredmin.vs v8, v8, v850; CHECK-NEXT: vfmv.f.s fa0, v851; CHECK-NEXT: ret52 %r1 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)53 %r2 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %b)54 %r = call float @llvm.minnum.f32(float %r1, float %r2)55 ret float %r56}57 58define float @fmax_f32(<4 x float> %a, <4 x float> %b) {59; CHECK-LABEL: fmax_f32:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma62; CHECK-NEXT: vfmax.vv v8, v8, v963; CHECK-NEXT: vfredmax.vs v8, v8, v864; CHECK-NEXT: vfmv.f.s fa0, v865; CHECK-NEXT: ret66 %r1 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)67 %r2 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %b)68 %r = call float @llvm.maxnum.f32(float %r1, float %r2)69 ret float %r70}71 72define i32 @add_i32(<4 x i32> %a, <4 x i32> %b) {73; CHECK-LABEL: add_i32:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma76; CHECK-NEXT: vadd.vv v8, v8, v977; CHECK-NEXT: vmv.s.x v9, zero78; CHECK-NEXT: vredsum.vs v8, v8, v979; CHECK-NEXT: vmv.x.s a0, v880; CHECK-NEXT: ret81 %r1 = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %a)82 %r2 = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %b)83 %r = add i32 %r1, %r284 ret i32 %r85}86 87define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) {88; CHECK-LABEL: add_ext_i16:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma91; CHECK-NEXT: vwaddu.vv v10, v8, v992; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma93; CHECK-NEXT: vmv.s.x v8, zero94; CHECK-NEXT: vredsum.vs v8, v10, v895; CHECK-NEXT: vmv.x.s a0, v896; CHECK-NEXT: ret97 %ae = zext <16 x i8> %a to <16 x i16>98 %be = zext <16 x i8> %b to <16 x i16>99 %r1 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %ae)100 %r2 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %be)101 %r = add i16 %r1, %r2102 ret i16 %r103}104 105define i16 @add_ext_v32i16(<32 x i8> %a, <16 x i8> %b) {106; CHECK-LABEL: add_ext_v32i16:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetivli zero, 16, e16, m1, ta, ma109; CHECK-NEXT: vmv.s.x v11, zero110; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma111; CHECK-NEXT: vwredsumu.vs v10, v10, v11112; CHECK-NEXT: li a0, 32113; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma114; CHECK-NEXT: vwredsumu.vs v8, v8, v10115; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma116; CHECK-NEXT: vmv.x.s a0, v8117; CHECK-NEXT: ret118 %ae = zext <32 x i8> %a to <32 x i16>119 %be = zext <16 x i8> %b to <16 x i16>120 %r1 = call i16 @llvm.vector.reduce.add.i16.v32i16(<32 x i16> %ae)121 %r2 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %be)122 %r = add i16 %r1, %r2123 ret i16 %r124}125 126define i32 @mul_i32(<4 x i32> %a, <4 x i32> %b) {127; RV32-LABEL: mul_i32:128; RV32: # %bb.0:129; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma130; RV32-NEXT: vslidedown.vi v10, v8, 2131; RV32-NEXT: vmul.vv v8, v8, v10132; RV32-NEXT: vslidedown.vi v10, v9, 2133; RV32-NEXT: vmul.vv v9, v9, v10134; RV32-NEXT: vrgather.vi v10, v8, 1135; RV32-NEXT: vmul.vv v8, v8, v10136; RV32-NEXT: vrgather.vi v10, v9, 1137; RV32-NEXT: vmul.vv v9, v9, v10138; RV32-NEXT: vmv.x.s a0, v8139; RV32-NEXT: vmv.x.s a1, v9140; RV32-NEXT: mul a0, a0, a1141; RV32-NEXT: ret142;143; RV64-LABEL: mul_i32:144; RV64: # %bb.0:145; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma146; RV64-NEXT: vslidedown.vi v10, v8, 2147; RV64-NEXT: vmul.vv v8, v8, v10148; RV64-NEXT: vslidedown.vi v10, v9, 2149; RV64-NEXT: vmul.vv v9, v9, v10150; RV64-NEXT: vrgather.vi v10, v8, 1151; RV64-NEXT: vmul.vv v8, v8, v10152; RV64-NEXT: vrgather.vi v10, v9, 1153; RV64-NEXT: vmul.vv v9, v9, v10154; RV64-NEXT: vmv.x.s a0, v8155; RV64-NEXT: vmv.x.s a1, v9156; RV64-NEXT: mulw a0, a0, a1157; RV64-NEXT: ret158 %r1 = call i32 @llvm.vector.reduce.mul.i32.v4i32(<4 x i32> %a)159 %r2 = call i32 @llvm.vector.reduce.mul.i32.v4i32(<4 x i32> %b)160 %r = mul i32 %r1, %r2161 ret i32 %r162}163 164define i32 @and_i32(<4 x i32> %a, <4 x i32> %b) {165; CHECK-LABEL: and_i32:166; CHECK: # %bb.0:167; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma168; CHECK-NEXT: vand.vv v8, v8, v9169; CHECK-NEXT: vredand.vs v8, v8, v8170; CHECK-NEXT: vmv.x.s a0, v8171; CHECK-NEXT: ret172 %r1 = call i32 @llvm.vector.reduce.and.i32.v4i32(<4 x i32> %a)173 %r2 = call i32 @llvm.vector.reduce.and.i32.v4i32(<4 x i32> %b)174 %r = and i32 %r1, %r2175 ret i32 %r176}177 178define i32 @or_i32(<4 x i32> %a, <4 x i32> %b) {179; CHECK-LABEL: or_i32:180; CHECK: # %bb.0:181; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma182; CHECK-NEXT: vor.vv v8, v8, v9183; CHECK-NEXT: vredor.vs v8, v8, v8184; CHECK-NEXT: vmv.x.s a0, v8185; CHECK-NEXT: ret186 %r1 = call i32 @llvm.vector.reduce.or.i32.v4i32(<4 x i32> %a)187 %r2 = call i32 @llvm.vector.reduce.or.i32.v4i32(<4 x i32> %b)188 %r = or i32 %r1, %r2189 ret i32 %r190}191 192define i32 @xor_i32(<4 x i32> %a, <4 x i32> %b) {193; CHECK-LABEL: xor_i32:194; CHECK: # %bb.0:195; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma196; CHECK-NEXT: vxor.vv v8, v8, v9197; CHECK-NEXT: vmv.s.x v9, zero198; CHECK-NEXT: vredxor.vs v8, v8, v9199; CHECK-NEXT: vmv.x.s a0, v8200; CHECK-NEXT: ret201 %r1 = call i32 @llvm.vector.reduce.xor.i32.v4i32(<4 x i32> %a)202 %r2 = call i32 @llvm.vector.reduce.xor.i32.v4i32(<4 x i32> %b)203 %r = xor i32 %r1, %r2204 ret i32 %r205}206 207define i32 @umin_i32(<4 x i32> %a, <4 x i32> %b) {208; CHECK-LABEL: umin_i32:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma211; CHECK-NEXT: vminu.vv v8, v8, v9212; CHECK-NEXT: vredminu.vs v8, v8, v8213; CHECK-NEXT: vmv.x.s a0, v8214; CHECK-NEXT: ret215 %r1 = call i32 @llvm.vector.reduce.umin.i32.v4i32(<4 x i32> %a)216 %r2 = call i32 @llvm.vector.reduce.umin.i32.v4i32(<4 x i32> %b)217 %r = call i32 @llvm.umin.i32(i32 %r1, i32 %r2)218 ret i32 %r219}220 221define i32 @umax_i32(<4 x i32> %a, <4 x i32> %b) {222; CHECK-LABEL: umax_i32:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma225; CHECK-NEXT: vmaxu.vv v8, v8, v9226; CHECK-NEXT: vredmaxu.vs v8, v8, v8227; CHECK-NEXT: vmv.x.s a0, v8228; CHECK-NEXT: ret229 %r1 = call i32 @llvm.vector.reduce.umax.i32.v4i32(<4 x i32> %a)230 %r2 = call i32 @llvm.vector.reduce.umax.i32.v4i32(<4 x i32> %b)231 %r = call i32 @llvm.umax.i32(i32 %r1, i32 %r2)232 ret i32 %r233}234 235define i32 @smin_i32(<4 x i32> %a, <4 x i32> %b) {236; CHECK-LABEL: smin_i32:237; CHECK: # %bb.0:238; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma239; CHECK-NEXT: vmin.vv v8, v8, v9240; CHECK-NEXT: vredmin.vs v8, v8, v8241; CHECK-NEXT: vmv.x.s a0, v8242; CHECK-NEXT: ret243 %r1 = call i32 @llvm.vector.reduce.smin.i32.v4i32(<4 x i32> %a)244 %r2 = call i32 @llvm.vector.reduce.smin.i32.v4i32(<4 x i32> %b)245 %r = call i32 @llvm.smin.i32(i32 %r1, i32 %r2)246 ret i32 %r247}248 249define i32 @smax_i32(<4 x i32> %a, <4 x i32> %b) {250; CHECK-LABEL: smax_i32:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma253; CHECK-NEXT: vmax.vv v8, v8, v9254; CHECK-NEXT: vredmax.vs v8, v8, v8255; CHECK-NEXT: vmv.x.s a0, v8256; CHECK-NEXT: ret257 %r1 = call i32 @llvm.vector.reduce.smax.i32.v4i32(<4 x i32> %a)258 %r2 = call i32 @llvm.vector.reduce.smax.i32.v4i32(<4 x i32> %b)259 %r = call i32 @llvm.smax.i32(i32 %r1, i32 %r2)260 ret i32 %r261}262 263