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1; RUN: llc -mtriple=riscv32 -mattr=help 2>&1 | FileCheck %s2; RUN: llc -mtriple=riscv64 -mattr=help 2>&1 | FileCheck %s3 4; CHECK: Available features for this target:5; CHECK-EMPTY:6; CHECK-NEXT: 32bit - Implements RV32.7; CHECK-NEXT: 64bit - Implements RV64.8; CHECK-NEXT: a - 'A' (Atomic Instructions).9; CHECK-NEXT: add-load-fusion - Enable ADD(.UW) + load macrofusion.10; CHECK-NEXT: addi-load-fusion - Enable ADDI + load macrofusion.11; CHECK-NEXT: andes45 - Andes 45-Series processors.12; CHECK-NEXT: auipc-addi-fusion - Enable AUIPC+ADDI macrofusion.13; CHECK-NEXT: auipc-load-fusion - Enable AUIPC + load macrofusion.14; CHECK-NEXT: b - 'B' (the collection of the Zba, Zbb, Zbs extensions).15; CHECK-NEXT: bfext-fusion - Enable SLLI+SRLI (bitfield extract) macrofusion.16; CHECK-NEXT: c - 'C' (Compressed Instructions).17; CHECK-NEXT: conditional-cmv-fusion - Enable branch+c.mv fusion.18; CHECK-NEXT: d - 'D' (Double-Precision Floating-Point).19; CHECK-NEXT: disable-latency-sched-heuristic - Disable latency scheduling heuristic.20; CHECK-NEXT: disable-misched-load-clustering - Disable load clustering in the machine scheduler.21; CHECK-NEXT: disable-misched-store-clustering - Disable store clustering in the machine scheduler.22; CHECK-NEXT: disable-postmisched-load-clustering - Disable PostRA load clustering in the machine scheduler.23; CHECK-NEXT: disable-postmisched-store-clustering - Disable PostRA store clustering in the machine scheduler.24; CHECK-NEXT: dlen-factor-2 - Vector unit DLEN(data path width) is half of VLEN.25; CHECK-NEXT: e - 'E' (Embedded Instruction Set with 16 GPRs).26; CHECK-NEXT: exact-asm - Enable Exact Assembly (Disables Compression and Relaxation).27; CHECK-NEXT: experimental - Experimental intrinsics.28; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)).29; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.30; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension).31; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).32; CHECK-NEXT: experimental-xqccmp - 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves).33; CHECK-NEXT: experimental-xqcia - 'Xqcia' (Qualcomm uC Arithmetic Extension).34; CHECK-NEXT: experimental-xqciac - 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension).35; CHECK-NEXT: experimental-xqcibi - 'Xqcibi' (Qualcomm uC Branch Immediate Extension).36; CHECK-NEXT: experimental-xqcibm - 'Xqcibm' (Qualcomm uC Bit Manipulation Extension).37; CHECK-NEXT: experimental-xqcicli - 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension).38; CHECK-NEXT: experimental-xqcicm - 'Xqcicm' (Qualcomm uC Conditional Move Extension).39; CHECK-NEXT: experimental-xqcics - 'Xqcics' (Qualcomm uC Conditional Select Extension).40; CHECK-NEXT: experimental-xqcicsr - 'Xqcicsr' (Qualcomm uC CSR Extension).41; CHECK-NEXT: experimental-xqciint - 'Xqciint' (Qualcomm uC Interrupts Extension).42; CHECK-NEXT: experimental-xqciio - 'Xqciio' (Qualcomm uC External Input Output Extension).43; CHECK-NEXT: experimental-xqcilb - 'Xqcilb' (Qualcomm uC Long Branch Extension).44; CHECK-NEXT: experimental-xqcili - 'Xqcili' (Qualcomm uC Load Large Immediate Extension).45; CHECK-NEXT: experimental-xqcilia - 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension).46; CHECK-NEXT: experimental-xqcilo - 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension).47; CHECK-NEXT: experimental-xqcilsm - 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension).48; CHECK-NEXT: experimental-xqcisim - 'Xqcisim' (Qualcomm uC Simulation Hint Extension).49; CHECK-NEXT: experimental-xqcisls - 'Xqcisls' (Qualcomm uC Scaled Load Store Extension).50; CHECK-NEXT: experimental-xqcisync - 'Xqcisync' (Qualcomm uC Sync Delay Extension).51; CHECK-NEXT: experimental-xrivosvisni - 'XRivosVisni' (Rivos Vector Integer Small New).52; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips).53; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).54; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs).55; CHECK-NEXT: experimental-zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions).56; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate).57; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad).58; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack).59; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements).60; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support).61; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts).62; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).63; CHECK-NEXT: experimental-zvqdotq - 'Zvqdotq' (Vector quad widening 4D Dot Product).64; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point).65; CHECK-NEXT: forced-atomics - Assume that lock-free native-width atomics are available.66; CHECK-NEXT: h - 'H' (Hypervisor).67; CHECK-NEXT: i - 'I' (Base Integer Instruction Set).68; CHECK-NEXT: ld-add-fusion - Enable LD+ADD macrofusion.69; CHECK-NEXT: log-vrgather - Has vrgather.vv with LMUL*log2(LMUL) latency70; CHECK-NEXT: lui-addi-fusion - Enable LUI+ADDI macro fusion.71; CHECK-NEXT: lui-load-fusion - Enable LUI + load macrofusion.72; CHECK-NEXT: m - 'M' (Integer Multiplication and Division).73; CHECK-NEXT: mips-p8700 - MIPS p8700 processor.74; CHECK-NEXT: no-default-unroll - Disable default unroll preference..75; CHECK-NEXT: no-sink-splat-operands - Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions.76; CHECK-NEXT: no-trailing-seq-cst-fence - Disable trailing fence for seq-cst store..77; CHECK-NEXT: optimized-nf2-segment-load-store - vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle.78; CHECK-NEXT: optimized-nf3-segment-load-store - vlseg3eN.v and vsseg3eN.v are implemented as a wide memory op and shuffle.79; CHECK-NEXT: optimized-nf4-segment-load-store - vlseg4eN.v and vsseg4eN.v are implemented as a wide memory op and shuffle.80; CHECK-NEXT: optimized-nf5-segment-load-store - vlseg5eN.v and vsseg5eN.v are implemented as a wide memory op and shuffle.81; CHECK-NEXT: optimized-nf6-segment-load-store - vlseg6eN.v and vsseg6eN.v are implemented as a wide memory op and shuffle.82; CHECK-NEXT: optimized-nf7-segment-load-store - vlseg7eN.v and vsseg7eN.v are implemented as a wide memory op and shuffle.83; CHECK-NEXT: optimized-nf8-segment-load-store - vlseg8eN.v and vsseg8eN.v are implemented as a wide memory op and shuffle.84; CHECK-NEXT: optimized-zero-stride-load - Optimized (perform fewer memory operations)zero-stride vector load.85; CHECK-NEXT: permissive-zalrsc - Implementation permits non-base instructions between LR/SC pairs.86; CHECK-NEXT: predictable-select-expensive - Prefer likely predicted branches over selects.87; CHECK-NEXT: prefer-vsetvli-over-read-vlenb - Prefer vsetvli over read vlenb CSR to calculate VLEN.88; CHECK-NEXT: prefer-w-inst - Prefer instructions with W suffix.89; CHECK-NEXT: q - 'Q' (Quad-Precision Floating-Point).90; CHECK-NEXT: relax - Enable Linker relaxation..91; CHECK-NEXT: reserve-x1 - Reserve X1.92; CHECK-NEXT: reserve-x10 - Reserve X10.93; CHECK-NEXT: reserve-x11 - Reserve X11.94; CHECK-NEXT: reserve-x12 - Reserve X12.95; CHECK-NEXT: reserve-x13 - Reserve X13.96; CHECK-NEXT: reserve-x14 - Reserve X14.97; CHECK-NEXT: reserve-x15 - Reserve X15.98; CHECK-NEXT: reserve-x16 - Reserve X16.99; CHECK-NEXT: reserve-x17 - Reserve X17.100; CHECK-NEXT: reserve-x18 - Reserve X18.101; CHECK-NEXT: reserve-x19 - Reserve X19.102; CHECK-NEXT: reserve-x2 - Reserve X2.103; CHECK-NEXT: reserve-x20 - Reserve X20.104; CHECK-NEXT: reserve-x21 - Reserve X21.105; CHECK-NEXT: reserve-x22 - Reserve X22.106; CHECK-NEXT: reserve-x23 - Reserve X23.107; CHECK-NEXT: reserve-x24 - Reserve X24.108; CHECK-NEXT: reserve-x25 - Reserve X25.109; CHECK-NEXT: reserve-x26 - Reserve X26.110; CHECK-NEXT: reserve-x27 - Reserve X27.111; CHECK-NEXT: reserve-x28 - Reserve X28.112; CHECK-NEXT: reserve-x29 - Reserve X29.113; CHECK-NEXT: reserve-x3 - Reserve X3.114; CHECK-NEXT: reserve-x30 - Reserve X30.115; CHECK-NEXT: reserve-x31 - Reserve X31.116; CHECK-NEXT: reserve-x4 - Reserve X4.117; CHECK-NEXT: reserve-x5 - Reserve X5.118; CHECK-NEXT: reserve-x6 - Reserve X6.119; CHECK-NEXT: reserve-x7 - Reserve X7.120; CHECK-NEXT: reserve-x8 - Reserve X8.121; CHECK-NEXT: reserve-x9 - Reserve X9.122; CHECK-NEXT: rva20s64 - RISC-V rva20s64 profile.123; CHECK-NEXT: rva20u64 - RISC-V rva20u64 profile.124; CHECK-NEXT: rva22s64 - RISC-V rva22s64 profile.125; CHECK-NEXT: rva22u64 - RISC-V rva22u64 profile.126; CHECK-NEXT: rva23s64 - RISC-V rva23s64 profile.127; CHECK-NEXT: rva23u64 - RISC-V rva23u64 profile.128; CHECK-NEXT: rvb23s64 - RISC-V rvb23s64 profile.129; CHECK-NEXT: rvb23u64 - RISC-V rvb23u64 profile.130; CHECK-NEXT: rvi20u32 - RISC-V rvi20u32 profile.131; CHECK-NEXT: rvi20u64 - RISC-V rvi20u64 profile.132; CHECK-NEXT: save-restore - Enable save/restore..133; CHECK-NEXT: sdext - 'Sdext' (External debugger).134; CHECK-NEXT: sdtrig - 'Sdtrig' (Debugger triggers).135; CHECK-NEXT: sha - 'Sha' (Augmented Hypervisor).136; CHECK-NEXT: shcounterenw - 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero).137; CHECK-NEXT: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare).138; CHECK-NEXT: shifted-zextw-fusion - Enable SLLI+SRLI to be fused when computing (shifted) word zero extension.139; CHECK-NEXT: shlcofideleg - 'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode).140; CHECK-NEXT: short-forward-branch-ialu - Enable short forward branch optimization for RVI base instructions.141; CHECK-NEXT: short-forward-branch-iminmax - Enable short forward branch optimization for MIN,MAX instructions in Zbb.142; CHECK-NEXT: short-forward-branch-imul - Enable short forward branch optimization for MUL instruction.143; CHECK-NEXT: shtvala - 'Shtvala' (htval provides all needed values).144; CHECK-NEXT: shvsatpa - 'Shvsatpa' (vsatp supports all modes supported by satp).145; CHECK-NEXT: shvstvala - 'Shvstvala' (vstval provides all needed values).146; CHECK-NEXT: shvstvecd - 'Shvstvecd' (vstvec supports Direct mode).147; CHECK-NEXT: shxadd-load-fusion - Enable SH(1|2|3)ADD(.UW) + load macrofusion.148; CHECK-NEXT: sifive7 - SiFive 7-Series processors.149; CHECK-NEXT: single-element-vec-fp64 - Certain vector FP64 operations produce a single result element per cycle.150; CHECK-NEXT: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level).151; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level).152; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering).153; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level).154; CHECK-NEXT: smctr - 'Smctr' (Control Transfer Records Machine Level).155; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap Machine Level).156; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection).157; CHECK-NEXT: smmpm - 'Smmpm' (Machine-level Pointer Masking for M-mode).158; CHECK-NEXT: smnpm - 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode).159; CHECK-NEXT: smrnmi - 'Smrnmi' (Resumable Non-Maskable Interrupts).160; CHECK-NEXT: smstateen - 'Smstateen' (Machine-mode view of the state-enable extension).161; CHECK-NEXT: ssaia - 'Ssaia' (Advanced Interrupt Architecture Supervisor Level).162; CHECK-NEXT: ssccfg - 'Ssccfg' (Counter Configuration Supervisor Level).163; CHECK-NEXT: ssccptr - 'Ssccptr' (Main memory supports page table reads).164; CHECK-NEXT: sscofpmf - 'Sscofpmf' (Count Overflow and Mode-Based Filtering).165; CHECK-NEXT: sscounterenw - 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero).166; CHECK-NEXT: sscsrind - 'Sscsrind' (Indirect CSR Access Supervisor Level).167; CHECK-NEXT: ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).168; CHECK-NEXT: ssdbltrp - 'Ssdbltrp' (Double Trap Supervisor Level).169; CHECK-NEXT: ssnpm - 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode).170; CHECK-NEXT: sspm - 'Sspm' (Indicates Supervisor-mode Pointer Masking).171; CHECK-NEXT: ssqosid - 'Ssqosid' (Quality-of-Service (QoS) Identifiers).172; CHECK-NEXT: ssstateen - 'Ssstateen' (Supervisor-mode view of the state-enable extension).173; CHECK-NEXT: ssstrict - 'Ssstrict' (No non-conforming extensions are present).174; CHECK-NEXT: sstc - 'Sstc' (Supervisor-mode timer interrupts).175; CHECK-NEXT: sstvala - 'Sstvala' (stval provides all needed values).176; CHECK-NEXT: sstvecd - 'Sstvecd' (stvec supports Direct mode).177; CHECK-NEXT: ssu64xl - 'Ssu64xl' (UXLEN=64 supported).178; CHECK-NEXT: supm - 'Supm' (Indicates User-mode Pointer Masking).179; CHECK-NEXT: svade - 'Svade' (Raise exceptions on improper A/D bits).180; CHECK-NEXT: svadu - 'Svadu' (Hardware A/D updates).181; CHECK-NEXT: svbare - 'Svbare' (satp mode Bare supported).182; CHECK-NEXT: svinval - 'Svinval' (Fine-Grained Address-Translation Cache Invalidation).183; CHECK-NEXT: svnapot - 'Svnapot' (NAPOT Translation Contiguity).184; CHECK-NEXT: svpbmt - 'Svpbmt' (Page-Based Memory Types).185; CHECK-NEXT: svvptc - 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid).186; CHECK-NEXT: tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits.187; CHECK-NEXT: unaligned-scalar-mem - Has reasonably performant unaligned scalar loads and stores.188; CHECK-NEXT: unaligned-vector-mem - Has reasonably performant unaligned vector loads and stores.189; CHECK-NEXT: use-postra-scheduler - Schedule again after register allocation.190; CHECK-NEXT: v - 'V' (Vector Extension for Application Processors).191; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors.192; CHECK-NEXT: vl-dependent-latency - Latency of vector instructions is dependent on the dynamic value of vl.193; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush.194; CHECK-NEXT: xandesbfhcvt - 'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension).195; CHECK-NEXT: xandesperf - 'XAndesPerf' (Andes Performance Extension).196; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension).197; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension).198; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension).199; CHECK-NEXT: xandesvsinth - 'XAndesVSIntH' (Andes Vector Small INT Handling Extension).200; CHECK-NEXT: xandesvsintload - 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension).201; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations).202; CHECK-NEXT: xcvbi - 'XCVbi' (CORE-V Immediate Branching).203; CHECK-NEXT: xcvbitmanip - 'XCVbitmanip' (CORE-V Bit Manipulation).204; CHECK-NEXT: xcvelw - 'XCVelw' (CORE-V Event Load Word).205; CHECK-NEXT: xcvmac - 'XCVmac' (CORE-V Multiply-Accumulate).206; CHECK-NEXT: xcvmem - 'XCVmem' (CORE-V Post-incrementing Load & Store).207; CHECK-NEXT: xcvsimd - 'XCVsimd' (CORE-V SIMD ALU).208; CHECK-NEXT: xmipscbop - 'XMIPSCBOP' (MIPS Software Prefetch).209; CHECK-NEXT: xmipscmov - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)).210; CHECK-NEXT: mipsexectl - 'XMIPSEXECTL' (MIPS execution control).211; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding).212; CHECK-NEXT: xsfcease - 'XSfcease' (SiFive sf.cease Instruction).213; CHECK-NEXT: xsfmm128t - 'XSfmm128t' (TE=128 configuration).214; CHECK-NEXT: xsfmm16t - 'XSfmm16t' (TE=16 configuration).215; CHECK-NEXT: xsfmm32a16f - 'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)). 216; CHECK-NEXT: xsfmm32a32f - 'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b). 217; CHECK-NEXT: xsfmm32a8f - 'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8). 218; CHECK-NEXT: xsfmm32a8i - 'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b). 219; CHECK-NEXT: xsfmm32t - 'XSfmm32t' (TE=32 configuration). 220; CHECK-NEXT: xsfmm64a64f - 'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64). 221; CHECK-NEXT: xsfmm64t - 'XSfmm64t' (TE=64 configuration). 222; CHECK-NEXT: xsfmmbase - 'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero).223; CHECK-NEXT: xsfvcp - 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions).224; CHECK-NEXT: xsfvfbfexp16e - 'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16).225; CHECK-NEXT: xsfvfexp16e - 'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision).226; CHECK-NEXT: xsfvfexp32e - 'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision).227; CHECK-NEXT: xsfvfexpa - 'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction).228; CHECK-NEXT: xsfvfexpa64e - 'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision).229; CHECK-NEXT: xsfvfnrclipxfqf - 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions).230; CHECK-NEXT: xsfvfwmaccqqq - 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4)).231; CHECK-NEXT: xsfvqmaccdod - 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)).232; CHECK-NEXT: xsfvqmaccqoq - 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)).233; CHECK-NEXT: xsifivecdiscarddlone - 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction).234; CHECK-NEXT: xsifivecflushdlone - 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction).235; CHECK-NEXT: xsmtvdot - 'XSMTVDot' (SpacemiT Vector Dot Product Extension).236; CHECK-NEXT: xtheadba - 'XTHeadBa' (T-Head address calculation instructions).237; CHECK-NEXT: xtheadbb - 'XTHeadBb' (T-Head basic bit-manipulation instructions).238; CHECK-NEXT: xtheadbs - 'XTHeadBs' (T-Head single-bit instructions).239; CHECK-NEXT: xtheadcmo - 'XTHeadCmo' (T-Head cache management instructions).240; CHECK-NEXT: xtheadcondmov - 'XTHeadCondMov' (T-Head conditional move instructions).241; CHECK-NEXT: xtheadfmemidx - 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations).242; CHECK-NEXT: xtheadmac - 'XTHeadMac' (T-Head Multiply-Accumulate Instructions).243; CHECK-NEXT: xtheadmemidx - 'XTHeadMemIdx' (T-Head Indexed Memory Operations).244; CHECK-NEXT: xtheadmempair - 'XTHeadMemPair' (T-Head two-GPR Memory Operations).245; CHECK-NEXT: xtheadsync - 'XTHeadSync' (T-Head multicore synchronization instructions).246; CHECK-NEXT: xtheadvdot - 'XTHeadVdot' (T-Head Vector Extensions for Dot).247; CHECK-NEXT: xventanacondops - 'XVentanaCondOps' (Ventana Conditional Ops).248; CHECK-NEXT: xwchc - 'Xwchc' (WCH/QingKe additional compressed opcodes).249; CHECK-NEXT: za128rs - 'Za128rs' (Reservation Set Size of at Most 128 Bytes).250; CHECK-NEXT: za64rs - 'Za64rs' (Reservation Set Size of at Most 64 Bytes).251; CHECK-NEXT: zaamo - 'Zaamo' (Atomic Memory Operations).252; CHECK-NEXT: zabha - 'Zabha' (Byte and Halfword Atomic Memory Operations).253; CHECK-NEXT: zacas - 'Zacas' (Atomic Compare-And-Swap Instructions).254; CHECK-NEXT: zalrsc - 'Zalrsc' (Load-Reserved/Store-Conditional).255; CHECK-NEXT: zama16b - 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs).256; CHECK-NEXT: zawrs - 'Zawrs' (Wait on Reservation Set).257; CHECK-NEXT: zba - 'Zba' (Address Generation Instructions).258; CHECK-NEXT: zbb - 'Zbb' (Basic Bit-Manipulation).259; CHECK-NEXT: zbc - 'Zbc' (Carry-Less Multiplication).260; CHECK-NEXT: zbkb - 'Zbkb' (Bitmanip instructions for Cryptography).261; CHECK-NEXT: zbkc - 'Zbkc' (Carry-less multiply instructions for Cryptography).262; CHECK-NEXT: zbkx - 'Zbkx' (Crossbar permutation instructions).263; CHECK-NEXT: zbs - 'Zbs' (Single-Bit Instructions).264; CHECK-NEXT: zca - 'Zca' (part of the C extension, excluding compressed floating point loads/stores).265; CHECK-NEXT: zcb - 'Zcb' (Compressed basic bit manipulation instructions).266; CHECK-NEXT: zcd - 'Zcd' (Compressed Double-Precision Floating-Point Instructions).267; CHECK-NEXT: zce - 'Zce' (Compressed extensions for microcontrollers).268; CHECK-NEXT: zcf - 'Zcf' (Compressed Single-Precision Floating-Point Instructions).269; CHECK-NEXT: zclsd - 'Zclsd' (Compressed Load/Store Pair Instructions).270; CHECK-NEXT: zcmop - 'Zcmop' (Compressed May-Be-Operations).271; CHECK-NEXT: zcmp - 'Zcmp' (sequenced instructions for code-size reduction).272; CHECK-NEXT: zcmt - 'Zcmt' (table jump instructions for code-size reduction).273; CHECK-NEXT: zdinx - 'Zdinx' (Double in Integer).274; CHECK-NEXT: zexth-fusion - Enable SLLI+SRLI to be fused to zero extension of halfword.275; CHECK-NEXT: zextw-fusion - Enable SLLI+SRLI to be fused to zero extension of word.276; CHECK-NEXT: zfa - 'Zfa' (Additional Floating-Point).277; CHECK-NEXT: zfbfmin - 'Zfbfmin' (Scalar BF16 Converts).278; CHECK-NEXT: zfh - 'Zfh' (Half-Precision Floating-Point).279; CHECK-NEXT: zfhmin - 'Zfhmin' (Half-Precision Floating-Point Minimal).280; CHECK-NEXT: zfinx - 'Zfinx' (Float in Integer).281; CHECK-NEXT: zhinx - 'Zhinx' (Half Float in Integer).282; CHECK-NEXT: zhinxmin - 'Zhinxmin' (Half Float in Integer Minimal).283; CHECK-NEXT: zic64b - 'Zic64b' (Cache Block Size Is 64 Bytes).284; CHECK-NEXT: zicbom - 'Zicbom' (Cache-Block Management Instructions).285; CHECK-NEXT: zicbop - 'Zicbop' (Cache-Block Prefetch Instructions).286; CHECK-NEXT: zicboz - 'Zicboz' (Cache-Block Zero Instructions).287; CHECK-NEXT: ziccamoa - 'Ziccamoa' (Main Memory Supports All Atomics in A).288; CHECK-NEXT: ziccamoc - 'Ziccamoc' (Main Memory Supports Atomics in Zacas).289; CHECK-NEXT: ziccif - 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement).290; CHECK-NEXT: zicclsm - 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores).291; CHECK-NEXT: ziccrse - 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences).292; CHECK-NEXT: zicntr - 'Zicntr' (Base Counters and Timers).293; CHECK-NEXT: zicond - 'Zicond' (Integer Conditional Operations).294; CHECK-NEXT: zicsr - 'Zicsr' (CSRs).295; CHECK-NEXT: zifencei - 'Zifencei' (fence.i).296; CHECK-NEXT: zihintntl - 'Zihintntl' (Non-Temporal Locality Hints).297; CHECK-NEXT: zihintpause - 'Zihintpause' (Pause Hint).298; CHECK-NEXT: zihpm - 'Zihpm' (Hardware Performance Counters).299; CHECK-NEXT: zilsd - 'Zilsd' (Load/Store Pair Instructions).300; CHECK-NEXT: zilsd-4byte-align - Allow 4-byte alignment for Zilsd LD/SD instructions.301; CHECK-NEXT: zimop - 'Zimop' (May-Be-Operations).302; CHECK-NEXT: zk - 'Zk' (Standard scalar cryptography extension).303; CHECK-NEXT: zkn - 'Zkn' (NIST Algorithm Suite).304; CHECK-NEXT: zknd - 'Zknd' (NIST Suite: AES Decryption).305; CHECK-NEXT: zkne - 'Zkne' (NIST Suite: AES Encryption).306; CHECK-NEXT: zknh - 'Zknh' (NIST Suite: Hash Function Instructions).307; CHECK-NEXT: zkr - 'Zkr' (Entropy Source Extension).308; CHECK-NEXT: zks - 'Zks' (ShangMi Algorithm Suite).309; CHECK-NEXT: zksed - 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions).310; CHECK-NEXT: zksh - 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions).311; CHECK-NEXT: zkt - 'Zkt' (Data Independent Execution Latency).312; CHECK-NEXT: zmmul - 'Zmmul' (Integer Multiplication).313; CHECK-NEXT: ztso - 'Ztso' (Memory Model - Total Store Order).314; CHECK-NEXT: zvbb - 'Zvbb' (Vector basic bit-manipulation instructions).315; CHECK-NEXT: zvbc - 'Zvbc' (Vector Carryless Multiplication).316; CHECK-NEXT: zve32f - 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension).317; CHECK-NEXT: zve32x - 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW).318; CHECK-NEXT: zve64d - 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension).319; CHECK-NEXT: zve64f - 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension).320; CHECK-NEXT: zve64x - 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW).321; CHECK-NEXT: zvfbfmin - 'Zvfbfmin' (Vector BF16 Converts).322; CHECK-NEXT: zvfbfwma - 'Zvfbfwma' (Vector BF16 widening mul-add).323; CHECK-NEXT: zvfh - 'Zvfh' (Vector Half-Precision Floating-Point).324; CHECK-NEXT: zvfhmin - 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal).325; CHECK-NEXT: zvkb - 'Zvkb' (Vector Bit-manipulation used in Cryptography).326; CHECK-NEXT: zvkg - 'Zvkg' (Vector GCM instructions for Cryptography).327; CHECK-NEXT: zvkn - 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt').328; CHECK-NEXT: zvknc - 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc').329; CHECK-NEXT: zvkned - 'Zvkned' (Vector AES Encryption & Decryption (Single Round)).330; CHECK-NEXT: zvkng - 'Zvkng' (shorthand for 'Zvkn' and 'Zvkg').331; CHECK-NEXT: zvknha - 'Zvknha' (Vector SHA-2 (SHA-256 only)).332; CHECK-NEXT: zvknhb - 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)).333; CHECK-NEXT: zvks - 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt').334; CHECK-NEXT: zvksc - 'Zvksc' (shorthand for 'Zvks' and 'Zvbc').335; CHECK-NEXT: zvksed - 'Zvksed' (SM4 Block Cipher Instructions).336; CHECK-NEXT: zvksg - 'Zvksg' (shorthand for 'Zvks' and 'Zvkg').337; CHECK-NEXT: zvksh - 'Zvksh' (SM3 Hash Function Instructions).338; CHECK-NEXT: zvkt - 'Zvkt' (Vector Data-Independent Execution Latency).339; CHECK-NEXT: zvl1024b - 'Zvl1024b' (Minimum Vector Length 1024).340; CHECK-NEXT: zvl128b - 'Zvl128b' (Minimum Vector Length 128).341; CHECK-NEXT: zvl16384b - 'Zvl16384b' (Minimum Vector Length 16384).342; CHECK-NEXT: zvl2048b - 'Zvl2048b' (Minimum Vector Length 2048).343; CHECK-NEXT: zvl256b - 'Zvl256b' (Minimum Vector Length 256).344; CHECK-NEXT: zvl32768b - 'Zvl32768b' (Minimum Vector Length 32768).345; CHECK-NEXT: zvl32b - 'Zvl32b' (Minimum Vector Length 32).346; CHECK-NEXT: zvl4096b - 'Zvl4096b' (Minimum Vector Length 4096).347; CHECK-NEXT: zvl512b - 'Zvl512b' (Minimum Vector Length 512).348; CHECK-NEXT: zvl64b - 'Zvl64b' (Minimum Vector Length 64).349; CHECK-NEXT: zvl65536b - 'Zvl65536b' (Minimum Vector Length 65536).350; CHECK-NEXT: zvl8192b - 'Zvl8192b' (Minimum Vector Length 8192).351; CHECK-EMPTY:352