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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \3; RUN: -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \5; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s6; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \7; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s8; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \9; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s10; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \11; RUN: | FileCheck -check-prefix=RV32I %s12; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \13; RUN: | FileCheck -check-prefix=RV64I %s14 15; These tests are each targeted at a particular RISC-V FPU instruction.16; Compares and conversions can be found in float-fcmp.ll and float-convert.ll17; respectively. Some other float-*.ll files in this folder exercise LLVM IR18; instructions that don't directly match a RISC-V instruction.19 20define float @fadd_s(float %a, float %b) nounwind {21; CHECKIF-LABEL: fadd_s:22; CHECKIF: # %bb.0:23; CHECKIF-NEXT: fadd.s fa0, fa0, fa124; CHECKIF-NEXT: ret25;26; CHECKIZFINX-LABEL: fadd_s:27; CHECKIZFINX: # %bb.0:28; CHECKIZFINX-NEXT: fadd.s a0, a0, a129; CHECKIZFINX-NEXT: ret30;31; RV32I-LABEL: fadd_s:32; RV32I: # %bb.0:33; RV32I-NEXT: addi sp, sp, -1634; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill35; RV32I-NEXT: call __addsf336; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload37; RV32I-NEXT: addi sp, sp, 1638; RV32I-NEXT: ret39;40; RV64I-LABEL: fadd_s:41; RV64I: # %bb.0:42; RV64I-NEXT: addi sp, sp, -1643; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill44; RV64I-NEXT: call __addsf345; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload46; RV64I-NEXT: addi sp, sp, 1647; RV64I-NEXT: ret48 %1 = fadd float %a, %b49 ret float %150}51 52define float @fsub_s(float %a, float %b) nounwind {53; CHECKIF-LABEL: fsub_s:54; CHECKIF: # %bb.0:55; CHECKIF-NEXT: fsub.s fa0, fa0, fa156; CHECKIF-NEXT: ret57;58; CHECKIZFINX-LABEL: fsub_s:59; CHECKIZFINX: # %bb.0:60; CHECKIZFINX-NEXT: fsub.s a0, a0, a161; CHECKIZFINX-NEXT: ret62;63; RV32I-LABEL: fsub_s:64; RV32I: # %bb.0:65; RV32I-NEXT: addi sp, sp, -1666; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill67; RV32I-NEXT: call __subsf368; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload69; RV32I-NEXT: addi sp, sp, 1670; RV32I-NEXT: ret71;72; RV64I-LABEL: fsub_s:73; RV64I: # %bb.0:74; RV64I-NEXT: addi sp, sp, -1675; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill76; RV64I-NEXT: call __subsf377; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload78; RV64I-NEXT: addi sp, sp, 1679; RV64I-NEXT: ret80 %1 = fsub float %a, %b81 ret float %182}83 84define float @fmul_s(float %a, float %b) nounwind {85; CHECKIF-LABEL: fmul_s:86; CHECKIF: # %bb.0:87; CHECKIF-NEXT: fmul.s fa0, fa0, fa188; CHECKIF-NEXT: ret89;90; CHECKIZFINX-LABEL: fmul_s:91; CHECKIZFINX: # %bb.0:92; CHECKIZFINX-NEXT: fmul.s a0, a0, a193; CHECKIZFINX-NEXT: ret94;95; RV32I-LABEL: fmul_s:96; RV32I: # %bb.0:97; RV32I-NEXT: addi sp, sp, -1698; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill99; RV32I-NEXT: call __mulsf3100; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload101; RV32I-NEXT: addi sp, sp, 16102; RV32I-NEXT: ret103;104; RV64I-LABEL: fmul_s:105; RV64I: # %bb.0:106; RV64I-NEXT: addi sp, sp, -16107; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill108; RV64I-NEXT: call __mulsf3109; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload110; RV64I-NEXT: addi sp, sp, 16111; RV64I-NEXT: ret112 %1 = fmul float %a, %b113 ret float %1114}115 116define float @fdiv_s(float %a, float %b) nounwind {117; CHECKIF-LABEL: fdiv_s:118; CHECKIF: # %bb.0:119; CHECKIF-NEXT: fdiv.s fa0, fa0, fa1120; CHECKIF-NEXT: ret121;122; CHECKIZFINX-LABEL: fdiv_s:123; CHECKIZFINX: # %bb.0:124; CHECKIZFINX-NEXT: fdiv.s a0, a0, a1125; CHECKIZFINX-NEXT: ret126;127; RV32I-LABEL: fdiv_s:128; RV32I: # %bb.0:129; RV32I-NEXT: addi sp, sp, -16130; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill131; RV32I-NEXT: call __divsf3132; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload133; RV32I-NEXT: addi sp, sp, 16134; RV32I-NEXT: ret135;136; RV64I-LABEL: fdiv_s:137; RV64I: # %bb.0:138; RV64I-NEXT: addi sp, sp, -16139; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill140; RV64I-NEXT: call __divsf3141; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload142; RV64I-NEXT: addi sp, sp, 16143; RV64I-NEXT: ret144 %1 = fdiv float %a, %b145 ret float %1146}147 148define float @fsqrt_s(float %a) nounwind {149; CHECKIF-LABEL: fsqrt_s:150; CHECKIF: # %bb.0:151; CHECKIF-NEXT: fsqrt.s fa0, fa0152; CHECKIF-NEXT: ret153;154; CHECKIZFINX-LABEL: fsqrt_s:155; CHECKIZFINX: # %bb.0:156; CHECKIZFINX-NEXT: fsqrt.s a0, a0157; CHECKIZFINX-NEXT: ret158;159; RV32I-LABEL: fsqrt_s:160; RV32I: # %bb.0:161; RV32I-NEXT: addi sp, sp, -16162; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill163; RV32I-NEXT: call sqrtf164; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload165; RV32I-NEXT: addi sp, sp, 16166; RV32I-NEXT: ret167;168; RV64I-LABEL: fsqrt_s:169; RV64I: # %bb.0:170; RV64I-NEXT: addi sp, sp, -16171; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill172; RV64I-NEXT: call sqrtf173; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload174; RV64I-NEXT: addi sp, sp, 16175; RV64I-NEXT: ret176 %1 = call float @llvm.sqrt.f32(float %a)177 ret float %1178}179 180define float @fsgnj_s(float %a, float %b) nounwind {181; CHECKIF-LABEL: fsgnj_s:182; CHECKIF: # %bb.0:183; CHECKIF-NEXT: fsgnj.s fa0, fa0, fa1184; CHECKIF-NEXT: ret185;186; CHECKIZFINX-LABEL: fsgnj_s:187; CHECKIZFINX: # %bb.0:188; CHECKIZFINX-NEXT: fsgnj.s a0, a0, a1189; CHECKIZFINX-NEXT: ret190;191; RV32I-LABEL: fsgnj_s:192; RV32I: # %bb.0:193; RV32I-NEXT: lui a2, 524288194; RV32I-NEXT: slli a0, a0, 1195; RV32I-NEXT: and a1, a1, a2196; RV32I-NEXT: srli a0, a0, 1197; RV32I-NEXT: or a0, a0, a1198; RV32I-NEXT: ret199;200; RV64I-LABEL: fsgnj_s:201; RV64I: # %bb.0:202; RV64I-NEXT: lui a2, 524288203; RV64I-NEXT: slli a0, a0, 33204; RV64I-NEXT: and a1, a1, a2205; RV64I-NEXT: srli a0, a0, 33206; RV64I-NEXT: or a0, a0, a1207; RV64I-NEXT: ret208 %1 = call float @llvm.copysign.f32(float %a, float %b)209 ret float %1210}211 212define i32 @fneg_s(float %a, float %b) nounwind {213; CHECKIF-LABEL: fneg_s:214; CHECKIF: # %bb.0:215; CHECKIF-NEXT: fadd.s fa5, fa0, fa0216; CHECKIF-NEXT: fneg.s fa4, fa5217; CHECKIF-NEXT: feq.s a0, fa5, fa4218; CHECKIF-NEXT: ret219;220; CHECKIZFINX-LABEL: fneg_s:221; CHECKIZFINX: # %bb.0:222; CHECKIZFINX-NEXT: fadd.s a0, a0, a0223; CHECKIZFINX-NEXT: fneg.s a1, a0224; CHECKIZFINX-NEXT: feq.s a0, a0, a1225; CHECKIZFINX-NEXT: ret226;227; RV32I-LABEL: fneg_s:228; RV32I: # %bb.0:229; RV32I-NEXT: addi sp, sp, -16230; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill231; RV32I-NEXT: mv a1, a0232; RV32I-NEXT: call __addsf3233; RV32I-NEXT: lui a1, 524288234; RV32I-NEXT: xor a1, a0, a1235; RV32I-NEXT: call __eqsf2236; RV32I-NEXT: seqz a0, a0237; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload238; RV32I-NEXT: addi sp, sp, 16239; RV32I-NEXT: ret240;241; RV64I-LABEL: fneg_s:242; RV64I: # %bb.0:243; RV64I-NEXT: addi sp, sp, -16244; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill245; RV64I-NEXT: mv a1, a0246; RV64I-NEXT: call __addsf3247; RV64I-NEXT: lui a1, 524288248; RV64I-NEXT: xor a1, a0, a1249; RV64I-NEXT: call __eqsf2250; RV64I-NEXT: seqz a0, a0251; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload252; RV64I-NEXT: addi sp, sp, 16253; RV64I-NEXT: ret254 %1 = fadd float %a, %a255 %2 = fneg float %1256 %3 = fcmp oeq float %1, %2257 %4 = zext i1 %3 to i32258 ret i32 %4259}260 261define float @fsgnjn_s(float %a, float %b) nounwind {262; CHECKIF-LABEL: fsgnjn_s:263; CHECKIF: # %bb.0:264; CHECKIF-NEXT: fadd.s fa5, fa0, fa1265; CHECKIF-NEXT: fsgnjn.s fa0, fa0, fa5266; CHECKIF-NEXT: ret267;268; CHECKIZFINX-LABEL: fsgnjn_s:269; CHECKIZFINX: # %bb.0:270; CHECKIZFINX-NEXT: fadd.s a1, a0, a1271; CHECKIZFINX-NEXT: fsgnjn.s a0, a0, a1272; CHECKIZFINX-NEXT: ret273;274; RV32I-LABEL: fsgnjn_s:275; RV32I: # %bb.0:276; RV32I-NEXT: addi sp, sp, -16277; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill278; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill279; RV32I-NEXT: mv s0, a0280; RV32I-NEXT: call __addsf3281; RV32I-NEXT: not a0, a0282; RV32I-NEXT: lui a1, 524288283; RV32I-NEXT: slli s0, s0, 1284; RV32I-NEXT: and a0, a0, a1285; RV32I-NEXT: srli s0, s0, 1286; RV32I-NEXT: or a0, s0, a0287; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload288; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload289; RV32I-NEXT: addi sp, sp, 16290; RV32I-NEXT: ret291;292; RV64I-LABEL: fsgnjn_s:293; RV64I: # %bb.0:294; RV64I-NEXT: addi sp, sp, -16295; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill296; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill297; RV64I-NEXT: mv s0, a0298; RV64I-NEXT: call __addsf3299; RV64I-NEXT: not a0, a0300; RV64I-NEXT: lui a1, 524288301; RV64I-NEXT: slli s0, s0, 33302; RV64I-NEXT: and a0, a0, a1303; RV64I-NEXT: srli s0, s0, 33304; RV64I-NEXT: or a0, s0, a0305; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload306; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload307; RV64I-NEXT: addi sp, sp, 16308; RV64I-NEXT: ret309 %1 = fadd float %a, %b310 %2 = fneg float %1311 %3 = call float @llvm.copysign.f32(float %a, float %2)312 ret float %3313}314 315define float @fabs_s(float %a, float %b) nounwind {316; CHECKIF-LABEL: fabs_s:317; CHECKIF: # %bb.0:318; CHECKIF-NEXT: fadd.s fa5, fa0, fa1319; CHECKIF-NEXT: fabs.s fa4, fa5320; CHECKIF-NEXT: fadd.s fa0, fa4, fa5321; CHECKIF-NEXT: ret322;323; CHECKIZFINX-LABEL: fabs_s:324; CHECKIZFINX: # %bb.0:325; CHECKIZFINX-NEXT: fadd.s a0, a0, a1326; CHECKIZFINX-NEXT: fabs.s a1, a0327; CHECKIZFINX-NEXT: fadd.s a0, a1, a0328; CHECKIZFINX-NEXT: ret329;330; RV32I-LABEL: fabs_s:331; RV32I: # %bb.0:332; RV32I-NEXT: addi sp, sp, -16333; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill334; RV32I-NEXT: call __addsf3335; RV32I-NEXT: mv a1, a0336; RV32I-NEXT: slli a0, a0, 1337; RV32I-NEXT: srli a0, a0, 1338; RV32I-NEXT: call __addsf3339; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload340; RV32I-NEXT: addi sp, sp, 16341; RV32I-NEXT: ret342;343; RV64I-LABEL: fabs_s:344; RV64I: # %bb.0:345; RV64I-NEXT: addi sp, sp, -16346; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill347; RV64I-NEXT: call __addsf3348; RV64I-NEXT: mv a1, a0349; RV64I-NEXT: slli a0, a0, 33350; RV64I-NEXT: srli a0, a0, 33351; RV64I-NEXT: call __addsf3352; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload353; RV64I-NEXT: addi sp, sp, 16354; RV64I-NEXT: ret355 %1 = fadd float %a, %b356 %2 = call float @llvm.fabs.f32(float %1)357 %3 = fadd float %2, %1358 ret float %3359}360 361define float @fmin_s(float %a, float %b) nounwind {362; CHECKIF-LABEL: fmin_s:363; CHECKIF: # %bb.0:364; CHECKIF-NEXT: fmin.s fa0, fa0, fa1365; CHECKIF-NEXT: ret366;367; CHECKIZFINX-LABEL: fmin_s:368; CHECKIZFINX: # %bb.0:369; CHECKIZFINX-NEXT: fmin.s a0, a0, a1370; CHECKIZFINX-NEXT: ret371;372; RV32I-LABEL: fmin_s:373; RV32I: # %bb.0:374; RV32I-NEXT: addi sp, sp, -16375; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill376; RV32I-NEXT: call fminf377; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload378; RV32I-NEXT: addi sp, sp, 16379; RV32I-NEXT: ret380;381; RV64I-LABEL: fmin_s:382; RV64I: # %bb.0:383; RV64I-NEXT: addi sp, sp, -16384; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill385; RV64I-NEXT: call fminf386; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload387; RV64I-NEXT: addi sp, sp, 16388; RV64I-NEXT: ret389 %1 = call float @llvm.minnum.f32(float %a, float %b)390 ret float %1391}392 393define float @fmax_s(float %a, float %b) nounwind {394; CHECKIF-LABEL: fmax_s:395; CHECKIF: # %bb.0:396; CHECKIF-NEXT: fmax.s fa0, fa0, fa1397; CHECKIF-NEXT: ret398;399; CHECKIZFINX-LABEL: fmax_s:400; CHECKIZFINX: # %bb.0:401; CHECKIZFINX-NEXT: fmax.s a0, a0, a1402; CHECKIZFINX-NEXT: ret403;404; RV32I-LABEL: fmax_s:405; RV32I: # %bb.0:406; RV32I-NEXT: addi sp, sp, -16407; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill408; RV32I-NEXT: call fmaxf409; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload410; RV32I-NEXT: addi sp, sp, 16411; RV32I-NEXT: ret412;413; RV64I-LABEL: fmax_s:414; RV64I: # %bb.0:415; RV64I-NEXT: addi sp, sp, -16416; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill417; RV64I-NEXT: call fmaxf418; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload419; RV64I-NEXT: addi sp, sp, 16420; RV64I-NEXT: ret421 %1 = call float @llvm.maxnum.f32(float %a, float %b)422 ret float %1423}424 425define float @fmadd_s(float %a, float %b, float %c) nounwind {426; CHECKIF-LABEL: fmadd_s:427; CHECKIF: # %bb.0:428; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2429; CHECKIF-NEXT: ret430;431; CHECKIZFINX-LABEL: fmadd_s:432; CHECKIZFINX: # %bb.0:433; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a2434; CHECKIZFINX-NEXT: ret435;436; RV32I-LABEL: fmadd_s:437; RV32I: # %bb.0:438; RV32I-NEXT: addi sp, sp, -16439; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill440; RV32I-NEXT: call fmaf441; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload442; RV32I-NEXT: addi sp, sp, 16443; RV32I-NEXT: ret444;445; RV64I-LABEL: fmadd_s:446; RV64I: # %bb.0:447; RV64I-NEXT: addi sp, sp, -16448; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill449; RV64I-NEXT: call fmaf450; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload451; RV64I-NEXT: addi sp, sp, 16452; RV64I-NEXT: ret453 %1 = call float @llvm.fma.f32(float %a, float %b, float %c)454 ret float %1455}456 457define float @fmsub_s(float %a, float %b, float %c) nounwind {458; CHECKIF-LABEL: fmsub_s:459; CHECKIF: # %bb.0:460; CHECKIF-NEXT: fmv.w.x fa5, zero461; CHECKIF-NEXT: fadd.s fa5, fa2, fa5462; CHECKIF-NEXT: fmsub.s fa0, fa0, fa1, fa5463; CHECKIF-NEXT: ret464;465; CHECKIZFINX-LABEL: fmsub_s:466; CHECKIZFINX: # %bb.0:467; CHECKIZFINX-NEXT: fadd.s a2, a2, zero468; CHECKIZFINX-NEXT: fmsub.s a0, a0, a1, a2469; CHECKIZFINX-NEXT: ret470;471; RV32I-LABEL: fmsub_s:472; RV32I: # %bb.0:473; RV32I-NEXT: addi sp, sp, -16474; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill475; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill476; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill477; RV32I-NEXT: mv s0, a1478; RV32I-NEXT: mv s1, a0479; RV32I-NEXT: mv a0, a2480; RV32I-NEXT: li a1, 0481; RV32I-NEXT: call __addsf3482; RV32I-NEXT: lui a2, 524288483; RV32I-NEXT: xor a2, a0, a2484; RV32I-NEXT: mv a0, s1485; RV32I-NEXT: mv a1, s0486; RV32I-NEXT: call fmaf487; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload488; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload489; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload490; RV32I-NEXT: addi sp, sp, 16491; RV32I-NEXT: ret492;493; RV64I-LABEL: fmsub_s:494; RV64I: # %bb.0:495; RV64I-NEXT: addi sp, sp, -32496; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill497; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill498; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill499; RV64I-NEXT: mv s0, a1500; RV64I-NEXT: mv s1, a0501; RV64I-NEXT: mv a0, a2502; RV64I-NEXT: li a1, 0503; RV64I-NEXT: call __addsf3504; RV64I-NEXT: lui a2, 524288505; RV64I-NEXT: xor a2, a0, a2506; RV64I-NEXT: mv a0, s1507; RV64I-NEXT: mv a1, s0508; RV64I-NEXT: call fmaf509; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload510; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload511; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload512; RV64I-NEXT: addi sp, sp, 32513; RV64I-NEXT: ret514 %c_ = fadd float 0.0, %c ; avoid negation using xor515 %negc = fsub float -0.0, %c_516 %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)517 ret float %1518}519 520define float @fmsub_s_fmul_fneg(float %a, float %b, float %c, float %d) nounwind {521; CHECKIFD-LABEL: fmsub_d_fmul_fneg:522; CHECKIFD: # %bb.0:523; CHECKIFD-NEXT: fneg.d fa5, fa3524; CHECKIFD-NEXT: fmul.d fa5, fa2, fa5525; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa5526; CHECKIFD-NEXT: ret527;528; RV32IZFINXZDINX-LABEL: fmsub_d_fmul_fneg:529; RV32IZFINXZDINX: # %bb.0:530; RV32IZFINXZDINX-NEXT: fneg.d a6, a6531; RV32IZFINXZDINX-NEXT: fmul.d a4, a4, a6532; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4533; RV32IZFINXZDINX-NEXT: ret534;535; RV64IZFINXZDINX-LABEL: fmsub_d_fmul_fneg:536; RV64IZFINXZDINX: # %bb.0:537; RV64IZFINXZDINX-NEXT: fneg.d a3, a3538; RV64IZFINXZDINX-NEXT: fmul.d a2, a2, a3539; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2540; RV64IZFINXZDINX-NEXT: ret541;542; CHECKIF-LABEL: fmsub_s_fmul_fneg:543; CHECKIF: # %bb.0:544; CHECKIF-NEXT: fmul.s fa5, fa2, fa3545; CHECKIF-NEXT: fmsub.s fa0, fa0, fa1, fa5546; CHECKIF-NEXT: ret547;548; CHECKIZFINX-LABEL: fmsub_s_fmul_fneg:549; CHECKIZFINX: # %bb.0:550; CHECKIZFINX-NEXT: fmul.s a2, a2, a3551; CHECKIZFINX-NEXT: fmsub.s a0, a0, a1, a2552; CHECKIZFINX-NEXT: ret553;554; RV32I-LABEL: fmsub_s_fmul_fneg:555; RV32I: # %bb.0:556; RV32I-NEXT: addi sp, sp, -16557; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill558; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill559; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill560; RV32I-NEXT: mv s0, a1561; RV32I-NEXT: mv s1, a0562; RV32I-NEXT: lui a1, 524288563; RV32I-NEXT: xor a1, a3, a1564; RV32I-NEXT: mv a0, a2565; RV32I-NEXT: call __mulsf3566; RV32I-NEXT: mv a2, a0567; RV32I-NEXT: mv a0, s1568; RV32I-NEXT: mv a1, s0569; RV32I-NEXT: call fmaf570; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload571; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload572; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload573; RV32I-NEXT: addi sp, sp, 16574; RV32I-NEXT: ret575;576; RV64I-LABEL: fmsub_s_fmul_fneg:577; RV64I: # %bb.0:578; RV64I-NEXT: addi sp, sp, -32579; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill580; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill581; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill582; RV64I-NEXT: mv s0, a1583; RV64I-NEXT: mv s1, a0584; RV64I-NEXT: lui a1, 524288585; RV64I-NEXT: xor a1, a3, a1586; RV64I-NEXT: mv a0, a2587; RV64I-NEXT: call __mulsf3588; RV64I-NEXT: mv a2, a0589; RV64I-NEXT: mv a0, s1590; RV64I-NEXT: mv a1, s0591; RV64I-NEXT: call fmaf592; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload593; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload594; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload595; RV64I-NEXT: addi sp, sp, 32596; RV64I-NEXT: ret597 %negd = fneg float %d598 %fmul = fmul float %c, %negd599 %1 = call float @llvm.fma.f32(float %a, float %b, float %fmul)600 ret float %1601}602 603define float @fnmadd_s(float %a, float %b, float %c) nounwind {604; CHECKIF-LABEL: fnmadd_s:605; CHECKIF: # %bb.0:606; CHECKIF-NEXT: fmv.w.x fa5, zero607; CHECKIF-NEXT: fadd.s fa4, fa0, fa5608; CHECKIF-NEXT: fadd.s fa5, fa2, fa5609; CHECKIF-NEXT: fnmadd.s fa0, fa4, fa1, fa5610; CHECKIF-NEXT: ret611;612; CHECKIZFINX-LABEL: fnmadd_s:613; CHECKIZFINX: # %bb.0:614; CHECKIZFINX-NEXT: fadd.s a0, a0, zero615; CHECKIZFINX-NEXT: fadd.s a2, a2, zero616; CHECKIZFINX-NEXT: fnmadd.s a0, a0, a1, a2617; CHECKIZFINX-NEXT: ret618;619; RV32I-LABEL: fnmadd_s:620; RV32I: # %bb.0:621; RV32I-NEXT: addi sp, sp, -16622; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill623; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill624; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill625; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill626; RV32I-NEXT: mv s0, a2627; RV32I-NEXT: mv s1, a1628; RV32I-NEXT: li a1, 0629; RV32I-NEXT: call __addsf3630; RV32I-NEXT: mv s2, a0631; RV32I-NEXT: mv a0, s0632; RV32I-NEXT: li a1, 0633; RV32I-NEXT: call __addsf3634; RV32I-NEXT: lui a2, 524288635; RV32I-NEXT: xor a1, s2, a2636; RV32I-NEXT: xor a2, a0, a2637; RV32I-NEXT: mv a0, a1638; RV32I-NEXT: mv a1, s1639; RV32I-NEXT: call fmaf640; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload641; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload642; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload643; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload644; RV32I-NEXT: addi sp, sp, 16645; RV32I-NEXT: ret646;647; RV64I-LABEL: fnmadd_s:648; RV64I: # %bb.0:649; RV64I-NEXT: addi sp, sp, -32650; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill651; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill652; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill653; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill654; RV64I-NEXT: mv s0, a2655; RV64I-NEXT: mv s1, a1656; RV64I-NEXT: li a1, 0657; RV64I-NEXT: call __addsf3658; RV64I-NEXT: mv s2, a0659; RV64I-NEXT: mv a0, s0660; RV64I-NEXT: li a1, 0661; RV64I-NEXT: call __addsf3662; RV64I-NEXT: lui a2, 524288663; RV64I-NEXT: xor a1, s2, a2664; RV64I-NEXT: xor a2, a0, a2665; RV64I-NEXT: mv a0, a1666; RV64I-NEXT: mv a1, s1667; RV64I-NEXT: call fmaf668; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload669; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload670; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload671; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload672; RV64I-NEXT: addi sp, sp, 32673; RV64I-NEXT: ret674 %a_ = fadd float 0.0, %a675 %c_ = fadd float 0.0, %c676 %nega = fsub float -0.0, %a_677 %negc = fsub float -0.0, %c_678 %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)679 ret float %1680}681 682define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {683; CHECKIF-LABEL: fnmadd_s_2:684; CHECKIF: # %bb.0:685; CHECKIF-NEXT: fmv.w.x fa5, zero686; CHECKIF-NEXT: fadd.s fa4, fa1, fa5687; CHECKIF-NEXT: fadd.s fa5, fa2, fa5688; CHECKIF-NEXT: fnmadd.s fa0, fa4, fa0, fa5689; CHECKIF-NEXT: ret690;691; CHECKIZFINX-LABEL: fnmadd_s_2:692; CHECKIZFINX: # %bb.0:693; CHECKIZFINX-NEXT: fadd.s a1, a1, zero694; CHECKIZFINX-NEXT: fadd.s a2, a2, zero695; CHECKIZFINX-NEXT: fnmadd.s a0, a1, a0, a2696; CHECKIZFINX-NEXT: ret697;698; RV32I-LABEL: fnmadd_s_2:699; RV32I: # %bb.0:700; RV32I-NEXT: addi sp, sp, -16701; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill702; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill703; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill704; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill705; RV32I-NEXT: mv s0, a2706; RV32I-NEXT: mv s1, a0707; RV32I-NEXT: mv a0, a1708; RV32I-NEXT: li a1, 0709; RV32I-NEXT: call __addsf3710; RV32I-NEXT: mv s2, a0711; RV32I-NEXT: mv a0, s0712; RV32I-NEXT: li a1, 0713; RV32I-NEXT: call __addsf3714; RV32I-NEXT: lui a2, 524288715; RV32I-NEXT: xor a1, s2, a2716; RV32I-NEXT: xor a2, a0, a2717; RV32I-NEXT: mv a0, s1718; RV32I-NEXT: call fmaf719; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload720; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload721; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload722; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload723; RV32I-NEXT: addi sp, sp, 16724; RV32I-NEXT: ret725;726; RV64I-LABEL: fnmadd_s_2:727; RV64I: # %bb.0:728; RV64I-NEXT: addi sp, sp, -32729; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill730; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill731; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill732; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill733; RV64I-NEXT: mv s0, a2734; RV64I-NEXT: mv s1, a0735; RV64I-NEXT: mv a0, a1736; RV64I-NEXT: li a1, 0737; RV64I-NEXT: call __addsf3738; RV64I-NEXT: mv s2, a0739; RV64I-NEXT: mv a0, s0740; RV64I-NEXT: li a1, 0741; RV64I-NEXT: call __addsf3742; RV64I-NEXT: lui a2, 524288743; RV64I-NEXT: xor a1, s2, a2744; RV64I-NEXT: xor a2, a0, a2745; RV64I-NEXT: mv a0, s1746; RV64I-NEXT: call fmaf747; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload748; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload749; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload750; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload751; RV64I-NEXT: addi sp, sp, 32752; RV64I-NEXT: ret753 %b_ = fadd float 0.0, %b754 %c_ = fadd float 0.0, %c755 %negb = fsub float -0.0, %b_756 %negc = fsub float -0.0, %c_757 %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)758 ret float %1759}760 761define float @fnmadd_s_3(float %a, float %b, float %c) nounwind {762; RV32IF-LABEL: fnmadd_s_3:763; RV32IF: # %bb.0:764; RV32IF-NEXT: fmadd.s ft0, fa0, fa1, fa2765; RV32IF-NEXT: fneg.s fa0, ft0766; RV32IF-NEXT: ret767;768; RV64IF-LABEL: fnmadd_s_3:769; RV64IF: # %bb.0:770; RV64IF-NEXT: fmadd.s ft0, fa0, fa1, fa2771; RV64IF-NEXT: fneg.s fa0, ft0772; RV64IF-NEXT: ret773;774; CHECKIF-LABEL: fnmadd_s_3:775; CHECKIF: # %bb.0:776; CHECKIF-NEXT: fmadd.s fa5, fa0, fa1, fa2777; CHECKIF-NEXT: fneg.s fa0, fa5778; CHECKIF-NEXT: ret779;780; CHECKIZFINX-LABEL: fnmadd_s_3:781; CHECKIZFINX: # %bb.0:782; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a2783; CHECKIZFINX-NEXT: fneg.s a0, a0784; CHECKIZFINX-NEXT: ret785;786; RV32I-LABEL: fnmadd_s_3:787; RV32I: # %bb.0:788; RV32I-NEXT: addi sp, sp, -16789; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill790; RV32I-NEXT: call fmaf791; RV32I-NEXT: lui a1, 524288792; RV32I-NEXT: xor a0, a0, a1793; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload794; RV32I-NEXT: addi sp, sp, 16795; RV32I-NEXT: ret796;797; RV64I-LABEL: fnmadd_s_3:798; RV64I: # %bb.0:799; RV64I-NEXT: addi sp, sp, -16800; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill801; RV64I-NEXT: call fmaf802; RV64I-NEXT: lui a1, 524288803; RV64I-NEXT: xor a0, a0, a1804; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload805; RV64I-NEXT: addi sp, sp, 16806; RV64I-NEXT: ret807 %1 = call float @llvm.fma.f32(float %a, float %b, float %c)808 %neg = fneg float %1809 ret float %neg810}811 812define float @fnmadd_s_fmul_fneg(float %a, float %b, float %c, float %d) nounwind {813; CHECKIFD-LABEL: fnmadd_d_fmul_fneg:814; CHECKIFD: # %bb.0:815; CHECKIFD-NEXT: fneg.d fa5, fa0816; CHECKIFD-NEXT: fmul.d fa5, fa1, fa5817; CHECKIFD-NEXT: fmadd.d fa0, fa2, fa3, fa5818; CHECKIFD-NEXT: ret819;820; RV32IZFINXZDINX-LABEL: fnmadd_d_fmul_fneg:821; RV32IZFINXZDINX: # %bb.0:822; RV32IZFINXZDINX-NEXT: fneg.d a0, a0823; RV32IZFINXZDINX-NEXT: fmul.d a0, a2, a0824; RV32IZFINXZDINX-NEXT: fmadd.d a0, a4, a6, a0825; RV32IZFINXZDINX-NEXT: ret826;827; RV64IZFINXZDINX-LABEL: fnmadd_d_fmul_fneg:828; RV64IZFINXZDINX: # %bb.0:829; RV64IZFINXZDINX-NEXT: fneg.d a0, a0830; RV64IZFINXZDINX-NEXT: fmul.d a0, a1, a0831; RV64IZFINXZDINX-NEXT: fmadd.d a0, a2, a3, a0832; RV64IZFINXZDINX-NEXT: ret833;834; CHECKIF-LABEL: fnmadd_s_fmul_fneg:835; CHECKIF: # %bb.0:836; CHECKIF-NEXT: fmul.s fa5, fa1, fa0837; CHECKIF-NEXT: fmsub.s fa0, fa2, fa3, fa5838; CHECKIF-NEXT: ret839;840; CHECKIZFINX-LABEL: fnmadd_s_fmul_fneg:841; CHECKIZFINX: # %bb.0:842; CHECKIZFINX-NEXT: fmul.s a0, a1, a0843; CHECKIZFINX-NEXT: fmsub.s a0, a2, a3, a0844; CHECKIZFINX-NEXT: ret845;846; RV32I-LABEL: fnmadd_s_fmul_fneg:847; RV32I: # %bb.0:848; RV32I-NEXT: addi sp, sp, -16849; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill850; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill851; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill852; RV32I-NEXT: mv s0, a3853; RV32I-NEXT: mv s1, a2854; RV32I-NEXT: mv a2, a1855; RV32I-NEXT: lui a1, 524288856; RV32I-NEXT: xor a1, a0, a1857; RV32I-NEXT: mv a0, a2858; RV32I-NEXT: call __mulsf3859; RV32I-NEXT: mv a2, a0860; RV32I-NEXT: mv a0, s1861; RV32I-NEXT: mv a1, s0862; RV32I-NEXT: call fmaf863; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload864; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload865; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload866; RV32I-NEXT: addi sp, sp, 16867; RV32I-NEXT: ret868;869; RV64I-LABEL: fnmadd_s_fmul_fneg:870; RV64I: # %bb.0:871; RV64I-NEXT: addi sp, sp, -32872; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill873; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill874; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill875; RV64I-NEXT: mv s0, a3876; RV64I-NEXT: mv s1, a2877; RV64I-NEXT: mv a2, a1878; RV64I-NEXT: lui a1, 524288879; RV64I-NEXT: xor a1, a0, a1880; RV64I-NEXT: mv a0, a2881; RV64I-NEXT: call __mulsf3882; RV64I-NEXT: mv a2, a0883; RV64I-NEXT: mv a0, s1884; RV64I-NEXT: mv a1, s0885; RV64I-NEXT: call fmaf886; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload887; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload888; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload889; RV64I-NEXT: addi sp, sp, 32890; RV64I-NEXT: ret891 %nega = fneg float %a892 %mul = fmul float %b, %nega893 %1 = call float @llvm.fma.f32(float %c, float %d, float %mul)894 ret float %1895}896 897define float @fnmadd_nsz(float %a, float %b, float %c) nounwind {898; RV32IF-LABEL: fnmadd_nsz:899; RV32IF: # %bb.0:900; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2901; RV32IF-NEXT: ret902;903; RV64IF-LABEL: fnmadd_nsz:904; RV64IF: # %bb.0:905; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2906; RV64IF-NEXT: ret907;908; CHECKIF-LABEL: fnmadd_nsz:909; CHECKIF: # %bb.0:910; CHECKIF-NEXT: fnmadd.s fa0, fa0, fa1, fa2911; CHECKIF-NEXT: ret912;913; CHECKIZFINX-LABEL: fnmadd_nsz:914; CHECKIZFINX: # %bb.0:915; CHECKIZFINX-NEXT: fnmadd.s a0, a0, a1, a2916; CHECKIZFINX-NEXT: ret917;918; RV32I-LABEL: fnmadd_nsz:919; RV32I: # %bb.0:920; RV32I-NEXT: addi sp, sp, -16921; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill922; RV32I-NEXT: call fmaf923; RV32I-NEXT: lui a1, 524288924; RV32I-NEXT: xor a0, a0, a1925; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload926; RV32I-NEXT: addi sp, sp, 16927; RV32I-NEXT: ret928;929; RV64I-LABEL: fnmadd_nsz:930; RV64I: # %bb.0:931; RV64I-NEXT: addi sp, sp, -16932; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill933; RV64I-NEXT: call fmaf934; RV64I-NEXT: lui a1, 524288935; RV64I-NEXT: xor a0, a0, a1936; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload937; RV64I-NEXT: addi sp, sp, 16938; RV64I-NEXT: ret939 %1 = call nsz float @llvm.fma.f32(float %a, float %b, float %c)940 %neg = fneg nsz float %1941 ret float %neg942}943 944define float @fnmsub_s(float %a, float %b, float %c) nounwind {945; CHECKIF-LABEL: fnmsub_s:946; CHECKIF: # %bb.0:947; CHECKIF-NEXT: fmv.w.x fa5, zero948; CHECKIF-NEXT: fadd.s fa5, fa0, fa5949; CHECKIF-NEXT: fnmsub.s fa0, fa5, fa1, fa2950; CHECKIF-NEXT: ret951;952; CHECKIZFINX-LABEL: fnmsub_s:953; CHECKIZFINX: # %bb.0:954; CHECKIZFINX-NEXT: fadd.s a0, a0, zero955; CHECKIZFINX-NEXT: fnmsub.s a0, a0, a1, a2956; CHECKIZFINX-NEXT: ret957;958; RV32I-LABEL: fnmsub_s:959; RV32I: # %bb.0:960; RV32I-NEXT: addi sp, sp, -16961; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill962; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill963; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill964; RV32I-NEXT: mv s0, a2965; RV32I-NEXT: mv s1, a1966; RV32I-NEXT: li a1, 0967; RV32I-NEXT: call __addsf3968; RV32I-NEXT: lui a1, 524288969; RV32I-NEXT: xor a0, a0, a1970; RV32I-NEXT: mv a1, s1971; RV32I-NEXT: mv a2, s0972; RV32I-NEXT: call fmaf973; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload974; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload975; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload976; RV32I-NEXT: addi sp, sp, 16977; RV32I-NEXT: ret978;979; RV64I-LABEL: fnmsub_s:980; RV64I: # %bb.0:981; RV64I-NEXT: addi sp, sp, -32982; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill983; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill984; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill985; RV64I-NEXT: mv s0, a2986; RV64I-NEXT: mv s1, a1987; RV64I-NEXT: li a1, 0988; RV64I-NEXT: call __addsf3989; RV64I-NEXT: lui a1, 524288990; RV64I-NEXT: xor a0, a0, a1991; RV64I-NEXT: mv a1, s1992; RV64I-NEXT: mv a2, s0993; RV64I-NEXT: call fmaf994; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload995; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload996; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload997; RV64I-NEXT: addi sp, sp, 32998; RV64I-NEXT: ret999 %a_ = fadd float 0.0, %a1000 %nega = fsub float -0.0, %a_1001 %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)1002 ret float %11003}1004 1005define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {1006; CHECKIF-LABEL: fnmsub_s_2:1007; CHECKIF: # %bb.0:1008; CHECKIF-NEXT: fmv.w.x fa5, zero1009; CHECKIF-NEXT: fadd.s fa5, fa1, fa51010; CHECKIF-NEXT: fnmsub.s fa0, fa5, fa0, fa21011; CHECKIF-NEXT: ret1012;1013; CHECKIZFINX-LABEL: fnmsub_s_2:1014; CHECKIZFINX: # %bb.0:1015; CHECKIZFINX-NEXT: fadd.s a1, a1, zero1016; CHECKIZFINX-NEXT: fnmsub.s a0, a1, a0, a21017; CHECKIZFINX-NEXT: ret1018;1019; RV32I-LABEL: fnmsub_s_2:1020; RV32I: # %bb.0:1021; RV32I-NEXT: addi sp, sp, -161022; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1023; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill1024; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill1025; RV32I-NEXT: mv s0, a21026; RV32I-NEXT: mv s1, a01027; RV32I-NEXT: mv a0, a11028; RV32I-NEXT: li a1, 01029; RV32I-NEXT: call __addsf31030; RV32I-NEXT: lui a1, 5242881031; RV32I-NEXT: xor a1, a0, a11032; RV32I-NEXT: mv a0, s11033; RV32I-NEXT: mv a2, s01034; RV32I-NEXT: call fmaf1035; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1036; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload1037; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload1038; RV32I-NEXT: addi sp, sp, 161039; RV32I-NEXT: ret1040;1041; RV64I-LABEL: fnmsub_s_2:1042; RV64I: # %bb.0:1043; RV64I-NEXT: addi sp, sp, -321044; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill1045; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill1046; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill1047; RV64I-NEXT: mv s0, a21048; RV64I-NEXT: mv s1, a01049; RV64I-NEXT: mv a0, a11050; RV64I-NEXT: li a1, 01051; RV64I-NEXT: call __addsf31052; RV64I-NEXT: lui a1, 5242881053; RV64I-NEXT: xor a1, a0, a11054; RV64I-NEXT: mv a0, s11055; RV64I-NEXT: mv a2, s01056; RV64I-NEXT: call fmaf1057; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload1058; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload1059; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload1060; RV64I-NEXT: addi sp, sp, 321061; RV64I-NEXT: ret1062 %b_ = fadd float 0.0, %b1063 %negb = fsub float -0.0, %b_1064 %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)1065 ret float %11066}1067 1068define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {1069; CHECKIF-LABEL: fmadd_s_contract:1070; CHECKIF: # %bb.0:1071; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa21072; CHECKIF-NEXT: ret1073;1074; CHECKIZFINX-LABEL: fmadd_s_contract:1075; CHECKIZFINX: # %bb.0:1076; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a21077; CHECKIZFINX-NEXT: ret1078;1079; RV32I-LABEL: fmadd_s_contract:1080; RV32I: # %bb.0:1081; RV32I-NEXT: addi sp, sp, -161082; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1083; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill1084; RV32I-NEXT: mv s0, a21085; RV32I-NEXT: call __mulsf31086; RV32I-NEXT: mv a1, s01087; RV32I-NEXT: call __addsf31088; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1089; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload1090; RV32I-NEXT: addi sp, sp, 161091; RV32I-NEXT: ret1092;1093; RV64I-LABEL: fmadd_s_contract:1094; RV64I: # %bb.0:1095; RV64I-NEXT: addi sp, sp, -161096; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1097; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill1098; RV64I-NEXT: mv s0, a21099; RV64I-NEXT: call __mulsf31100; RV64I-NEXT: mv a1, s01101; RV64I-NEXT: call __addsf31102; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1103; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload1104; RV64I-NEXT: addi sp, sp, 161105; RV64I-NEXT: ret1106 %1 = fmul contract float %a, %b1107 %2 = fadd contract float %1, %c1108 ret float %21109}1110 1111define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {1112; CHECKIF-LABEL: fmsub_s_contract:1113; CHECKIF: # %bb.0:1114; CHECKIF-NEXT: fmv.w.x fa5, zero1115; CHECKIF-NEXT: fadd.s fa5, fa2, fa51116; CHECKIF-NEXT: fmsub.s fa0, fa0, fa1, fa51117; CHECKIF-NEXT: ret1118;1119; CHECKIZFINX-LABEL: fmsub_s_contract:1120; CHECKIZFINX: # %bb.0:1121; CHECKIZFINX-NEXT: fadd.s a2, a2, zero1122; CHECKIZFINX-NEXT: fmsub.s a0, a0, a1, a21123; CHECKIZFINX-NEXT: ret1124;1125; RV32I-LABEL: fmsub_s_contract:1126; RV32I: # %bb.0:1127; RV32I-NEXT: addi sp, sp, -161128; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1129; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill1130; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill1131; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill1132; RV32I-NEXT: mv s0, a11133; RV32I-NEXT: mv s1, a01134; RV32I-NEXT: mv a0, a21135; RV32I-NEXT: li a1, 01136; RV32I-NEXT: call __addsf31137; RV32I-NEXT: mv s2, a01138; RV32I-NEXT: mv a0, s11139; RV32I-NEXT: mv a1, s01140; RV32I-NEXT: call __mulsf31141; RV32I-NEXT: mv a1, s21142; RV32I-NEXT: call __subsf31143; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1144; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload1145; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload1146; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload1147; RV32I-NEXT: addi sp, sp, 161148; RV32I-NEXT: ret1149;1150; RV64I-LABEL: fmsub_s_contract:1151; RV64I: # %bb.0:1152; RV64I-NEXT: addi sp, sp, -321153; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill1154; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill1155; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill1156; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill1157; RV64I-NEXT: mv s0, a11158; RV64I-NEXT: mv s1, a01159; RV64I-NEXT: mv a0, a21160; RV64I-NEXT: li a1, 01161; RV64I-NEXT: call __addsf31162; RV64I-NEXT: mv s2, a01163; RV64I-NEXT: mv a0, s11164; RV64I-NEXT: mv a1, s01165; RV64I-NEXT: call __mulsf31166; RV64I-NEXT: mv a1, s21167; RV64I-NEXT: call __subsf31168; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload1169; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload1170; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload1171; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload1172; RV64I-NEXT: addi sp, sp, 321173; RV64I-NEXT: ret1174 %c_ = fadd float 0.0, %c ; avoid negation using xor1175 %1 = fmul contract float %a, %b1176 %2 = fsub contract float %1, %c_1177 ret float %21178}1179 1180define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {1181; CHECKIF-LABEL: fnmadd_s_contract:1182; CHECKIF: # %bb.0:1183; CHECKIF-NEXT: fmv.w.x fa5, zero1184; CHECKIF-NEXT: fadd.s fa4, fa0, fa51185; CHECKIF-NEXT: fadd.s fa3, fa1, fa51186; CHECKIF-NEXT: fadd.s fa5, fa2, fa51187; CHECKIF-NEXT: fnmadd.s fa0, fa4, fa3, fa51188; CHECKIF-NEXT: ret1189;1190; CHECKIZFINX-LABEL: fnmadd_s_contract:1191; CHECKIZFINX: # %bb.0:1192; CHECKIZFINX-NEXT: fadd.s a0, a0, zero1193; CHECKIZFINX-NEXT: fadd.s a1, a1, zero1194; CHECKIZFINX-NEXT: fadd.s a2, a2, zero1195; CHECKIZFINX-NEXT: fnmadd.s a0, a0, a1, a21196; CHECKIZFINX-NEXT: ret1197;1198; RV32I-LABEL: fnmadd_s_contract:1199; RV32I: # %bb.0:1200; RV32I-NEXT: addi sp, sp, -161201; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1202; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill1203; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill1204; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill1205; RV32I-NEXT: mv s0, a21206; RV32I-NEXT: mv s1, a11207; RV32I-NEXT: li a1, 01208; RV32I-NEXT: call __addsf31209; RV32I-NEXT: mv s2, a01210; RV32I-NEXT: mv a0, s11211; RV32I-NEXT: li a1, 01212; RV32I-NEXT: call __addsf31213; RV32I-NEXT: mv s1, a01214; RV32I-NEXT: mv a0, s01215; RV32I-NEXT: li a1, 01216; RV32I-NEXT: call __addsf31217; RV32I-NEXT: mv s0, a01218; RV32I-NEXT: mv a0, s21219; RV32I-NEXT: mv a1, s11220; RV32I-NEXT: call __mulsf31221; RV32I-NEXT: lui a1, 5242881222; RV32I-NEXT: xor a0, a0, a11223; RV32I-NEXT: mv a1, s01224; RV32I-NEXT: call __subsf31225; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1226; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload1227; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload1228; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload1229; RV32I-NEXT: addi sp, sp, 161230; RV32I-NEXT: ret1231;1232; RV64I-LABEL: fnmadd_s_contract:1233; RV64I: # %bb.0:1234; RV64I-NEXT: addi sp, sp, -321235; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill1236; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill1237; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill1238; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill1239; RV64I-NEXT: mv s0, a21240; RV64I-NEXT: mv s1, a11241; RV64I-NEXT: li a1, 01242; RV64I-NEXT: call __addsf31243; RV64I-NEXT: mv s2, a01244; RV64I-NEXT: mv a0, s11245; RV64I-NEXT: li a1, 01246; RV64I-NEXT: call __addsf31247; RV64I-NEXT: mv s1, a01248; RV64I-NEXT: mv a0, s01249; RV64I-NEXT: li a1, 01250; RV64I-NEXT: call __addsf31251; RV64I-NEXT: mv s0, a01252; RV64I-NEXT: mv a0, s21253; RV64I-NEXT: mv a1, s11254; RV64I-NEXT: call __mulsf31255; RV64I-NEXT: lui a1, 5242881256; RV64I-NEXT: xor a0, a0, a11257; RV64I-NEXT: mv a1, s01258; RV64I-NEXT: call __subsf31259; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload1260; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload1261; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload1262; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload1263; RV64I-NEXT: addi sp, sp, 321264; RV64I-NEXT: ret1265 %a_ = fadd float 0.0, %a ; avoid negation using xor1266 %b_ = fadd float 0.0, %b ; avoid negation using xor1267 %c_ = fadd float 0.0, %c ; avoid negation using xor1268 %1 = fmul contract float %a_, %b_1269 %2 = fneg float %11270 %3 = fsub contract float %2, %c_1271 ret float %31272}1273 1274define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {1275; CHECKIF-LABEL: fnmsub_s_contract:1276; CHECKIF: # %bb.0:1277; CHECKIF-NEXT: fmv.w.x fa5, zero1278; CHECKIF-NEXT: fadd.s fa4, fa0, fa51279; CHECKIF-NEXT: fadd.s fa5, fa1, fa51280; CHECKIF-NEXT: fnmsub.s fa0, fa4, fa5, fa21281; CHECKIF-NEXT: ret1282;1283; CHECKIZFINX-LABEL: fnmsub_s_contract:1284; CHECKIZFINX: # %bb.0:1285; CHECKIZFINX-NEXT: fadd.s a0, a0, zero1286; CHECKIZFINX-NEXT: fadd.s a1, a1, zero1287; CHECKIZFINX-NEXT: fnmsub.s a0, a0, a1, a21288; CHECKIZFINX-NEXT: ret1289;1290; RV32I-LABEL: fnmsub_s_contract:1291; RV32I: # %bb.0:1292; RV32I-NEXT: addi sp, sp, -161293; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1294; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill1295; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill1296; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill1297; RV32I-NEXT: mv s0, a21298; RV32I-NEXT: mv s1, a11299; RV32I-NEXT: li a1, 01300; RV32I-NEXT: call __addsf31301; RV32I-NEXT: mv s2, a01302; RV32I-NEXT: mv a0, s11303; RV32I-NEXT: li a1, 01304; RV32I-NEXT: call __addsf31305; RV32I-NEXT: mv a1, a01306; RV32I-NEXT: mv a0, s21307; RV32I-NEXT: call __mulsf31308; RV32I-NEXT: mv a1, a01309; RV32I-NEXT: mv a0, s01310; RV32I-NEXT: call __subsf31311; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1312; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload1313; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload1314; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload1315; RV32I-NEXT: addi sp, sp, 161316; RV32I-NEXT: ret1317;1318; RV64I-LABEL: fnmsub_s_contract:1319; RV64I: # %bb.0:1320; RV64I-NEXT: addi sp, sp, -321321; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill1322; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill1323; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill1324; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill1325; RV64I-NEXT: mv s0, a21326; RV64I-NEXT: mv s1, a11327; RV64I-NEXT: li a1, 01328; RV64I-NEXT: call __addsf31329; RV64I-NEXT: mv s2, a01330; RV64I-NEXT: mv a0, s11331; RV64I-NEXT: li a1, 01332; RV64I-NEXT: call __addsf31333; RV64I-NEXT: mv a1, a01334; RV64I-NEXT: mv a0, s21335; RV64I-NEXT: call __mulsf31336; RV64I-NEXT: mv a1, a01337; RV64I-NEXT: mv a0, s01338; RV64I-NEXT: call __subsf31339; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload1340; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload1341; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload1342; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload1343; RV64I-NEXT: addi sp, sp, 321344; RV64I-NEXT: ret1345 %a_ = fadd float 0.0, %a ; avoid negation using xor1346 %b_ = fadd float 0.0, %b ; avoid negation using xor1347 %1 = fmul contract float %a_, %b_1348 %2 = fsub contract float %c, %11349 ret float %21350}1351 1352define float @fsgnjx_f32(float %x, float %y) nounwind {1353; CHECKIF-LABEL: fsgnjx_f32:1354; CHECKIF: # %bb.0:1355; CHECKIF-NEXT: fsgnjx.s fa0, fa1, fa01356; CHECKIF-NEXT: ret1357;1358; CHECKIZFINX-LABEL: fsgnjx_f32:1359; CHECKIZFINX: # %bb.0:1360; CHECKIZFINX-NEXT: fsgnjx.s a0, a1, a01361; CHECKIZFINX-NEXT: ret1362;1363; RV32I-LABEL: fsgnjx_f32:1364; RV32I: # %bb.0:1365; RV32I-NEXT: addi sp, sp, -161366; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill1367; RV32I-NEXT: lui a2, 5242881368; RV32I-NEXT: and a0, a0, a21369; RV32I-NEXT: lui a2, 2600961370; RV32I-NEXT: or a0, a0, a21371; RV32I-NEXT: call __mulsf31372; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload1373; RV32I-NEXT: addi sp, sp, 161374; RV32I-NEXT: ret1375;1376; RV64I-LABEL: fsgnjx_f32:1377; RV64I: # %bb.0:1378; RV64I-NEXT: addi sp, sp, -161379; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill1380; RV64I-NEXT: lui a2, 5242881381; RV64I-NEXT: and a0, a0, a21382; RV64I-NEXT: lui a2, 2600961383; RV64I-NEXT: or a0, a0, a21384; RV64I-NEXT: call __mulsf31385; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload1386; RV64I-NEXT: addi sp, sp, 161387; RV64I-NEXT: ret1388 %z = call float @llvm.copysign.f32(float 1.0, float %x)1389 %mul = fmul float %z, %y1390 ret float %mul1391}1392;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1393; RV32IZFINX: {{.*}}1394; RV64IZFINX: {{.*}}1395