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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \3; RUN: -disable-strictnode-mutation -target-abi=ilp32f \4; RUN: | FileCheck -check-prefixes=CHECKIF,RV32IF %s5; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \6; RUN: -disable-strictnode-mutation -target-abi=lp64f \7; RUN: | FileCheck -check-prefixes=CHECKIF,RV64IF %s8; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \9; RUN: -disable-strictnode-mutation -target-abi=ilp32 \10; RUN: | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s11; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \12; RUN: -disable-strictnode-mutation -target-abi=lp64 \13; RUN: | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s14; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \15; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s16; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \17; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s18 19; NOTE: The rounding mode metadata does not effect which instruction is20; selected. Dynamic rounding mode is always used for operations that21; support rounding mode.22 23define i32 @fcvt_w_s(float %a) nounwind strictfp {24; CHECKIF-LABEL: fcvt_w_s:25; CHECKIF: # %bb.0:26; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz27; CHECKIF-NEXT: ret28;29; CHECKIZFINX-LABEL: fcvt_w_s:30; CHECKIZFINX: # %bb.0:31; CHECKIZFINX-NEXT: fcvt.w.s a0, a0, rtz32; CHECKIZFINX-NEXT: ret33;34; RV32I-LABEL: fcvt_w_s:35; RV32I: # %bb.0:36; RV32I-NEXT: addi sp, sp, -1637; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill38; RV32I-NEXT: call __fixsfsi39; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload40; RV32I-NEXT: addi sp, sp, 1641; RV32I-NEXT: ret42;43; RV64I-LABEL: fcvt_w_s:44; RV64I: # %bb.0:45; RV64I-NEXT: addi sp, sp, -1646; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill47; RV64I-NEXT: call __fixsfsi48; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload49; RV64I-NEXT: addi sp, sp, 1650; RV64I-NEXT: ret51 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict")52 ret i32 %153}54 55define i32 @fcvt_wu_s(float %a) nounwind strictfp {56; CHECKIF-LABEL: fcvt_wu_s:57; CHECKIF: # %bb.0:58; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz59; CHECKIF-NEXT: ret60;61; CHECKIZFINX-LABEL: fcvt_wu_s:62; CHECKIZFINX: # %bb.0:63; CHECKIZFINX-NEXT: fcvt.wu.s a0, a0, rtz64; CHECKIZFINX-NEXT: ret65;66; RV32I-LABEL: fcvt_wu_s:67; RV32I: # %bb.0:68; RV32I-NEXT: addi sp, sp, -1669; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill70; RV32I-NEXT: call __fixunssfsi71; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload72; RV32I-NEXT: addi sp, sp, 1673; RV32I-NEXT: ret74;75; RV64I-LABEL: fcvt_wu_s:76; RV64I: # %bb.0:77; RV64I-NEXT: addi sp, sp, -1678; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill79; RV64I-NEXT: call __fixunssfsi80; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload81; RV64I-NEXT: addi sp, sp, 1682; RV64I-NEXT: ret83 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict")84 ret i32 %185}86 87; Test where the fptoui has multiple uses, one of which causes a sext to be88; inserted on RV64.89define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind strictfp {90; CHECKIF-LABEL: fcvt_wu_s_multiple_use:91; CHECKIF: # %bb.0:92; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz93; CHECKIF-NEXT: seqz a1, a094; CHECKIF-NEXT: add a0, a0, a195; CHECKIF-NEXT: ret96;97; CHECKIZFINX-LABEL: fcvt_wu_s_multiple_use:98; CHECKIZFINX: # %bb.0:99; CHECKIZFINX-NEXT: fcvt.wu.s a0, a0, rtz100; CHECKIZFINX-NEXT: seqz a1, a0101; CHECKIZFINX-NEXT: add a0, a0, a1102; CHECKIZFINX-NEXT: ret103;104; RV32I-LABEL: fcvt_wu_s_multiple_use:105; RV32I: # %bb.0:106; RV32I-NEXT: addi sp, sp, -16107; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill108; RV32I-NEXT: call __fixunssfsi109; RV32I-NEXT: seqz a1, a0110; RV32I-NEXT: add a0, a0, a1111; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload112; RV32I-NEXT: addi sp, sp, 16113; RV32I-NEXT: ret114;115; RV64I-LABEL: fcvt_wu_s_multiple_use:116; RV64I: # %bb.0:117; RV64I-NEXT: addi sp, sp, -16118; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill119; RV64I-NEXT: call __fixunssfsi120; RV64I-NEXT: seqz a1, a0121; RV64I-NEXT: add a0, a0, a1122; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload123; RV64I-NEXT: addi sp, sp, 16124; RV64I-NEXT: ret125 %a = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict")126 %b = icmp eq i32 %a, 0127 %c = select i1 %b, i32 1, i32 %a128 ret i32 %c129}130 131define float @fcvt_s_w(i32 %a) nounwind strictfp {132; CHECKIF-LABEL: fcvt_s_w:133; CHECKIF: # %bb.0:134; CHECKIF-NEXT: fcvt.s.w fa0, a0135; CHECKIF-NEXT: ret136;137; CHECKIZFINX-LABEL: fcvt_s_w:138; CHECKIZFINX: # %bb.0:139; CHECKIZFINX-NEXT: fcvt.s.w a0, a0140; CHECKIZFINX-NEXT: ret141;142; RV32I-LABEL: fcvt_s_w:143; RV32I: # %bb.0:144; RV32I-NEXT: addi sp, sp, -16145; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill146; RV32I-NEXT: call __floatsisf147; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload148; RV32I-NEXT: addi sp, sp, 16149; RV32I-NEXT: ret150;151; RV64I-LABEL: fcvt_s_w:152; RV64I: # %bb.0:153; RV64I-NEXT: addi sp, sp, -16154; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill155; RV64I-NEXT: sext.w a0, a0156; RV64I-NEXT: call __floatsisf157; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload158; RV64I-NEXT: addi sp, sp, 16159; RV64I-NEXT: ret160 %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")161 ret float %1162}163 164define float @fcvt_s_w_load(ptr %p) nounwind strictfp {165; CHECKIF-LABEL: fcvt_s_w_load:166; CHECKIF: # %bb.0:167; CHECKIF-NEXT: lw a0, 0(a0)168; CHECKIF-NEXT: fcvt.s.w fa0, a0169; CHECKIF-NEXT: ret170;171; CHECKIZFINX-LABEL: fcvt_s_w_load:172; CHECKIZFINX: # %bb.0:173; CHECKIZFINX-NEXT: lw a0, 0(a0)174; CHECKIZFINX-NEXT: fcvt.s.w a0, a0175; CHECKIZFINX-NEXT: ret176;177; RV32I-LABEL: fcvt_s_w_load:178; RV32I: # %bb.0:179; RV32I-NEXT: addi sp, sp, -16180; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill181; RV32I-NEXT: lw a0, 0(a0)182; RV32I-NEXT: call __floatsisf183; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload184; RV32I-NEXT: addi sp, sp, 16185; RV32I-NEXT: ret186;187; RV64I-LABEL: fcvt_s_w_load:188; RV64I: # %bb.0:189; RV64I-NEXT: addi sp, sp, -16190; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill191; RV64I-NEXT: lw a0, 0(a0)192; RV64I-NEXT: call __floatsisf193; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload194; RV64I-NEXT: addi sp, sp, 16195; RV64I-NEXT: ret196 %a = load i32, ptr %p197 %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")198 ret float %1199}200 201define float @fcvt_s_wu(i32 %a) nounwind strictfp {202; CHECKIF-LABEL: fcvt_s_wu:203; CHECKIF: # %bb.0:204; CHECKIF-NEXT: fcvt.s.wu fa0, a0205; CHECKIF-NEXT: ret206;207; CHECKIZFINX-LABEL: fcvt_s_wu:208; CHECKIZFINX: # %bb.0:209; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0210; CHECKIZFINX-NEXT: ret211;212; RV32I-LABEL: fcvt_s_wu:213; RV32I: # %bb.0:214; RV32I-NEXT: addi sp, sp, -16215; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill216; RV32I-NEXT: call __floatunsisf217; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload218; RV32I-NEXT: addi sp, sp, 16219; RV32I-NEXT: ret220;221; RV64I-LABEL: fcvt_s_wu:222; RV64I: # %bb.0:223; RV64I-NEXT: addi sp, sp, -16224; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill225; RV64I-NEXT: sext.w a0, a0226; RV64I-NEXT: call __floatunsisf227; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload228; RV64I-NEXT: addi sp, sp, 16229; RV64I-NEXT: ret230 %1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")231 ret float %1232}233 234define float @fcvt_s_wu_load(ptr %p) nounwind strictfp {235; CHECKIF-LABEL: fcvt_s_wu_load:236; CHECKIF: # %bb.0:237; CHECKIF-NEXT: lw a0, 0(a0)238; CHECKIF-NEXT: fcvt.s.wu fa0, a0239; CHECKIF-NEXT: ret240;241; CHECKIZFINX-LABEL: fcvt_s_wu_load:242; CHECKIZFINX: # %bb.0:243; CHECKIZFINX-NEXT: lw a0, 0(a0)244; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0245; CHECKIZFINX-NEXT: ret246;247; RV32I-LABEL: fcvt_s_wu_load:248; RV32I: # %bb.0:249; RV32I-NEXT: addi sp, sp, -16250; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill251; RV32I-NEXT: lw a0, 0(a0)252; RV32I-NEXT: call __floatunsisf253; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload254; RV32I-NEXT: addi sp, sp, 16255; RV32I-NEXT: ret256;257; RV64I-LABEL: fcvt_s_wu_load:258; RV64I: # %bb.0:259; RV64I-NEXT: addi sp, sp, -16260; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill261; RV64I-NEXT: lw a0, 0(a0)262; RV64I-NEXT: call __floatunsisf263; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload264; RV64I-NEXT: addi sp, sp, 16265; RV64I-NEXT: ret266 %a = load i32, ptr %p267 %1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")268 ret float %1269}270 271define i64 @fcvt_l_s(float %a) nounwind strictfp {272; RV32IF-LABEL: fcvt_l_s:273; RV32IF: # %bb.0:274; RV32IF-NEXT: addi sp, sp, -16275; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill276; RV32IF-NEXT: call __fixsfdi277; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload278; RV32IF-NEXT: addi sp, sp, 16279; RV32IF-NEXT: ret280;281; RV64IF-LABEL: fcvt_l_s:282; RV64IF: # %bb.0:283; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz284; RV64IF-NEXT: ret285;286; RV32IZFINX-LABEL: fcvt_l_s:287; RV32IZFINX: # %bb.0:288; RV32IZFINX-NEXT: addi sp, sp, -16289; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill290; RV32IZFINX-NEXT: call __fixsfdi291; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload292; RV32IZFINX-NEXT: addi sp, sp, 16293; RV32IZFINX-NEXT: ret294;295; RV64IZFINX-LABEL: fcvt_l_s:296; RV64IZFINX: # %bb.0:297; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz298; RV64IZFINX-NEXT: ret299;300; RV32I-LABEL: fcvt_l_s:301; RV32I: # %bb.0:302; RV32I-NEXT: addi sp, sp, -16303; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill304; RV32I-NEXT: call __fixsfdi305; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload306; RV32I-NEXT: addi sp, sp, 16307; RV32I-NEXT: ret308;309; RV64I-LABEL: fcvt_l_s:310; RV64I: # %bb.0:311; RV64I-NEXT: addi sp, sp, -16312; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill313; RV64I-NEXT: call __fixsfdi314; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload315; RV64I-NEXT: addi sp, sp, 16316; RV64I-NEXT: ret317 %1 = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %a, metadata !"fpexcept.strict")318 ret i64 %1319}320 321define i64 @fcvt_lu_s(float %a) nounwind strictfp {322; RV32IF-LABEL: fcvt_lu_s:323; RV32IF: # %bb.0:324; RV32IF-NEXT: addi sp, sp, -16325; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill326; RV32IF-NEXT: call __fixunssfdi327; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload328; RV32IF-NEXT: addi sp, sp, 16329; RV32IF-NEXT: ret330;331; RV64IF-LABEL: fcvt_lu_s:332; RV64IF: # %bb.0:333; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz334; RV64IF-NEXT: ret335;336; RV32IZFINX-LABEL: fcvt_lu_s:337; RV32IZFINX: # %bb.0:338; RV32IZFINX-NEXT: addi sp, sp, -16339; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill340; RV32IZFINX-NEXT: call __fixunssfdi341; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload342; RV32IZFINX-NEXT: addi sp, sp, 16343; RV32IZFINX-NEXT: ret344;345; RV64IZFINX-LABEL: fcvt_lu_s:346; RV64IZFINX: # %bb.0:347; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz348; RV64IZFINX-NEXT: ret349;350; RV32I-LABEL: fcvt_lu_s:351; RV32I: # %bb.0:352; RV32I-NEXT: addi sp, sp, -16353; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill354; RV32I-NEXT: call __fixunssfdi355; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload356; RV32I-NEXT: addi sp, sp, 16357; RV32I-NEXT: ret358;359; RV64I-LABEL: fcvt_lu_s:360; RV64I: # %bb.0:361; RV64I-NEXT: addi sp, sp, -16362; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill363; RV64I-NEXT: call __fixunssfdi364; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload365; RV64I-NEXT: addi sp, sp, 16366; RV64I-NEXT: ret367 %1 = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %a, metadata !"fpexcept.strict")368 ret i64 %1369}370 371define float @fcvt_s_l(i64 %a) nounwind strictfp {372; RV32IF-LABEL: fcvt_s_l:373; RV32IF: # %bb.0:374; RV32IF-NEXT: addi sp, sp, -16375; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill376; RV32IF-NEXT: call __floatdisf377; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload378; RV32IF-NEXT: addi sp, sp, 16379; RV32IF-NEXT: ret380;381; RV64IF-LABEL: fcvt_s_l:382; RV64IF: # %bb.0:383; RV64IF-NEXT: fcvt.s.l fa0, a0384; RV64IF-NEXT: ret385;386; RV32IZFINX-LABEL: fcvt_s_l:387; RV32IZFINX: # %bb.0:388; RV32IZFINX-NEXT: addi sp, sp, -16389; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill390; RV32IZFINX-NEXT: call __floatdisf391; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload392; RV32IZFINX-NEXT: addi sp, sp, 16393; RV32IZFINX-NEXT: ret394;395; RV64IZFINX-LABEL: fcvt_s_l:396; RV64IZFINX: # %bb.0:397; RV64IZFINX-NEXT: fcvt.s.l a0, a0398; RV64IZFINX-NEXT: ret399;400; RV32I-LABEL: fcvt_s_l:401; RV32I: # %bb.0:402; RV32I-NEXT: addi sp, sp, -16403; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill404; RV32I-NEXT: call __floatdisf405; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload406; RV32I-NEXT: addi sp, sp, 16407; RV32I-NEXT: ret408;409; RV64I-LABEL: fcvt_s_l:410; RV64I: # %bb.0:411; RV64I-NEXT: addi sp, sp, -16412; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill413; RV64I-NEXT: call __floatdisf414; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload415; RV64I-NEXT: addi sp, sp, 16416; RV64I-NEXT: ret417 %1 = call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")418 ret float %1419}420 421define float @fcvt_s_lu(i64 %a) nounwind strictfp {422; RV32IF-LABEL: fcvt_s_lu:423; RV32IF: # %bb.0:424; RV32IF-NEXT: addi sp, sp, -16425; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill426; RV32IF-NEXT: call __floatundisf427; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload428; RV32IF-NEXT: addi sp, sp, 16429; RV32IF-NEXT: ret430;431; RV64IF-LABEL: fcvt_s_lu:432; RV64IF: # %bb.0:433; RV64IF-NEXT: fcvt.s.lu fa0, a0434; RV64IF-NEXT: ret435;436; RV32IZFINX-LABEL: fcvt_s_lu:437; RV32IZFINX: # %bb.0:438; RV32IZFINX-NEXT: addi sp, sp, -16439; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill440; RV32IZFINX-NEXT: call __floatundisf441; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload442; RV32IZFINX-NEXT: addi sp, sp, 16443; RV32IZFINX-NEXT: ret444;445; RV64IZFINX-LABEL: fcvt_s_lu:446; RV64IZFINX: # %bb.0:447; RV64IZFINX-NEXT: fcvt.s.lu a0, a0448; RV64IZFINX-NEXT: ret449;450; RV32I-LABEL: fcvt_s_lu:451; RV32I: # %bb.0:452; RV32I-NEXT: addi sp, sp, -16453; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill454; RV32I-NEXT: call __floatundisf455; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload456; RV32I-NEXT: addi sp, sp, 16457; RV32I-NEXT: ret458;459; RV64I-LABEL: fcvt_s_lu:460; RV64I: # %bb.0:461; RV64I-NEXT: addi sp, sp, -16462; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill463; RV64I-NEXT: call __floatundisf464; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload465; RV64I-NEXT: addi sp, sp, 16466; RV64I-NEXT: ret467 %1 = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")468 ret float %1469}470 471define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp {472; CHECKIF-LABEL: fcvt_s_w_i8:473; CHECKIF: # %bb.0:474; CHECKIF-NEXT: fcvt.s.w fa0, a0475; CHECKIF-NEXT: ret476;477; CHECKIZFINX-LABEL: fcvt_s_w_i8:478; CHECKIZFINX: # %bb.0:479; CHECKIZFINX-NEXT: fcvt.s.w a0, a0480; CHECKIZFINX-NEXT: ret481;482; RV32I-LABEL: fcvt_s_w_i8:483; RV32I: # %bb.0:484; RV32I-NEXT: addi sp, sp, -16485; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill486; RV32I-NEXT: call __floatsisf487; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload488; RV32I-NEXT: addi sp, sp, 16489; RV32I-NEXT: ret490;491; RV64I-LABEL: fcvt_s_w_i8:492; RV64I: # %bb.0:493; RV64I-NEXT: addi sp, sp, -16494; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill495; RV64I-NEXT: call __floatsisf496; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload497; RV64I-NEXT: addi sp, sp, 16498; RV64I-NEXT: ret499 %1 = call float @llvm.experimental.constrained.sitofp.f32.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")500 ret float %1501}502 503define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp {504; CHECKIF-LABEL: fcvt_s_wu_i8:505; CHECKIF: # %bb.0:506; CHECKIF-NEXT: fcvt.s.wu fa0, a0507; CHECKIF-NEXT: ret508;509; CHECKIZFINX-LABEL: fcvt_s_wu_i8:510; CHECKIZFINX: # %bb.0:511; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0512; CHECKIZFINX-NEXT: ret513;514; RV32I-LABEL: fcvt_s_wu_i8:515; RV32I: # %bb.0:516; RV32I-NEXT: addi sp, sp, -16517; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill518; RV32I-NEXT: call __floatunsisf519; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload520; RV32I-NEXT: addi sp, sp, 16521; RV32I-NEXT: ret522;523; RV64I-LABEL: fcvt_s_wu_i8:524; RV64I: # %bb.0:525; RV64I-NEXT: addi sp, sp, -16526; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill527; RV64I-NEXT: call __floatunsisf528; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload529; RV64I-NEXT: addi sp, sp, 16530; RV64I-NEXT: ret531 %1 = call float @llvm.experimental.constrained.uitofp.f32.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")532 ret float %1533}534 535define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp {536; CHECKIF-LABEL: fcvt_s_w_i16:537; CHECKIF: # %bb.0:538; CHECKIF-NEXT: fcvt.s.w fa0, a0539; CHECKIF-NEXT: ret540;541; CHECKIZFINX-LABEL: fcvt_s_w_i16:542; CHECKIZFINX: # %bb.0:543; CHECKIZFINX-NEXT: fcvt.s.w a0, a0544; CHECKIZFINX-NEXT: ret545;546; RV32I-LABEL: fcvt_s_w_i16:547; RV32I: # %bb.0:548; RV32I-NEXT: addi sp, sp, -16549; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill550; RV32I-NEXT: call __floatsisf551; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload552; RV32I-NEXT: addi sp, sp, 16553; RV32I-NEXT: ret554;555; RV64I-LABEL: fcvt_s_w_i16:556; RV64I: # %bb.0:557; RV64I-NEXT: addi sp, sp, -16558; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill559; RV64I-NEXT: call __floatsisf560; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload561; RV64I-NEXT: addi sp, sp, 16562; RV64I-NEXT: ret563 %1 = call float @llvm.experimental.constrained.sitofp.f32.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")564 ret float %1565}566 567define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp {568; CHECKIF-LABEL: fcvt_s_wu_i16:569; CHECKIF: # %bb.0:570; CHECKIF-NEXT: fcvt.s.wu fa0, a0571; CHECKIF-NEXT: ret572;573; CHECKIZFINX-LABEL: fcvt_s_wu_i16:574; CHECKIZFINX: # %bb.0:575; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0576; CHECKIZFINX-NEXT: ret577;578; RV32I-LABEL: fcvt_s_wu_i16:579; RV32I: # %bb.0:580; RV32I-NEXT: addi sp, sp, -16581; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill582; RV32I-NEXT: call __floatunsisf583; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload584; RV32I-NEXT: addi sp, sp, 16585; RV32I-NEXT: ret586;587; RV64I-LABEL: fcvt_s_wu_i16:588; RV64I: # %bb.0:589; RV64I-NEXT: addi sp, sp, -16590; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill591; RV64I-NEXT: call __floatunsisf592; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload593; RV64I-NEXT: addi sp, sp, 16594; RV64I-NEXT: ret595 %1 = call float @llvm.experimental.constrained.uitofp.f32.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")596 ret float %1597}598 599; Make sure we select W version of addi on RV64.600define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind strictfp {601; RV32IF-LABEL: fcvt_s_w_demanded_bits:602; RV32IF: # %bb.0:603; RV32IF-NEXT: addi a0, a0, 1604; RV32IF-NEXT: fcvt.s.w fa5, a0605; RV32IF-NEXT: fsw fa5, 0(a1)606; RV32IF-NEXT: ret607;608; RV64IF-LABEL: fcvt_s_w_demanded_bits:609; RV64IF: # %bb.0:610; RV64IF-NEXT: addiw a0, a0, 1611; RV64IF-NEXT: fcvt.s.w fa5, a0612; RV64IF-NEXT: fsw fa5, 0(a1)613; RV64IF-NEXT: ret614;615; RV32IZFINX-LABEL: fcvt_s_w_demanded_bits:616; RV32IZFINX: # %bb.0:617; RV32IZFINX-NEXT: addi a0, a0, 1618; RV32IZFINX-NEXT: fcvt.s.w a2, a0619; RV32IZFINX-NEXT: sw a2, 0(a1)620; RV32IZFINX-NEXT: ret621;622; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits:623; RV64IZFINX: # %bb.0:624; RV64IZFINX-NEXT: addiw a0, a0, 1625; RV64IZFINX-NEXT: fcvt.s.w a2, a0626; RV64IZFINX-NEXT: sw a2, 0(a1)627; RV64IZFINX-NEXT: ret628;629; RV32I-LABEL: fcvt_s_w_demanded_bits:630; RV32I: # %bb.0:631; RV32I-NEXT: addi sp, sp, -16632; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill633; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill634; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill635; RV32I-NEXT: mv s0, a1636; RV32I-NEXT: addi s1, a0, 1637; RV32I-NEXT: mv a0, s1638; RV32I-NEXT: call __floatsisf639; RV32I-NEXT: sw a0, 0(s0)640; RV32I-NEXT: mv a0, s1641; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload642; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload643; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload644; RV32I-NEXT: addi sp, sp, 16645; RV32I-NEXT: ret646;647; RV64I-LABEL: fcvt_s_w_demanded_bits:648; RV64I: # %bb.0:649; RV64I-NEXT: addi sp, sp, -32650; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill651; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill652; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill653; RV64I-NEXT: mv s0, a1654; RV64I-NEXT: addiw s1, a0, 1655; RV64I-NEXT: mv a0, s1656; RV64I-NEXT: call __floatsisf657; RV64I-NEXT: sw a0, 0(s0)658; RV64I-NEXT: mv a0, s1659; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload660; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload661; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload662; RV64I-NEXT: addi sp, sp, 32663; RV64I-NEXT: ret664 %3 = add i32 %0, 1665 %4 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict")666 store float %4, ptr %1, align 4667 ret i32 %3668}669 670; Make sure we select W version of addi on RV64.671define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind strictfp {672; RV32IF-LABEL: fcvt_s_wu_demanded_bits:673; RV32IF: # %bb.0:674; RV32IF-NEXT: addi a0, a0, 1675; RV32IF-NEXT: fcvt.s.wu fa5, a0676; RV32IF-NEXT: fsw fa5, 0(a1)677; RV32IF-NEXT: ret678;679; RV64IF-LABEL: fcvt_s_wu_demanded_bits:680; RV64IF: # %bb.0:681; RV64IF-NEXT: addiw a0, a0, 1682; RV64IF-NEXT: fcvt.s.wu fa5, a0683; RV64IF-NEXT: fsw fa5, 0(a1)684; RV64IF-NEXT: ret685;686; RV32IZFINX-LABEL: fcvt_s_wu_demanded_bits:687; RV32IZFINX: # %bb.0:688; RV32IZFINX-NEXT: addi a0, a0, 1689; RV32IZFINX-NEXT: fcvt.s.wu a2, a0690; RV32IZFINX-NEXT: sw a2, 0(a1)691; RV32IZFINX-NEXT: ret692;693; RV64IZFINX-LABEL: fcvt_s_wu_demanded_bits:694; RV64IZFINX: # %bb.0:695; RV64IZFINX-NEXT: addiw a0, a0, 1696; RV64IZFINX-NEXT: fcvt.s.wu a2, a0697; RV64IZFINX-NEXT: sw a2, 0(a1)698; RV64IZFINX-NEXT: ret699;700; RV32I-LABEL: fcvt_s_wu_demanded_bits:701; RV32I: # %bb.0:702; RV32I-NEXT: addi sp, sp, -16703; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill704; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill705; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill706; RV32I-NEXT: mv s0, a1707; RV32I-NEXT: addi s1, a0, 1708; RV32I-NEXT: mv a0, s1709; RV32I-NEXT: call __floatunsisf710; RV32I-NEXT: sw a0, 0(s0)711; RV32I-NEXT: mv a0, s1712; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload713; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload714; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload715; RV32I-NEXT: addi sp, sp, 16716; RV32I-NEXT: ret717;718; RV64I-LABEL: fcvt_s_wu_demanded_bits:719; RV64I: # %bb.0:720; RV64I-NEXT: addi sp, sp, -32721; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill722; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill723; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill724; RV64I-NEXT: mv s0, a1725; RV64I-NEXT: addiw s1, a0, 1726; RV64I-NEXT: mv a0, s1727; RV64I-NEXT: call __floatunsisf728; RV64I-NEXT: sw a0, 0(s0)729; RV64I-NEXT: mv a0, s1730; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload731; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload732; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload733; RV64I-NEXT: addi sp, sp, 32734; RV64I-NEXT: ret735 %3 = add i32 %0, 1736 %4 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict")737 store float %4, ptr %1, align 4738 ret i32 %3739}740